From 2673e2313730678cd84dd97eb1e03b236b3fdb24 Mon Sep 17 00:00:00 2001 From: Jeevaha Coelho Date: Wed, 16 Dec 2020 05:21:57 -0800 Subject: [PATCH] FIxed PC! --- inputs/beq/beq-2.ref.txt | 2 +- rtl/mips_cpu_control.v | 2 +- rtl/mips_cpu_cpc.v | 35 +++++++++++++++ rtl/mips_cpu_harvard.v | 4 +- rtl/mips_cpu_npc.v | 27 ++++++++++++ rtl/mips_cpu_pc.v | 93 +++++++++++++++++++--------------------- 6 files changed, 111 insertions(+), 52 deletions(-) create mode 100644 rtl/mips_cpu_cpc.v create mode 100644 rtl/mips_cpu_npc.v diff --git a/inputs/beq/beq-2.ref.txt b/inputs/beq/beq-2.ref.txt index bf0d87a..60d3b2f 100644 --- a/inputs/beq/beq-2.ref.txt +++ b/inputs/beq/beq-2.ref.txt @@ -1 +1 @@ -4 \ No newline at end of file +15 diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index d11886c..b78c885 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -114,7 +114,7 @@ always @(*) begin CtrlMemRead = 1;//Memory is read enabled CtrlMemtoReg = 3'd1;//write data port of regfile is fed from data memory $display("Memory read enabled"); - end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))begin + end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==LUI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))begin CtrlMemRead = 0;//Memory is read disabled CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes $display("Memory read disabled"); diff --git a/rtl/mips_cpu_cpc.v b/rtl/mips_cpu_cpc.v new file mode 100644 index 0000000..0b649df --- /dev/null +++ b/rtl/mips_cpu_cpc.v @@ -0,0 +1,35 @@ +module mips_cpu_cpc( +input logic clk, +input logic rst, +input logic[31:0] cpc_in, +output logic[31:0] cpc_out, +output logic active +); + +reg[31:0] cpc_curr; +reg is_active; + +initial begin + cpc_curr = 32'hBFC00000; +end // initial + +always_comb begin + if (rst) begin + cpc_curr = 32'hBFC00000; + is_active = 1; + end else begin + cpc_curr = cpc_in; + end + + if(cpc_in == 32'd0)begin + is_active = 0; + end + +end + +always_ff @(posedge clk) begin + cpc_out <= cpc_curr; + active <= is_active; +end + +endmodule // pc \ No newline at end of file diff --git a/rtl/mips_cpu_harvard.v b/rtl/mips_cpu_harvard.v index aa0e2f2..3debd63 100644 --- a/rtl/mips_cpu_harvard.v +++ b/rtl/mips_cpu_harvard.v @@ -88,8 +88,8 @@ mips_cpu_pc pc( //PC inputs .clk(clk),//clk taken from the Standard signals .rst(reset),//clk taken from the Standard signals - .instr(instr_readdata), //needed for branches and jumps - .reg_readdata(out_readdata1), //needed for jump register + .Instr(instr_readdata), //needed for branches and jumps + .JumpReg(out_readdata1), //needed for jump register .pc_ctrl(out_PC), //PC outputs .pc_out(out_pc_out),//What the pc outputs at every clock edge that goes into the 'Read address' port of Instruction Memory. diff --git a/rtl/mips_cpu_npc.v b/rtl/mips_cpu_npc.v new file mode 100644 index 0000000..53cc2ae --- /dev/null +++ b/rtl/mips_cpu_npc.v @@ -0,0 +1,27 @@ +module mips_cpu_npc( +input logic clk, +input logic rst, +input logic[31:0] npc_in, +output logic[31:0] npc_out +); + +reg[31:0] npc_curr; + +initial begin + npc_curr = (32'hBFC00000 + 32'd4); +end // initial + +always_comb begin + if (rst) begin + npc_curr = (32'hBFC00000 + 32'd4); + end else begin + npc_curr = npc_in; + end + +end + +always_ff @(posedge clk) begin + npc_out <= npc_curr; +end + +endmodule // pc \ No newline at end of file diff --git a/rtl/mips_cpu_pc.v b/rtl/mips_cpu_pc.v index e6bee1b..fad1b8c 100644 --- a/rtl/mips_cpu_pc.v +++ b/rtl/mips_cpu_pc.v @@ -1,56 +1,53 @@ module mips_cpu_pc( - input logic clk, - input logic rst, - input logic[1:0] pc_ctrl, - input logic[31:0] instr, - input logic[31:0] reg_readdata, - output logic[31:0] pc_out, - output logic active +input logic clk, +input logic rst, +input logic[31:0] Instr, +input logic[31:0] JumpReg, +input logic[1:0] pc_ctrl, +output logic[31:0] pc_out, +output logic active ); -reg [31:0] pc_next, pc_lit_next, pc_next_next; +logic[31:0] out_cpc_out; +logic[31:0] out_npc_out; +logic[31:0] in_npc_in; -initial begin - pc_out = 32'hBFC00000; - pc_next = pc_out + 32'd4; - -end - -assign pc_lit_next = pc_out + 32'd4; - -always_ff @(posedge clk) begin - if (rst) begin - active <= 1; - pc_out <= 32'hBFC00000; - end else begin - if(pc_out == 32'd0) begin - active <= 0; - end - pc_out <= pc_next; - pc_next <= pc_next_next; - end -end +assign pc_out = out_cpc_out; always @(*) begin - case(pc_ctrl) - 2'd1: begin // Branch - pc_next_next = pc_out + 32'd4 + {{14{instr[15]}},instr[15:0],2'b00}; - end - 2'd2: begin // Jump - pc_next_next = {pc_lit_next[31:28], instr[25:0], 2'b00}; - $display("JUMPING"); - $display("pc_lit_next: %h", pc_lit_next[31:28]); - $display("instr: %b", instr[25:0]); - $display("%h",pc_next); - end - 2'd3: begin // Jump using Register - pc_next_next = reg_readdata; - $display("REGREADEADTAATATAT %h", reg_readdata); - end - default: begin - pc_next_next = pc_out + 32'd4; - end - endcase + case(pc_ctrl) + 2'd0: begin + in_npc_in = out_npc_out + 32'd4;//No branch or jump or load. + end + 2'd1: begin + in_npc_in = out_npc_out + {{14{Instr[15]}}, Instr[15:0], 2'b00}; + end + 2'd2: begin + in_npc_in = {out_npc_out[31:28], Instr[25:0], 2'b00}; + end + 2'd3: begin + in_npc_in = JumpReg; + end + endcase end -endmodule // pc \ No newline at end of file +mips_cpu_cpc cpc( +//Inputs for cpc + .clk(clk), + .rst(rst), + .cpc_in(out_npc_out), +//Outputs for cpc + .cpc_out(out_cpc_out), + .active(active) +); + +mips_cpu_npc npc( +//Inputs for npc + .clk(clk), + .rst(rst), + .npc_in(in_npc_in), +//Outputs for npc + .npc_out(out_npc_out) +); + +endmodule \ No newline at end of file