mirror of
https://github.com/supleed2/ELEC50010-IAC-CW.git
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Merge pull request #2 from supleed2/bus_wrapper
Merge Bus Version and updated testcases to Main
This commit is contained in:
GitHub
commit
099540f6ec
1
.gitignore
vendored
1
.gitignore
vendored
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@ -3,5 +3,6 @@ exec/*
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*.log.txt
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*.out.txt
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mips_cpu_harvard.vcd
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mips_cpu_bus.vcd
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.DS_Store
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inputs/.DS_Store
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@ -1,7 +1,6 @@
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3C041234
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34045678
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3C05BFC0
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3405001C
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3405101C
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A0A40000
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80A20000
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00000008
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00000008
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@ -1,7 +1,6 @@
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3C041234
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34045678
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3C05BFC0
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3405001C
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3405101C
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A4A40000
|
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84A40000
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00000008
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84A20000
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00000008
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1
inputs/sh/sh-2.ref.txt
Normal file
1
inputs/sh/sh-2.ref.txt
Normal file
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@ -0,0 +1 @@
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22136
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6
inputs/sh/sh-2.txt
Normal file
6
inputs/sh/sh-2.txt
Normal file
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@ -0,0 +1,6 @@
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3C041234
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34045678
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3405101C
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A4A40000
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8CA20000
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00000008
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File diff suppressed because it is too large
Load diff
231
rtl/mips_cpu_bus.v
Normal file
231
rtl/mips_cpu_bus.v
Normal file
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@ -0,0 +1,231 @@
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module mips_cpu_bus(
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/* Standard signals */
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input logic clk,
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input logic reset,
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output logic active,
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output logic[31:0] register_v0,
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/* Avalon memory mapped bus controller (master) */
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output logic[31:0] address,
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output logic write,
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output logic read,
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input logic waitrequest,
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output logic[31:0] writedata,
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output logic[3:0] byteenable,
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input logic[31:0] readdata
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);
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logic[1:0] state; // current state of cpu within cycle
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logic[1:0] n_state; // state to be set at next clk edge
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logic[31:0] instr_reg; // instruction register / single-word cache for current instruction
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logic clk_internal; // modulated clock to be passed to harvard cpu
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logic[31:0] harvard_instr_address; // instr addr from pc
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logic harvard_read; // harvard cpu read flag
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logic harvard_write; // harvard cpu write flag
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logic[31:0] harvard_data_address; // data addr from ALU
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logic[31:0] harvard_readdata; // <= data read from Avalon MM Device
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logic[31:0] harvard_writedata; // data to be written to Avalon MM Device
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logic[3:0] write_byteenable; // byteenable calculator for partial write
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logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly
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logic partial_write; // flag to control datapath when doing a partial write
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logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte)
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logic[31:0] write_data_address; // modified data address for partial writes
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logic clk_enable; // unused floating wire
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initial begin
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clk_internal = 1'b0;
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n_state = 2'b00;
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state = 2'b00;
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instr_reg = 32'h00000000;
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address = 32'h00000000;
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write = 1'b0;
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read = 1'b0;
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writedata = 32'h00000000;
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byteenable = 4'b0000;
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clk_state = 0;
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end
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always_ff @(negedge reset) begin // kickstart clock after reset
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clk_internal <= 1'b1;
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state <= 2'b00;
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end
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always_ff @(posedge clk) begin // CLK Rising Edge
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if (!waitrequest && !clk_state) begin
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case (n_state)
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2'b00: begin // fetch
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clk_internal <= 1'b1;
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state <= 2'b00;
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end
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2'b01: begin // execute
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state <= 2'b01;
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instr_reg <= readdata;
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end
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2'b10: begin // read
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state <= 2'b10;
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end
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2'b11: begin // write
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state <= 2'b11;
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end
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endcase // state
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end
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clk_state <= 1'b1;
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end
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always_ff @(negedge clk) begin // CLK Falling Edge
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if (!waitrequest && clk_state) begin
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case (state)
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2'b00: begin // nothing happens on fetch negedge
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end
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2'b01: begin // execute negedge
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if (!harvard_read && !harvard_write) begin // instruction complete, trigger writeback
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clk_internal <= 1'b0;
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end // otherwise do nothing
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end
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2'b10: begin
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clk_internal <= 1'b0;
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end
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2'b11: begin
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clk_internal <= 1'b0;
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end
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endcase
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end
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clk_state <= 1'b0;
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end
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always @(*) begin
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case (instr_reg[31:26])
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6'b101000: begin // Store Byte
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partial_write = 1'b1;
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case (harvard_data_address[1:0])
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2'b00: begin
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partial_writedata = {{24{1'b0}}, harvard_writedata[7:0]};
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write_byteenable = 4'b0001;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b01: begin
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partial_writedata = {{16{1'b0}}, harvard_writedata[7:0], {8{1'b0}}};
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write_byteenable = 4'b0010;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b10: begin
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partial_writedata = {{8{1'b0}}, harvard_writedata[7:0], {16{1'b0}}};
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write_byteenable = 4'b0100;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b11: begin
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partial_writedata = {harvard_writedata[7:0], {24{1'b0}}};
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write_byteenable = 4'b1000;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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endcase
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end
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6'b101001: begin // Store Halfword
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partial_write = 1'b1;
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case (harvard_data_address[1:0])
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2'b00: begin
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partial_writedata = {{16{1'b0}}, harvard_writedata[15:0]};
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write_byteenable = 4'b0011;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b01: begin // halfword address must be matrually aligned, last bit must be 0
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partial_writedata = 32'hxxxxxxxx;
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write_byteenable = 4'bxxxx;
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write_data_address = 32'hxxxxxxxx;
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end
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2'b10: begin
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partial_writedata = {harvard_writedata[15:0], {16{1'b0}}};
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write_byteenable = 4'b1100;
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write_data_address = {harvard_data_address[31:2], 2'b00};
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end
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2'b11: begin // halfword address must be matrually aligned, last bit must be 0
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partial_writedata = 32'hxxxxxxxx;
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write_byteenable = 4'bxxxx;
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write_data_address = 32'hxxxxxxxx;
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end
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endcase
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end
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default: begin // Store Word OR All other instructions (These flags are ignored outside the write state)
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partial_write = 1'b0;
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partial_writedata = 32'h00000000;
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write_byteenable = 4'b1111;
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write_data_address = harvard_data_address;
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end
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endcase
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end
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always_comb begin
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if (reset) begin
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clk_internal = 1'b0;
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n_state = 2'b00;
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state = 2'b00;
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instr_reg = 32'h00000000;
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address = 32'h00000000;
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write = 1'b0;
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read = 1'b0;
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writedata = 32'h00000000;
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byteenable = 4'b0000;
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end else begin
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case (state)
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2'b00: begin // connecting wires when in fetch state
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address = harvard_instr_address;
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read = 1'b1;
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write = 1'b0;
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byteenable = 4'b1111;
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harvard_readdata = 32'h00000000;
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writedata = 32'h00000000;
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n_state = 2'b01;
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end
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2'b01: begin // connecting wires when in execute state
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address = 32'h00000000;
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read = 1'b0;
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write = 1'b0;
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byteenable = 4'b0000;
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harvard_readdata = 32'h00000000;
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writedata = 32'h00000000;
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if (harvard_read) begin
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n_state = 2'b10; // next state is read
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end else if (harvard_write) begin
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n_state = 2'b11; // next state is write
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end else begin
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n_state = 2'b00; // next state is fetch
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end
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end
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2'b10: begin // connecting wires when in read state
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address = harvard_data_address;
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read = clk_internal ? 1'b1 : 1'b0;
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write = 1'b0;
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byteenable = 4'b1111;
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harvard_readdata = readdata;
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writedata = 32'h00000000;
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n_state = 2'b00;
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end
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2'b11: begin // connecting wires when in write state
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address = write_data_address;
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read = 1'b0;
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write = 1'b1;
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byteenable = write_byteenable;
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harvard_readdata = 32'h00000000;
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writedata = partial_write ? partial_writedata : harvard_writedata;
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n_state = 2'b00;
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end
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endcase // state
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end
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end
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mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper
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.clk(clk_internal), // modulated clock input to allow waiting for valid data from memory, input
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.reset(reset), // CPU reset, input
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.active(active), // Is CPU active, output
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.register_v0(register_v0), // $2 / $v0 debug bus, output
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.clk_enable(clk_enable), // unused clock enable, input
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.instr_address(harvard_instr_address), // instr addr from pc, output
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.instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input
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.data_address(harvard_data_address), // harvard data memory address, output
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.data_write(harvard_write), // harvard write flag, output
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.data_read(harvard_read), // harvard read flag, output
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.data_writedata(harvard_writedata), // data output from regfile readport2, output
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.data_readdata(harvard_readdata) // data in from read instruction, input
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);
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endmodule
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@ -117,6 +117,8 @@ always @(*) begin
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CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi
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end else if ((op==SPECIAL)&&(funct == MFLO))begin
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CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo
|
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end else if (((op==SPECIAL)&&(funct == JR)) || (op == BEQ) || (op==SW) ||((op==REGIMM)&&(rt==BGEZ)) || (op==BGTZ) || ((op==REGIMM)&&(rt==BLTZ)) || (op==BLEZ) || (op==BNE) || (op==J) || ((op==SPECIAL)&&(funct==MTHI)) || ((op==SPECIAL)&&(funct==MTLO)) || ((op==SPECIAL)&&(funct==MULT)) || ((op==SPECIAL)&&(funct==MULTU)) || ((op==SPECIAL)&&(funct==DIV)) || ((op==SPECIAL)&&(funct==DIVU)) || (op==SB) || (op==SH))begin
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CtrlMemRead = 0;//Read disabled during jump
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end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
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//CtrlALUOp Logic
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|
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@ -9,6 +9,7 @@ reg[31:0] npc_curr;
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|||
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initial begin
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npc_curr = (32'hBFC00000 + 32'd4);
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npc_out = 32'hBFC00000;
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end // initial
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always_comb begin
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||||
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@ -1,4 +1,60 @@
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#!/bin/bash
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||||
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||||
# should not create any files in the rtl dir
|
||||
# but auxiliary files / dirs can be utilised
|
||||
SRC_DIR=${1?Error: no source directory given in argument};
|
||||
SRC=$(find ./${SRC_DIR}/*);
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SRC_TEMP="";
|
||||
for src in ${SRC}
|
||||
do
|
||||
SRC_TEMP+=${src}" ";
|
||||
done
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||||
SRC=${SRC_TEMP};
|
||||
|
||||
|
||||
INSTR=${2:-"No instruction specified: running all testcases"};
|
||||
|
||||
if [[ ${INSTR} == "No instruction specified: running all testcases" ]];
|
||||
then
|
||||
for DIR in inputs/*/
|
||||
do
|
||||
DIR=$(basename ${DIR});
|
||||
LOOP=$(find inputs/${DIR}/* ! -name '*ref*' ! -name '*log*' ! -name '*data*' ! -name '*out*');
|
||||
for TESTCASE in ${LOOP}
|
||||
do
|
||||
TESTCASE=$([[ ${TESTCASE} =~ /([^./]+)\. ]] && echo "${BASH_REMATCH[1]}");
|
||||
iverilog -Wall -g2012 \
|
||||
-s mips_cpu_bus_tb \
|
||||
-P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \
|
||||
-P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \
|
||||
-o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \
|
||||
${SRC} 2> /dev/null
|
||||
./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)
|
||||
echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference
|
||||
if diff -w ./inputs/${DIR}/${TESTCASE}.out.txt ./inputs/${DIR}/${TESTCASE}.ref.txt &> /dev/null # compare
|
||||
then
|
||||
echo ${TESTCASE} ${DIR} "Pass";
|
||||
else
|
||||
printf '%s %s %s%d %s%d%s\n' "${TESTCASE}" "${DIR}" "Fail Output=" "$(tail -1 ./inputs/${DIR}/${TESTCASE}.out.txt)" "Ref=" "$(tail -1 ./inputs/${DIR}/${TESTCASE}.ref.txt)" 2> /dev/null;
|
||||
fi
|
||||
done
|
||||
done
|
||||
else
|
||||
LOOP=$(find inputs/${INSTR}/* ! -name '*ref*' ! -name '*log*' ! -name '*data*' ! -name '*out*');
|
||||
for TESTCASE in ${LOOP}
|
||||
do
|
||||
TESTCASE=$([[ ${TESTCASE} =~ /([^./]+)\. ]] && echo "${BASH_REMATCH[1]}");
|
||||
iverilog -Wall -g2012 \
|
||||
-s mips_cpu_bus_tb \
|
||||
-P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \
|
||||
-P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
|
||||
-o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \
|
||||
${SRC} 2> /dev/null
|
||||
./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)
|
||||
echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference
|
||||
if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt &> /dev/null # compare
|
||||
then
|
||||
echo ${TESTCASE} ${INSTR} "Pass";
|
||||
else
|
||||
printf '%s %s %s%d %s%d%s\n' "${TESTCASE}" "${INSTR}" "Fail Output=" "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.out.txt)" "Ref=" "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.ref.txt)" 2> /dev/null;
|
||||
fi
|
||||
done
|
||||
fi
|
||||
|
|
@ -47,7 +47,7 @@ else
|
|||
-P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \
|
||||
-P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \
|
||||
-o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\
|
||||
${SRC} #2> /dev/null
|
||||
${SRC} 2> /dev/null
|
||||
./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display)
|
||||
echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference
|
||||
if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt &> /dev/null # compare
|
||||
|
|
|
|||
100
testbench/mips_cpu_bus_memory.v
Normal file
100
testbench/mips_cpu_bus_memory.v
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave)
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic[31:0] address,
|
||||
input logic write,
|
||||
input logic read,
|
||||
output logic waitrequest,
|
||||
input logic[31:0] writedata,
|
||||
input logic[3:0] byteenable,
|
||||
output logic[31:0] readdata
|
||||
);
|
||||
|
||||
parameter INSTR_INIT_FILE = "";
|
||||
parameter DATA_INIT_FILE = "";
|
||||
|
||||
logic [31:0] data_memory [0:63]; // location 0x00001000 onwards
|
||||
logic [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards
|
||||
|
||||
initial begin
|
||||
for (integer i=0; i<$size(data_memory); i++) begin //Initialise data to zero by default
|
||||
data_memory[i] = 0;
|
||||
end
|
||||
|
||||
for (integer i=0; i<$size(instr_memory); i++) begin //Initialise instr to zero by default
|
||||
instr_memory[i] = 0;
|
||||
end
|
||||
|
||||
if (INSTR_INIT_FILE != "") begin //Load instr contents from file if specified
|
||||
$display("RAM: Loading RAM contents from %s", INSTR_INIT_FILE);
|
||||
$readmemh(INSTR_INIT_FILE, instr_memory);
|
||||
end
|
||||
|
||||
for (integer i = 0; i<$size(instr_memory); i++) begin //Read out instr contents to log
|
||||
$display("byte +%h: %h", 32'hBFC00000+i*4, instr_memory[i]);
|
||||
end
|
||||
|
||||
if (DATA_INIT_FILE != "") begin //Load data contents from file if specified
|
||||
$display("MEM: Loading MEM contents from %s", DATA_INIT_FILE);
|
||||
$readmemh(DATA_INIT_FILE, data_memory);
|
||||
end else begin
|
||||
$display("MEM FILE NOT GIVEN");
|
||||
end
|
||||
|
||||
for (integer i = 0; i<$size(data_memory); i++) begin //Read out data contents to log
|
||||
$display("byte +%h: %h", 32'h00001000+i*4, data_memory[i]);
|
||||
end
|
||||
|
||||
waitrequest = 1'b0; // set waitrequest low to begin
|
||||
readdata = 32'h00000000; // set readdata low to begin
|
||||
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
if (reset) begin
|
||||
waitrequest = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge read or posedge write) begin
|
||||
waitrequest <= 1'b1;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (waitrequest) begin
|
||||
if (read) begin
|
||||
if (address >= 32'hBFC00000) begin // instruction read
|
||||
readdata <= instr_memory[{address-32'hBFC00000}>>2];
|
||||
end else if (address >= 32'h00001000) begin // data read
|
||||
readdata <= data_memory[{address-32'h00001000}>>2];
|
||||
end
|
||||
waitrequest <= 1'b0; // end with setting waitrequest low
|
||||
end else if (write) begin
|
||||
if (address >= 32'hBFC00000) begin // writing to instr mem area is invalid
|
||||
$display("Error, write attempted in instr area at address: %h", address);
|
||||
end else if (address >= 32'h00001000) begin // write to data mem
|
||||
if (byteenable[3]) begin // if first byte enabled, write
|
||||
data_memory[{address-32'h00001000}>>2][31:24] <= writedata[31:24];
|
||||
end
|
||||
if (byteenable[2]) begin // if second byte enabled, write
|
||||
data_memory[{address-32'h00001000}>>2][23:16] <= writedata[23:16];
|
||||
end
|
||||
if (byteenable[1]) begin // if third byte enabled, write
|
||||
data_memory[{address-32'h00001000}>>2][15:8] <= writedata[15:8];
|
||||
end
|
||||
if (byteenable[0]) begin // if fourth byte enabled, write
|
||||
data_memory[{address-32'h00001000}>>2][7:0] <= writedata[7:0];
|
||||
end
|
||||
waitrequest <= 1'b0; // end with setting waitrequest low
|
||||
end
|
||||
end else begin
|
||||
waitrequest <= 1'bx;
|
||||
readdata <= 32'hxxxxxxxx;
|
||||
end
|
||||
end else begin
|
||||
waitrequest <= 1'b0;
|
||||
readdata <= 32'h00000000;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,61 +1,80 @@
|
|||
module mips_cpu_bus_tb;
|
||||
timeunit 1ns / 10ps;
|
||||
|
||||
parameter RAM_INIT_FILE = "test/01-binary/countdown.hex.txt";
|
||||
parameter TIMEOUT_CYCLES = 10000;
|
||||
parameter INSTR_INIT_FILE = "";
|
||||
parameter DATA_INIT_FILE = "";
|
||||
parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
logic clk, reset, active, write, read, waitrequest;
|
||||
logic[31:0] address, register_v0, writedata, readdata;
|
||||
logic[3:0] byteenable;
|
||||
|
||||
logic running;
|
||||
mips_cpu_bus_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) memInst( //Avalon memory mapped bus controller (slave)
|
||||
.clk(clk), // clk input to mem
|
||||
.reset(reset), // reset input to stall mem during cpu reset
|
||||
.address(address), // addr input to mem
|
||||
.write(write), // write flag input
|
||||
.read(read), // read flag input
|
||||
.waitrequest(waitrequest), // mem stall output
|
||||
.writedata(writedata), // data to be written
|
||||
.byteenable(byteenable), // byteenable bus for writes
|
||||
.readdata(readdata) // read output port
|
||||
);
|
||||
|
||||
logic[11:0] address;
|
||||
logic write;
|
||||
logic read;
|
||||
logic[15:0] writedata;
|
||||
logic[15:0] readdata;
|
||||
mips_cpu_bus cpuInst(
|
||||
.clk(clk), // clk input to cpu wrapper
|
||||
.reset(reset), // reset input
|
||||
.active(active), // active output flag
|
||||
.register_v0(register_v0), // debug $2 or $v0 output bus
|
||||
.address(address), // mem addr output
|
||||
.write(write), // mem write output flag
|
||||
.read(read), // mem read output flag
|
||||
.waitrequest(waitrequest), // mem stall input flag
|
||||
.writedata(writedata), // data to write to mem output
|
||||
.byteenable(byteenable), // bytes to write output
|
||||
.readdata(readdata) // data from mem input
|
||||
);
|
||||
|
||||
RAM_16x4096_delay1 #(RAM_INIT_FILE) ramInst(clk, address, write, read, writedata, readdata);
|
||||
|
||||
CPU_MU0_delay1 cpuInst(clk, rst, running, address, write, read, writedata, readdata);
|
||||
// Setup and clock
|
||||
initial begin
|
||||
$dumpfile("mips_cpu_bus.vcd");
|
||||
$dumpvars(0,mips_cpu_bus_tb);
|
||||
clk=0;
|
||||
|
||||
// Generate clock
|
||||
initial begin
|
||||
clk=0;
|
||||
|
||||
repeat (TIMEOUT_CYCLES) begin
|
||||
#10;
|
||||
clk = !clk;
|
||||
#10;
|
||||
clk = !clk;
|
||||
end
|
||||
|
||||
$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
|
||||
repeat (TIMEOUT_CYCLES) begin
|
||||
#10;
|
||||
clk = !clk;
|
||||
#10;
|
||||
clk = !clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
rst <= 0;
|
||||
$fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES);
|
||||
end
|
||||
|
||||
initial begin
|
||||
reset <= 1;
|
||||
@(posedge clk);
|
||||
reset <= 0;
|
||||
|
||||
@(posedge clk);
|
||||
assert(active==1)
|
||||
else $display("TB : CPU did not set active=1 after reset.");
|
||||
|
||||
while (active) begin
|
||||
//$display("Clk: %d", clk);
|
||||
@(posedge clk);
|
||||
rst <= 1;
|
||||
|
||||
@(posedge clk);
|
||||
rst <= 0;
|
||||
|
||||
@(posedge clk);
|
||||
assert(running==1)
|
||||
else $display("TB : CPU did not set running=1 after reset.");
|
||||
|
||||
while (running) begin
|
||||
@(posedge clk);
|
||||
end
|
||||
|
||||
$display("TB : finished; running=0");
|
||||
|
||||
$finish;
|
||||
|
||||
//$display("Register v0: %d", register_v0);
|
||||
//$display("Reg File Write data: %d", cpuInst.in_writedata);
|
||||
$display("Reg File Out Read data: %h", cpuInst.mips_cpu_harvard.out_readdata1);
|
||||
$display("Reg File opcode: %b", cpuInst.mips_cpu_harvard.regfile.opcode);
|
||||
//$display("ALU output: %h", cpuInst.out_ALURes);
|
||||
//$display("ALU input B: %h", cpuInst.alu.B);
|
||||
end
|
||||
|
||||
|
||||
@(posedge clk);
|
||||
$display("TB: CPU Halt; active=0");
|
||||
$display("Output:");
|
||||
$display("%d",register_v0);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in a new issue