From 7997076be77f2a1e3cd1d9f03d5200749cb5bb4a Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Fri, 11 Dec 2020 10:56:34 +0000 Subject: [PATCH 01/28] Basic Wrapper, Logic to be added --- rtl/mips_cpu_bus.v | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index 111a7b3..f43174d 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -14,3 +14,34 @@ module mips_cpu_bus( output logic[3:0] byteenable, input logic[31:0] readdata ); + +logic[31:0] instr_reg; // instruction register / single-word cache for current instruction +logic clk_internal; // modulated clock to be passed to harvard cpu + +always_ff @(posedge clk) begin // how/when to pass through negedge? + if (waitrequest) begin //if waitrequest is high, do nothing + end else begin + //update outputs? + end +end + +always_comb begin + +end + +mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper +.clk(clk_internal), // modulated clock input to allow waiting for valid data from memory, input +.reset(reset), // CPU reset, input +.active(active), // Is CPU active, output +.register_v0(register_v0), // $2 / $v0 debug bus, output +.clk_enable(1'b0), // unused clock enable, input +.instr_address(######), // output +.instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input +.data_address(######), // output +.data_write(######), // output +.data_read(######), // output +.data_writedata(######), // output +.data_readdata(######) // input +); + +endmodule : mips_cpu_bus From 714b74ec833cce7f381b84471e4a6a0347f415df Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Fri, 11 Dec 2020 19:13:11 +0000 Subject: [PATCH 02/28] Update mips_cpu_bus.v Added fetch/execute states. All instructions not using data memory should function --- rtl/mips_cpu_bus.v | 86 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 7 deletions(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index f43174d..a2e0792 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -15,18 +15,90 @@ module mips_cpu_bus( input logic[31:0] readdata ); +logic[1:0] state; // current state of cpu within cycle +logic[1:0] n_state; // state to be set at next clk edge logic[31:0] instr_reg; // instruction register / single-word cache for current instruction logic clk_internal; // modulated clock to be passed to harvard cpu +logic[31:0] harvard_instr_address; // instr addr from pc +logic harvard_read; // harvard cpu read flag +logic harvard_write; // harvard cpu write flag -always_ff @(posedge clk) begin // how/when to pass through negedge? - if (waitrequest) begin //if waitrequest is high, do nothing +initial begin + clk_internal = 1'b0; + n_state = 2'b00; + state = 2'b00; + instr_reg = 32'h00000000; + address = 32'h00000000; + write = 1'b0; + read = 1'b0; + writedata = 32'h00000000; + byteenable = 4'b0000; +end + +always_ff @(posedge clk) begin // CLK Rising Edge + if (waitrequest) begin end else begin - //update outputs? + case (n_state) + 2'b00: begin // fetch + clk_internal <= 1'b1; + state <= 2'b00; + end + 2'b01: begin // execute + state <= 2'b10; + instr_reg <= readdata; + end + 2'b10: begin // read + end + 2'b11: begin // write + end + endcase // state end end -always_comb begin +always_ff @(negedge clk) begin // CLK Falling Edge + case (state) + 2'b00: // nothing happens on fetch negedge + 2'b01: begin // execute negedge + if (!harvard_read && !harvard_write) begin // instruction complete, trigger writeback + clk_internal <= 1'b0; + end // otherwise do nothing + end + endcase +end +always_comb begin + if (reset) begin + clk_internal = 1'b0; + n_state = 2'b00; + state = 2'b00; + instr_reg = 32'h00000000; + address = 32'h00000000; + write = 1'b0; + read = 1'b0; + writedata = 32'h00000000; + byteenable = 4'b0000; + end else begin + case (state) + 2'b00: begin + address = harvard_instr_address; + read = 1'b1; + byteenable = 4'b1111; + n_state = 2'b01; + end + 2'b01: begin + address = 32'h00000000; + read = 1'b0; + byteenable = 4'b0000; + if (harvard_read) begin + n_state = 2'b10; // next state is read + end else if (harvard_write) begin + n_state = 2'b11; // next state is write + end else begin + n_state 2'b00; // next state is fetch + end + end + endcase // state + end end mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper @@ -35,11 +107,11 @@ mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper .active(active), // Is CPU active, output .register_v0(register_v0), // $2 / $v0 debug bus, output .clk_enable(1'b0), // unused clock enable, input -.instr_address(######), // output +.instr_address(harvard_instr_address), // instr addr from pc, output .instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input .data_address(######), // output -.data_write(######), // output -.data_read(######), // output +.data_write(harvard_write), // harvard write flag, output +.data_read(harvard_read), // harvard read flag, output .data_writedata(######), // output .data_readdata(######) // input ); From af7645b5b03038e829261ffb47df0bbb4b7d968a Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Fri, 11 Dec 2020 19:45:00 +0000 Subject: [PATCH 03/28] Completed wrapper, to be tested --- rtl/mips_cpu_bus.v | 72 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 56 insertions(+), 16 deletions(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index a2e0792..c11e41c 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -22,6 +22,10 @@ logic clk_internal; // modulated clock to be passed to harvard cpu logic[31:0] harvard_instr_address; // instr addr from pc logic harvard_read; // harvard cpu read flag logic harvard_write; // harvard cpu write flag +logic[31:0] harvard_data_address; // data addr from ALU +logic[31:0] harvard_readdata; // <= data read from Avalon MM Device +logic[3:0] write_byteenable; // byteenable calculator for partial write +logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly initial begin clk_internal = 1'b0; @@ -33,37 +37,49 @@ initial begin read = 1'b0; writedata = 32'h00000000; byteenable = 4'b0000; + clk_state = 0; end always_ff @(posedge clk) begin // CLK Rising Edge - if (waitrequest) begin - end else begin + if (!waitrequest && !clk_state) begin case (n_state) 2'b00: begin // fetch clk_internal <= 1'b1; state <= 2'b00; end 2'b01: begin // execute - state <= 2'b10; + state <= 2'b01; instr_reg <= readdata; end 2'b10: begin // read + state <= 2'b10; end 2'b11: begin // write + state <= 2'b11; end endcase // state end + clk_state <= 1'b1; end always_ff @(negedge clk) begin // CLK Falling Edge - case (state) - 2'b00: // nothing happens on fetch negedge - 2'b01: begin // execute negedge - if (!harvard_read && !harvard_write) begin // instruction complete, trigger writeback + if (!waitrequest && clk_state) begin + case (state) + 2'b00: // nothing happens on fetch negedge + 2'b01: begin // execute negedge + if (!harvard_read && !harvard_write) begin // instruction complete, trigger writeback + clk_internal <= 1'b0; + end // otherwise do nothing + end + 2'b10: begin clk_internal <= 1'b0; - end // otherwise do nothing - end - endcase + end + 2'b11: begin + clk_internal <= 1'b0; + end + endcase + end + clk_state <= 1'b0; end always_comb begin @@ -79,24 +95,48 @@ always_comb begin byteenable = 4'b0000; end else begin case (state) - 2'b00: begin + 2'b00: begin // connecting wires when in fetch state address = harvard_instr_address; read = 1'b1; + write = 1'b0; byteenable = 4'b1111; + harvard_readdata = 32'h00000000; + writedata = 32'h00000000; n_state = 2'b01; end - 2'b01: begin + 2'b01: begin // connecting wires when in execute state address = 32'h00000000; read = 1'b0; + write = 1'b0; byteenable = 4'b0000; + harvard_readdata = 32'h00000000; + writedata = 32'h00000000; if (harvard_read) begin n_state = 2'b10; // next state is read end else if (harvard_write) begin n_state = 2'b11; // next state is write end else begin - n_state 2'b00; // next state is fetch + n_state = 2'b00; // next state is fetch end end + 2'b10: begin // connecting wires when in read state + address = harvard_data_address; + read = 1'b1; + write = 1'b0; + byteenable = 4'b1111; + harvard_readdata = readdata; + writedata = 32'h00000000; + n_state = 2'b00; + end + 2'b11: begin // connecting wires when in write state + address = harvard_data_address; + read = 1'b0; + write = 1'b1; + byteenable = write_byteenable; + harvard_readdata = 32'h00000000; + writedata = harvard_writedata; + n_state = 2'b00; + end endcase // state end end @@ -109,11 +149,11 @@ mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper .clk_enable(1'b0), // unused clock enable, input .instr_address(harvard_instr_address), // instr addr from pc, output .instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input -.data_address(######), // output +.data_address(harvard_data_address), // harvard data memory address, output .data_write(harvard_write), // harvard write flag, output .data_read(harvard_read), // harvard read flag, output -.data_writedata(######), // output -.data_readdata(######) // input +.data_writedata(harvard_writedata), // data output from regfile readport2, output +.data_readdata(harvard_readdata) // data in from read instruction, input ); endmodule : mips_cpu_bus From 50b9dba6515ae072535f5acd45e5c2fb27de9881 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Sat, 12 Dec 2020 16:49:02 +0000 Subject: [PATCH 04/28] Added partial writes SH and SB were not accounted for in previous version, partial reads are handled within regfile --- rtl/mips_cpu_bus.v | 57 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index c11e41c..08f9de9 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -24,8 +24,11 @@ logic harvard_read; // harvard cpu read flag logic harvard_write; // harvard cpu write flag logic[31:0] harvard_data_address; // data addr from ALU logic[31:0] harvard_readdata; // <= data read from Avalon MM Device +logic[31:0] harvard_writedata; // data to be written to Avalon MM Device logic[3:0] write_byteenable; // byteenable calculator for partial write logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly +logic partial_write; // flag to control datapath when doing a partial write +logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte) initial begin clk_internal = 1'b0; @@ -82,6 +85,58 @@ always_ff @(negedge clk) begin // CLK Falling Edge clk_state <= 1'b0; end +always_comb begin + case (instr_reg[31:26]) + 6'b101000: begin // Store Byte + partial_write = 1'b1; + case (harvard_data_address[1:0]) + 2'b00: begin + partial_writedata = {24{1'b0}, harvard_writedata[7:0]}; + write_byteenable = 4'b0001; + end + 2'b01: begin + partial_writedata = {16{1'b0}, harvard_writedata[7:0], 8{1'b0}}; + write_byteenable = 4'b0010; + end + 2'b10: begin + partial_writedata = {8{1'b0}, harvard_writedata[7:0], 16{1'b0}}; + write_byteenable = 4'b0100; + end + 2'b11: begin + partial_writedata = {harvard_writedata[7:0], 24{1'b0}}; + write_byteenable = 4'b1000; + end + endcase + end + 6'b101001: begin // Store Halfword + partial_write = 1'b1; + case (harvard_data_address[1:0]) + 2'b00: begin + partial_writedata = {16{1'b0}, harvard_writedata[15:0]}; + write_byteenable = 4'b0011; + end + 2'b01: begin // halfword address must be matrually aligned, last bit must be 0 + partial_writedata = 32'hxxxxxxxx; + write_byteenable = 4'bxxxx; + end + 2'b10: begin + partial_writedata = {harvard_writedata[15:0], 16{1'b0}}; + write_byteenable = 4'b1100; + end + 2'b11: begin // halfword address must be matrually aligned, last bit must be 0 + partial_writedata = 32'hxxxxxxxx; + write_byteenable = 4'bxxxx; + end + endcase + end + default: begin // Store Word OR All other instructions (These flags are ignored outside the write state) + partial_write = 1'b0; + partial_writedata = 32'h00000000; + write_byteenable = 4'b1111; + end + endcase +end + always_comb begin if (reset) begin clk_internal = 1'b0; @@ -134,7 +189,7 @@ always_comb begin write = 1'b1; byteenable = write_byteenable; harvard_readdata = 32'h00000000; - writedata = harvard_writedata; + writedata = partial_write ? partial_writedata : harvard_writedata; n_state = 2'b00; end endcase // state From 11234776906460d5145596dd1c75d8abf931f8ae Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Sun, 13 Dec 2020 00:15:15 +0000 Subject: [PATCH 05/28] Mask address during partial writes --- rtl/mips_cpu_bus.v | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index 08f9de9..2794ca6 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -29,6 +29,7 @@ logic[3:0] write_byteenable; // byteenable calculator for partial write logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly logic partial_write; // flag to control datapath when doing a partial write logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte) +logic[31:0] write_data_address; // modified data address for partial writes initial begin clk_internal = 1'b0; @@ -93,18 +94,22 @@ always_comb begin 2'b00: begin partial_writedata = {24{1'b0}, harvard_writedata[7:0]}; write_byteenable = 4'b0001; + write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b01: begin partial_writedata = {16{1'b0}, harvard_writedata[7:0], 8{1'b0}}; write_byteenable = 4'b0010; + write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b10: begin partial_writedata = {8{1'b0}, harvard_writedata[7:0], 16{1'b0}}; write_byteenable = 4'b0100; + write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b11: begin partial_writedata = {harvard_writedata[7:0], 24{1'b0}}; write_byteenable = 4'b1000; + write_data_address = {harvard_data_address[31:2], 2'b00}; end endcase end @@ -114,18 +119,22 @@ always_comb begin 2'b00: begin partial_writedata = {16{1'b0}, harvard_writedata[15:0]}; write_byteenable = 4'b0011; + write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b01: begin // halfword address must be matrually aligned, last bit must be 0 partial_writedata = 32'hxxxxxxxx; write_byteenable = 4'bxxxx; + write_data_address = 32'hxxxxxxxx; end 2'b10: begin partial_writedata = {harvard_writedata[15:0], 16{1'b0}}; write_byteenable = 4'b1100; + write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b11: begin // halfword address must be matrually aligned, last bit must be 0 partial_writedata = 32'hxxxxxxxx; write_byteenable = 4'bxxxx; + write_data_address = 32'hxxxxxxxx; end endcase end @@ -133,6 +142,7 @@ always_comb begin partial_write = 1'b0; partial_writedata = 32'h00000000; write_byteenable = 4'b1111; + write_data_address = harvard_data_address; end endcase end @@ -184,7 +194,7 @@ always_comb begin n_state = 2'b00; end 2'b11: begin // connecting wires when in write state - address = harvard_data_address; + address = write_data_address; read = 1'b0; write = 1'b1; byteenable = write_byteenable; From 67682ecfde9dd289187209f6c4432e0b8c54d998 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 14:07:43 +0000 Subject: [PATCH 06/28] Create basic bus memory block I/O, parameters and initial setup block included --- rtl/mips_cpu_bus_memory.v | 48 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 rtl/mips_cpu_bus_memory.v diff --git a/rtl/mips_cpu_bus_memory.v b/rtl/mips_cpu_bus_memory.v new file mode 100644 index 0000000..0e103b3 --- /dev/null +++ b/rtl/mips_cpu_bus_memory.v @@ -0,0 +1,48 @@ +module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave) + input logic clk, + input logic[31:0] address, + input logic write, + input logic read, + output logic waitrequest, + input logic[31:0] writedata, + input logic[3:0] byteenable, + output logic[31:0] readdata +); + +parameter INSTR_INIT_FILE = ""; +parameter DATA_INIT_FILE = ""; + +reg [31:0] data_memory [0:63]; // location 0x00001000 onwards +reg [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards + +initial begin + for (integer i=0; i<$size(data_memory); i++) begin //Initialise data to zero by default + data_memory[i] = 0; + end + + for (integer i=0; i<$size(instr_memory); i++) begin //Initialise instr to zero by default + instr_memory[i] = 0; + end + + if (INSTR_INIT_FILE != "") begin //Load instr contents from file if specified + $display("RAM: Loading RAM contents from %s", INSTR_INIT_FILE); + $readmemh(INSTR_INIT_FILE, instr_memory); + end + + for (integer i = 0; i<$size(instr_memory); i++) begin //Read out instr contents to log + $display("byte +%h: %h", 32'hBFC00000+i*4, instr_memory[i]); + end + + if (DATA_INIT_FILE != "") begin //Load data contents from file if specified + $display("MEM: Loading MEM contents from %s", DATA_INIT_FILE); + $readmemh(DATA_INIT_FILE, data_memory); + end else begin + $display("MEM FILE NOT GIVEN"); + end + + for (integer i = 0; i<$size(data_memory); i++) begin //Read out data contents to log + $display("byte +%h: %h", 32'h00001000+i*4, data_memory[i]); + end +end + +endmodule \ No newline at end of file From 4be31493000a14f69a1763a4e84f8d6ced31342e Mon Sep 17 00:00:00 2001 From: jl7719 Date: Wed, 16 Dec 2020 15:58:03 +0000 Subject: [PATCH 07/28] Update test_mips_cpu_bus.sh Needs checking for source file for bus version --- test/test_mips_cpu_bus.sh | 60 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/test/test_mips_cpu_bus.sh b/test/test_mips_cpu_bus.sh index bee7f43..be22673 100755 --- a/test/test_mips_cpu_bus.sh +++ b/test/test_mips_cpu_bus.sh @@ -1,4 +1,60 @@ #!/bin/bash -# should not create any files in the rtl dir -# but auxiliary files / dirs can be utilised \ No newline at end of file +SRC_DIR=${1?Error: no source directory given in argument}; +SRC=$(ls ${SRC_DIR} | grep -E "harvard|memory|alu|regfile|pc|control"); # *** UPDATE THE SRC FOR BUS *** +SRC_TEMP=""; +for src in ${SRC} +do + SRC_TEMP+=${SRC_DIR}/${src}" "; +done +SRC=${SRC_TEMP} + + +INSTR=${2:-"No instruction specified: running all testcases"}; + +if [[ ${INSTR} == "No instruction specified: running all testcases" ]]; +then + for DIR in inputs/*/ + do + DIR=$(basename ${DIR}); + LOOP=$(find inputs/${DIR}/* ! -name '*ref*' ! -name '*log*' ! -name '*data*' ! -name '*out*'); + for TESTCASE in ${LOOP} + do + TESTCASE=$([[ ${TESTCASE} =~ /([^./]+)\. ]] && echo "${BASH_REMATCH[1]}"); + iverilog -Wall -g2012 \ + -s mips_cpu_harvard_tb \ + -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \ + -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ + -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + ${SRC} 2> /dev/null + ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) + echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference + if diff -w ./inputs/${DIR}/${TESTCASE}.out.txt ./inputs/${DIR}/${TESTCASE}.ref.txt &> /dev/null # compare + then + echo ${TESTCASE} ${DIR} "Pass"; + else + printf '%s %s %s%d %s%d%s\n' "${TESTCASE}" "${DIR}" "Fail Output=" "$(tail -1 ./inputs/${DIR}/${TESTCASE}.out.txt)" "Ref=" "$(tail -1 ./inputs/${DIR}/${TESTCASE}.ref.txt)" 2> /dev/null; + fi + done + done +else + LOOP=$(find inputs/${INSTR}/* ! -name '*ref*' ! -name '*log*' ! -name '*data*' ! -name '*out*'); + for TESTCASE in ${LOOP} + do + TESTCASE=$([[ ${TESTCASE} =~ /([^./]+)\. ]] && echo "${BASH_REMATCH[1]}"); + iverilog -Wall -g2012 \ + -s mips_cpu_harvard_tb \ + -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ + -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ + -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + ${SRC} 2> /dev/null + ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) + echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference + if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt &> /dev/null # compare + then + echo ${TESTCASE} ${INSTR} "Pass"; + else + printf '%s %s %s%d %s%d%s\n' "${TESTCASE}" "${INSTR}" "Fail Output=" "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.out.txt)" "Ref=" "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.ref.txt)" 2> /dev/null; + fi + done +fi \ No newline at end of file From f5fea77ea7fc77ee4c999bd51249a783596d14fa Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 08:42:26 -0800 Subject: [PATCH 08/28] General structure of bus memory Read and Write logic to be added --- rtl/mips_cpu_bus_memory.v | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/rtl/mips_cpu_bus_memory.v b/rtl/mips_cpu_bus_memory.v index 0e103b3..6c33f17 100644 --- a/rtl/mips_cpu_bus_memory.v +++ b/rtl/mips_cpu_bus_memory.v @@ -12,8 +12,8 @@ module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave) parameter INSTR_INIT_FILE = ""; parameter DATA_INIT_FILE = ""; -reg [31:0] data_memory [0:63]; // location 0x00001000 onwards -reg [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards +logic [31:0] data_memory [0:63]; // location 0x00001000 onwards +logic [31:0] instr_memory [0:63]; // location 0xBFC00000 onwards initial begin for (integer i=0; i<$size(data_memory); i++) begin //Initialise data to zero by default @@ -45,4 +45,25 @@ initial begin end end +always_ff @(posedge read or posedge write) begin + waitrequest <= 1; +end + +always_ff @(posedge clk) begin + if (waitrequest) begin + if (read) begin + // read code + end else if (write) begin + // write code + end else begin + waitrequest = 1'bx; + readdata = 32'hxxxxxxxx; + end + end else begin + waitrequest = 1'b0; + readdata = 32'h00000000; + end +end + + endmodule \ No newline at end of file From 20880f6ab2b130d88d1f06ddd97accb345d14a1c Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 19:20:48 +0000 Subject: [PATCH 09/28] Complete avalon bus memory Read and write logic (including partial writes using byte enables) complete. Address is always word aligned, as handled within bus wrapper. --- rtl/mips_cpu_bus_memory.v | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/rtl/mips_cpu_bus_memory.v b/rtl/mips_cpu_bus_memory.v index 6c33f17..e2a0b2e 100644 --- a/rtl/mips_cpu_bus_memory.v +++ b/rtl/mips_cpu_bus_memory.v @@ -52,16 +52,36 @@ end always_ff @(posedge clk) begin if (waitrequest) begin if (read) begin - // read code + if (address >= 32'hBFC00000) begin // instruction read + readdata <= instr_memory[{address-32'hBFC00000}>>2]; + end else if (address >= 32'h00001000) begin // data read + readdata <= data_memory[{address-32'h00001000}>>2]; + end + waitrequest <= 1'b0; // end with setting waitrequest low end else if (write) begin - // write code + if (address >= 32'hBFC00000) begin // writing to instr mem area is invalid + $display("Error, write attempted in instr area at address: %h", address); + end else if (address >= 32'h00001000) begin // write to data mem + if (byteenable[3]) begin // if first byte enabled, write + data_memory[{address-32'h00001000}>>2][31:24] <= writedata[31:24]; + end + if (byteenable[2]) begin // if second byte enabled, write + data_memory[{address-32'h00001000}>>2][23:16] <= writedata[23:16]; + end + if (byteenable[1]) begin // if third byte enabled, write + data_memory[{address-32'h00001000}>>2][15:8] <= writedata[15:8]; + end + if (byteenable[0]) begin // if fourth byte enabled, write + data_memory[{address-32'h00001000}>>2][7:0] <= writedata[7:0]; + end + waitrequest <= 1'b0; // end with setting waitrequest low end else begin - waitrequest = 1'bx; - readdata = 32'hxxxxxxxx; + waitrequest <= 1'bx; + readdata <= 32'hxxxxxxxx; end end else begin - waitrequest = 1'b0; - readdata = 32'h00000000; + waitrequest <= 1'b0; + readdata <= 32'h00000000; end end From 2f9b08a363af9b98ba507fc1ebc0ba3bacc130ee Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 20:05:00 +0000 Subject: [PATCH 10/28] Updated bus tb to match harvard tb --- testbench/mips_cpu_bus_tb.v | 110 +++++++++++++++++++++--------------- 1 file changed, 64 insertions(+), 46 deletions(-) diff --git a/testbench/mips_cpu_bus_tb.v b/testbench/mips_cpu_bus_tb.v index 6e77504..fd29a2d 100644 --- a/testbench/mips_cpu_bus_tb.v +++ b/testbench/mips_cpu_bus_tb.v @@ -1,61 +1,79 @@ module mips_cpu_bus_tb; - timeunit 1ns / 10ps; - parameter RAM_INIT_FILE = "test/01-binary/countdown.hex.txt"; - parameter TIMEOUT_CYCLES = 10000; +parameter INSTR_INIT_FILE = "inputs/addiu.txt"; +parameter DATA_INIT_FILE = "inputs/addiu.data.txt"; +parameter TIMEOUT_CYCLES = 1000; // Timeout cycles are higher to account for memory stall delays - logic clk; - logic rst; +logic clk, reset, active, write, read, waitrequest; +logic[31:0] address, register_v0, writedata, readdata; +logic[3:0] byteenable; - logic running; +mips_cpu_bus_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) memInst( //Avalon memory mapped bus controller (slave) + .clk(clk), // clk input to mem + .address(address), // addr input to mem + .write(write), // write flag input + .read(read), // read flag input + .waitrequest(waitrequest), // mem stall output + .writedata(writedata), // data to be written + .byteenable(byteenable), // byteenable bus for writes + .readdata(readdata) // read output port +); - logic[11:0] address; - logic write; - logic read; - logic[15:0] writedata; - logic[15:0] readdata; +mips_cpu_bus cpuInst( + .clk(clk), // clk input to cpu wrapper + .reset(reset), // reset input + .active(active), // active output flag + .register_v0(register_v0), // debug $2 or $v0 output bus + .address(address), // mem addr output + .write(write), // mem write output flag + .read(read), // mem read output flag + .waitrequest(waitrequest), // mem stall input flag + .writedata(writedata), // data to write to mem output + .byteenable(byteenable), // bytes to write output + .readdata(readdata) // data from mem input +); - RAM_16x4096_delay1 #(RAM_INIT_FILE) ramInst(clk, address, write, read, writedata, readdata); - - CPU_MU0_delay1 cpuInst(clk, rst, running, address, write, read, writedata, readdata); +// Setup and clock +initial begin + $dumpfile("mips_cpu_bus.vcd"); + $dumpvars(0,mips_cpu_bus_tb); + clk=0; - // Generate clock - initial begin - clk=0; - - repeat (TIMEOUT_CYCLES) begin - #10; - clk = !clk; - #10; - clk = !clk; - end - - $fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES); + repeat (TIMEOUT_CYCLES) begin + #10; + clk = !clk; + #10; + clk = !clk; end - initial begin - rst <= 0; + $fatal(2, "Simulation did not finish within %d cycles.", TIMEOUT_CYCLES); +end +initial begin + reset <= 1; + @(posedge clk); + reset <= 0; + + @(posedge clk); + assert(active==1) + else $display("TB : CPU did not set active=1 after reset."); + + while (active) begin + //$display("Clk: %d", clk); @(posedge clk); - rst <= 1; - - @(posedge clk); - rst <= 0; - - @(posedge clk); - assert(running==1) - else $display("TB : CPU did not set running=1 after reset."); - - while (running) begin - @(posedge clk); - end - - $display("TB : finished; running=0"); - - $finish; - + //$display("Register v0: %d", register_v0); + //$display("Reg File Write data: %d", cpuInst.in_writedata); + $display("Reg File Out Read data: %h", cpuInst.mips_cpu_harvard.out_readdata1); + $display("Reg File opcode: %b", cpuInst.mips_cpu_harvard.regfile.opcode); + //$display("ALU output: %h", cpuInst.out_ALURes); + //$display("ALU input B: %h", cpuInst.alu.B); end - + @(posedge clk); + $display("TB: CPU Halt; active=0"); + $display("Output:"); + $display("%d",register_v0); + $finish; +end endmodule \ No newline at end of file From 4534ca6760e5405f6e576571ccb1ad59bb2f44c2 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 20:09:08 +0000 Subject: [PATCH 11/28] Add custom test script for bus tb Bus specific testcases have been uncommented (sb, sh) --- test/test_mips_cpu_custom_bus.sh | 67 ++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 test/test_mips_cpu_custom_bus.sh diff --git a/test/test_mips_cpu_custom_bus.sh b/test/test_mips_cpu_custom_bus.sh new file mode 100644 index 0000000..2fca13f --- /dev/null +++ b/test/test_mips_cpu_custom_bus.sh @@ -0,0 +1,67 @@ +#!/bin/bash + +# arithmetic +./test/test_mips_cpu_bus.sh rtl addu #Pass +./test/test_mips_cpu_bus.sh rtl addiu #Pass +./test/test_mips_cpu_bus.sh rtl subu #Pass +./test/test_mips_cpu_bus.sh rtl and #Pass +./test/test_mips_cpu_bus.sh rtl andi #Pass +./test/test_mips_cpu_bus.sh rtl or #Pass +./test/test_mips_cpu_bus.sh rtl ori #Pass +./test/test_mips_cpu_bus.sh rtl xor #Pass +./test/test_mips_cpu_bus.sh rtl xori #Pass +./test/test_mips_cpu_bus.sh rtl div #Pass +./test/test_mips_cpu_bus.sh rtl divu #pass +./test/test_mips_cpu_bus.sh rtl mthi #Pass +./test/test_mips_cpu_bus.sh rtl mtlo #Pass +./test/test_mips_cpu_bus.sh rtl mult #Pass +./test/test_mips_cpu_bus.sh rtl multu #Pass + + +# branches +./test/test_mips_cpu_bus.sh rtl beq #Pass +./test/test_mips_cpu_bus.sh rtl bgez #Pass +./test/test_mips_cpu_bus.sh rtl bgezal #Pass +./test/test_mips_cpu_bus.sh rtl bgtz #Pass +./test/test_mips_cpu_bus.sh rtl blez #Pass +./test/test_mips_cpu_bus.sh rtl bltz #Pass +./test/test_mips_cpu_bus.sh rtl bltzal #Pass +./test/test_mips_cpu_bus.sh rtl bne #Pass + +# jumps +./test/test_mips_cpu_bus.sh rtl j #Pass +./test/test_mips_cpu_bus.sh rtl jalr #Pass +./test/test_mips_cpu_bus.sh rtl jal #Pass +./test/test_mips_cpu_bus.sh rtl jr #Pass + +# shift +./test/test_mips_cpu_bus.sh rtl sll #Pass +./test/test_mips_cpu_bus.sh rtl srl #Pass +./test/test_mips_cpu_bus.sh rtl sra #Pass +./test/test_mips_cpu_bus.sh rtl srav #Pass +./test/test_mips_cpu_bus.sh rtl sllv #Pass +./test/test_mips_cpu_bus.sh rtl srlv #Pass + + + +# load & store +./test/test_mips_cpu_bus.sh rtl lw #Pass +./test/test_mips_cpu_bus.sh rtl lb #Pass +./test/test_mips_cpu_bus.sh rtl lbu #Pass +./test/test_mips_cpu_bus.sh rtl lh #Pass +./test/test_mips_cpu_bus.sh rtl lhu #Pass +./test/test_mips_cpu_bus.sh rtl lui #Pass +./test/test_mips_cpu_bus.sh rtl lwl #Pass +./test/test_mips_cpu_bus.sh rtl lwr #Pass +./test/test_mips_cpu_bus.sh rtl sw #Pass +./test/test_mips_cpu_bus.sh rtl sb #Once switched to bus +./test/test_mips_cpu_bus.sh rtl sh #Once switched to bus + + +# set on less than **Branch delay slots dont work on these... +./test/test_mips_cpu_bus.sh rtl slti #Pass +./test/test_mips_cpu_bus.sh rtl sltiu #Pass +./test/test_mips_cpu_bus.sh rtl slt #Pass +./test/test_mips_cpu_bus.sh rtl sltu #Pass + + From 744aee097ffb586cd4f3c44706fdd777a26ad9df Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 20:15:08 +0000 Subject: [PATCH 12/28] Modify bus tb to compile bus version instead --- test/test_mips_cpu_bus.sh | 26 +++++++++++++------------- testbench/mips_cpu_bus_tb.v | 4 ++-- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/test/test_mips_cpu_bus.sh b/test/test_mips_cpu_bus.sh index be22673..1b90fe7 100755 --- a/test/test_mips_cpu_bus.sh +++ b/test/test_mips_cpu_bus.sh @@ -1,13 +1,13 @@ #!/bin/bash SRC_DIR=${1?Error: no source directory given in argument}; -SRC=$(ls ${SRC_DIR} | grep -E "harvard|memory|alu|regfile|pc|control"); # *** UPDATE THE SRC FOR BUS *** +SRC=$(find ./${SRC_DIR}/*); SRC_TEMP=""; for src in ${SRC} do - SRC_TEMP+=${SRC_DIR}/${src}" "; + SRC_TEMP+=${src}" "; done -SRC=${SRC_TEMP} +SRC=${SRC_TEMP}; INSTR=${2:-"No instruction specified: running all testcases"}; @@ -22,12 +22,12 @@ then do TESTCASE=$([[ ${TESTCASE} =~ /([^./]+)\. ]] && echo "${BASH_REMATCH[1]}"); iverilog -Wall -g2012 \ - -s mips_cpu_harvard_tb \ - -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \ - -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + -s mips_cpu_bus_tb \ + -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \ + -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ + -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v \ ${SRC} 2> /dev/null - ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) + ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference if diff -w ./inputs/${DIR}/${TESTCASE}.out.txt ./inputs/${DIR}/${TESTCASE}.ref.txt &> /dev/null # compare then @@ -43,12 +43,12 @@ else do TESTCASE=$([[ ${TESTCASE} =~ /([^./]+)\. ]] && echo "${BASH_REMATCH[1]}"); iverilog -Wall -g2012 \ - -s mips_cpu_harvard_tb \ - -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ - -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + -s mips_cpu_bus_tb \ + -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ + -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ + -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v \ ${SRC} 2> /dev/null - ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) + ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt &> /dev/null # compare then diff --git a/testbench/mips_cpu_bus_tb.v b/testbench/mips_cpu_bus_tb.v index fd29a2d..ee7afa8 100644 --- a/testbench/mips_cpu_bus_tb.v +++ b/testbench/mips_cpu_bus_tb.v @@ -1,7 +1,7 @@ module mips_cpu_bus_tb; -parameter INSTR_INIT_FILE = "inputs/addiu.txt"; -parameter DATA_INIT_FILE = "inputs/addiu.data.txt"; +parameter INSTR_INIT_FILE = ""; +parameter DATA_INIT_FILE = ""; parameter TIMEOUT_CYCLES = 1000; // Timeout cycles are higher to account for memory stall delays logic clk, reset, active, write, read, waitrequest; From da0c9aba01088822e23505b99f122bc0e0aded9a Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 13:38:09 -0800 Subject: [PATCH 13/28] Fix {} for bit duplication, remove module name from endmodule --- rtl/mips_cpu_bus.v | 14 +++++++------- test/test_mips_cpu_bus.sh | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index 2794ca6..f3997fd 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -92,22 +92,22 @@ always_comb begin partial_write = 1'b1; case (harvard_data_address[1:0]) 2'b00: begin - partial_writedata = {24{1'b0}, harvard_writedata[7:0]}; + partial_writedata = {{24{1'b0}}, harvard_writedata[7:0]}; write_byteenable = 4'b0001; write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b01: begin - partial_writedata = {16{1'b0}, harvard_writedata[7:0], 8{1'b0}}; + partial_writedata = {{16{1'b0}}, harvard_writedata[7:0], {8{1'b0}}}; write_byteenable = 4'b0010; write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b10: begin - partial_writedata = {8{1'b0}, harvard_writedata[7:0], 16{1'b0}}; + partial_writedata = {{8{1'b0}}, harvard_writedata[7:0], {16{1'b0}}}; write_byteenable = 4'b0100; write_data_address = {harvard_data_address[31:2], 2'b00}; end 2'b11: begin - partial_writedata = {harvard_writedata[7:0], 24{1'b0}}; + partial_writedata = {harvard_writedata[7:0], {24{1'b0}}}; write_byteenable = 4'b1000; write_data_address = {harvard_data_address[31:2], 2'b00}; end @@ -117,7 +117,7 @@ always_comb begin partial_write = 1'b1; case (harvard_data_address[1:0]) 2'b00: begin - partial_writedata = {16{1'b0}, harvard_writedata[15:0]}; + partial_writedata = {{16{1'b0}}, harvard_writedata[15:0]}; write_byteenable = 4'b0011; write_data_address = {harvard_data_address[31:2], 2'b00}; end @@ -127,7 +127,7 @@ always_comb begin write_data_address = 32'hxxxxxxxx; end 2'b10: begin - partial_writedata = {harvard_writedata[15:0], 16{1'b0}}; + partial_writedata = {harvard_writedata[15:0], {16{1'b0}}}; write_byteenable = 4'b1100; write_data_address = {harvard_data_address[31:2], 2'b00}; end @@ -221,4 +221,4 @@ mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper .data_readdata(harvard_readdata) // data in from read instruction, input ); -endmodule : mips_cpu_bus +endmodule diff --git a/test/test_mips_cpu_bus.sh b/test/test_mips_cpu_bus.sh index 1b90fe7..352244b 100755 --- a/test/test_mips_cpu_bus.sh +++ b/test/test_mips_cpu_bus.sh @@ -47,10 +47,10 @@ else -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v \ - ${SRC} 2> /dev/null + ${SRC} #2> /dev/null ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference - if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt &> /dev/null # compare + if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt #&> /dev/null # compare then echo ${TESTCASE} ${INSTR} "Pass"; else From d17060b0a1571811bdf41af63ac9f608b8bd3c2f Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 13:54:01 -0800 Subject: [PATCH 14/28] Add missing end to if statement --- rtl/mips_cpu_bus_memory.v | 1 + 1 file changed, 1 insertion(+) diff --git a/rtl/mips_cpu_bus_memory.v b/rtl/mips_cpu_bus_memory.v index e2a0b2e..a2f47f2 100644 --- a/rtl/mips_cpu_bus_memory.v +++ b/rtl/mips_cpu_bus_memory.v @@ -75,6 +75,7 @@ always_ff @(posedge clk) begin data_memory[{address-32'h00001000}>>2][7:0] <= writedata[7:0]; end waitrequest <= 1'b0; // end with setting waitrequest low + end end else begin waitrequest <= 1'bx; readdata <= 32'hxxxxxxxx; From 5e62dd82d8d9e3530673b62df70309942773caa1 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 14:08:28 -0800 Subject: [PATCH 15/28] Add bus vcd to gitignore, fix missing case in bus --- .gitignore | 1 + rtl/mips_cpu_bus.v | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index ea6eaf9..15145de 100644 --- a/.gitignore +++ b/.gitignore @@ -3,5 +3,6 @@ exec/* *.log.txt *.out.txt mips_cpu_harvard.vcd +mips_cpu_bus.vcd .DS_Store inputs/.DS_Store diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index f3997fd..ca00dc9 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -69,7 +69,8 @@ end always_ff @(negedge clk) begin // CLK Falling Edge if (!waitrequest && clk_state) begin case (state) - 2'b00: // nothing happens on fetch negedge + 2'b00: begin // nothing happens on fetch negedge + end 2'b01: begin // execute negedge if (!harvard_read && !harvard_write) begin // instruction complete, trigger writeback clk_internal <= 1'b0; From 33bb4c7538212cc902b0698e0790a0f498f07800 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Wed, 16 Dec 2020 14:13:54 -0800 Subject: [PATCH 16/28] Constant selects not working in always_ff in current iverilog --- rtl/mips_cpu_bus.v | 2 +- test/test_mips_cpu_bus.sh | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index ca00dc9..ca117dd 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -87,7 +87,7 @@ always_ff @(negedge clk) begin // CLK Falling Edge clk_state <= 1'b0; end -always_comb begin +always @(*) begin case (instr_reg[31:26]) 6'b101000: begin // Store Byte partial_write = 1'b1; diff --git a/test/test_mips_cpu_bus.sh b/test/test_mips_cpu_bus.sh index 352244b..1b90fe7 100755 --- a/test/test_mips_cpu_bus.sh +++ b/test/test_mips_cpu_bus.sh @@ -47,10 +47,10 @@ else -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v \ - ${SRC} #2> /dev/null + ${SRC} 2> /dev/null ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference - if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt #&> /dev/null # compare + if diff -w ./inputs/${INSTR}/${TESTCASE}.out.txt ./inputs/${INSTR}/${TESTCASE}.ref.txt &> /dev/null # compare then echo ${TESTCASE} ${INSTR} "Pass"; else From af29f22651213a870a8cafea6fcd4bf58f3eb831 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 13:54:26 +0000 Subject: [PATCH 17/28] Merge branch 'main' into bus_wrapper Changes to be duplicated for bus version --- inputs/addiu/addiu-1.txt | 2 +- inputs/addiu/addiu-2.ref.txt | 1 - inputs/addiu/addiu-2.txt | 2 - inputs/addu/addu-1.txt | 2 +- inputs/and/and-1.txt | 2 +- inputs/andi/andi-1.txt | 2 +- inputs/beq/beq-2.ref.txt | 1 - inputs/beq/beq-2.txt | 8 - inputs/bgez/bgez-2.ref.txt | 1 - inputs/bgez/bgez-2.txt | 7 - inputs/lb/lb-1.txt | 2 +- inputs/lbu/lbu-1.txt | 2 +- inputs/lh/lh-1.txt | 2 +- inputs/lhu/lhu-1.txt | 2 +- inputs/lw/lw-1.txt | 2 +- inputs/lwl/lwl-1.txt | 2 +- inputs/lwr/lwr-1.txt | 2 +- inputs/or/or-1.txt | 2 +- inputs/ori/ori-1.ref.txt | 2 +- inputs/ori/ori-1.txt | 6 +- inputs/ori/ori-2.ref.txt | 1 - inputs/ori/ori-2.txt | 4 - inputs/sll/sll-1.txt | 2 +- inputs/sllv/sllv-1.txt | 2 +- inputs/slt/slt-1.txt | 4 +- inputs/slt/slt-2.ref.txt | 1 - inputs/slt/slt-2.txt | 4 - inputs/sra/sra-1.txt | 3 +- inputs/srav/srav-1.txt | 3 +- inputs/srl/srl-1.txt | 2 +- inputs/srlv/srlv-1.txt | 2 +- inputs/subu/subu-1.txt | 2 +- inputs/xori/xori-1.txt | 4 +- reference.txt | 869 ------------------ .../Instructions.xlsx | Bin mips-isa.pdf => reference/mips-isa.pdf | Bin reference/reference.txt | 604 ++++++++---- structure.png => reference/structure.png | Bin test/test_mips_cpu_harvard.sh | 4 +- {rtl => testbench}/mips_cpu_memory.v | 0 40 files changed, 480 insertions(+), 1083 deletions(-) delete mode 100644 inputs/addiu/addiu-2.ref.txt delete mode 100644 inputs/addiu/addiu-2.txt delete mode 100644 inputs/beq/beq-2.ref.txt delete mode 100644 inputs/beq/beq-2.txt delete mode 100644 inputs/bgez/bgez-2.ref.txt delete mode 100644 inputs/bgez/bgez-2.txt delete mode 100644 inputs/ori/ori-2.ref.txt delete mode 100644 inputs/ori/ori-2.txt delete mode 100644 inputs/slt/slt-2.ref.txt delete mode 100644 inputs/slt/slt-2.txt delete mode 100644 reference.txt rename Instructions.xlsx => reference/Instructions.xlsx (100%) rename mips-isa.pdf => reference/mips-isa.pdf (100%) rename structure.png => reference/structure.png (100%) rename {rtl => testbench}/mips_cpu_memory.v (100%) diff --git a/inputs/addiu/addiu-1.txt b/inputs/addiu/addiu-1.txt index 62290ae..7401d7b 100644 --- a/inputs/addiu/addiu-1.txt +++ b/inputs/addiu/addiu-1.txt @@ -1,3 +1,3 @@ 3404000a +00000008 24820014 -00000008 \ No newline at end of file diff --git a/inputs/addiu/addiu-2.ref.txt b/inputs/addiu/addiu-2.ref.txt deleted file mode 100644 index 9a03714..0000000 --- a/inputs/addiu/addiu-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -10 \ No newline at end of file diff --git a/inputs/addiu/addiu-2.txt b/inputs/addiu/addiu-2.txt deleted file mode 100644 index 664859c..0000000 --- a/inputs/addiu/addiu-2.txt +++ /dev/null @@ -1,2 +0,0 @@ -2442000A -00000008 \ No newline at end of file diff --git a/inputs/addu/addu-1.txt b/inputs/addu/addu-1.txt index 1c079df..5d98337 100644 --- a/inputs/addu/addu-1.txt +++ b/inputs/addu/addu-1.txt @@ -1,4 +1,4 @@ 34040003 34050005 +00000008 00851021 -00000008 \ No newline at end of file diff --git a/inputs/and/and-1.txt b/inputs/and/and-1.txt index 7a287c6..f50bee1 100644 --- a/inputs/and/and-1.txt +++ b/inputs/and/and-1.txt @@ -2,5 +2,5 @@ 34A5cccc 3c04aaaa 3484aaaa +00000008 00851024 -00000008 \ No newline at end of file diff --git a/inputs/andi/andi-1.txt b/inputs/andi/andi-1.txt index ccc9aa9..a927a1b 100644 --- a/inputs/andi/andi-1.txt +++ b/inputs/andi/andi-1.txt @@ -1,4 +1,4 @@ 3c04aaaa 3404aaaa +00000008 3082cccc -00000008 \ No newline at end of file diff --git a/inputs/beq/beq-2.ref.txt b/inputs/beq/beq-2.ref.txt deleted file mode 100644 index 60d3b2f..0000000 --- a/inputs/beq/beq-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -15 diff --git a/inputs/beq/beq-2.txt b/inputs/beq/beq-2.txt deleted file mode 100644 index 07e24de..0000000 --- a/inputs/beq/beq-2.txt +++ /dev/null @@ -1,8 +0,0 @@ -34040005 -34050005 -10850003 -34020005 -00000008 -00000000 -2442000A -00000008 \ No newline at end of file diff --git a/inputs/bgez/bgez-2.ref.txt b/inputs/bgez/bgez-2.ref.txt deleted file mode 100644 index 7813681..0000000 --- a/inputs/bgez/bgez-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -5 \ No newline at end of file diff --git a/inputs/bgez/bgez-2.txt b/inputs/bgez/bgez-2.txt deleted file mode 100644 index 13d6d41..0000000 --- a/inputs/bgez/bgez-2.txt +++ /dev/null @@ -1,7 +0,0 @@ -34040003 -04810003 -00000000 -24420001 -00000000 -24420005 -00000008 \ No newline at end of file diff --git a/inputs/lb/lb-1.txt b/inputs/lb/lb-1.txt index 43aa99a..940d1c7 100644 --- a/inputs/lb/lb-1.txt +++ b/inputs/lb/lb-1.txt @@ -1,3 +1,3 @@ 34041001 +00000008 80820005 -00000008 \ No newline at end of file diff --git a/inputs/lbu/lbu-1.txt b/inputs/lbu/lbu-1.txt index 14f9e84..0c0c283 100644 --- a/inputs/lbu/lbu-1.txt +++ b/inputs/lbu/lbu-1.txt @@ -1,3 +1,3 @@ 34041002 +00000008 90820004 -00000008 \ No newline at end of file diff --git a/inputs/lh/lh-1.txt b/inputs/lh/lh-1.txt index aa12925..f3c6ebd 100644 --- a/inputs/lh/lh-1.txt +++ b/inputs/lh/lh-1.txt @@ -1,3 +1,3 @@ 34041000 +00000008 84820004 -00000008 \ No newline at end of file diff --git a/inputs/lhu/lhu-1.txt b/inputs/lhu/lhu-1.txt index d8bc6f1..f185691 100644 --- a/inputs/lhu/lhu-1.txt +++ b/inputs/lhu/lhu-1.txt @@ -1,3 +1,3 @@ 34041000 +00000008 94820004 -00000008 \ No newline at end of file diff --git a/inputs/lw/lw-1.txt b/inputs/lw/lw-1.txt index 7c6a2ee..702ed31 100644 --- a/inputs/lw/lw-1.txt +++ b/inputs/lw/lw-1.txt @@ -1,3 +1,3 @@ 34041002 +00000008 8C820002 -00000008 \ No newline at end of file diff --git a/inputs/lwl/lwl-1.txt b/inputs/lwl/lwl-1.txt index c682e96..5ba291d 100644 --- a/inputs/lwl/lwl-1.txt +++ b/inputs/lwl/lwl-1.txt @@ -1,4 +1,4 @@ 34041001 34025678 +00000008 88820003 -00000008 \ No newline at end of file diff --git a/inputs/lwr/lwr-1.txt b/inputs/lwr/lwr-1.txt index 633db20..7f2641f 100644 --- a/inputs/lwr/lwr-1.txt +++ b/inputs/lwr/lwr-1.txt @@ -1,4 +1,4 @@ 3C021234 34041002 +00000008 98820003 -00000008 \ No newline at end of file diff --git a/inputs/or/or-1.txt b/inputs/or/or-1.txt index 25df299..7d9b029 100644 --- a/inputs/or/or-1.txt +++ b/inputs/or/or-1.txt @@ -1,4 +1,4 @@ 34040005 34050003 +00000008 00851025 -00000008 \ No newline at end of file diff --git a/inputs/ori/ori-1.ref.txt b/inputs/ori/ori-1.ref.txt index c793025..35ff949 100644 --- a/inputs/ori/ori-1.ref.txt +++ b/inputs/ori/ori-1.ref.txt @@ -1 +1 @@ -7 \ No newline at end of file +65535 \ No newline at end of file diff --git a/inputs/ori/ori-1.txt b/inputs/ori/ori-1.txt index b41478b..35a84da 100644 --- a/inputs/ori/ori-1.txt +++ b/inputs/ori/ori-1.txt @@ -1,3 +1,5 @@ -34020003 -34420005 +3404FFFF +34051234 00000008 +00851025 + diff --git a/inputs/ori/ori-2.ref.txt b/inputs/ori/ori-2.ref.txt deleted file mode 100644 index 35ff949..0000000 --- a/inputs/ori/ori-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -65535 \ No newline at end of file diff --git a/inputs/ori/ori-2.txt b/inputs/ori/ori-2.txt deleted file mode 100644 index b13206a..0000000 --- a/inputs/ori/ori-2.txt +++ /dev/null @@ -1,4 +0,0 @@ -3404FFFF -34052134 -00851025 -00000008 diff --git a/inputs/sll/sll-1.txt b/inputs/sll/sll-1.txt index e03a5d2..8956883 100644 --- a/inputs/sll/sll-1.txt +++ b/inputs/sll/sll-1.txt @@ -1,3 +1,3 @@ 34040003 +00000008 00041080 -00000008 \ No newline at end of file diff --git a/inputs/sllv/sllv-1.txt b/inputs/sllv/sllv-1.txt index d733281..5eaf2c8 100644 --- a/inputs/sllv/sllv-1.txt +++ b/inputs/sllv/sllv-1.txt @@ -1,4 +1,4 @@ 34040002 34050003 +00000008 00851004 -00000008 \ No newline at end of file diff --git a/inputs/slt/slt-1.txt b/inputs/slt/slt-1.txt index 2d14014..d58bdf7 100644 --- a/inputs/slt/slt-1.txt +++ b/inputs/slt/slt-1.txt @@ -1,4 +1,4 @@ -3404000F +3404FFFF 3405000B 00000008 -0085102A \ No newline at end of file +0085102A diff --git a/inputs/slt/slt-2.ref.txt b/inputs/slt/slt-2.ref.txt deleted file mode 100644 index c227083..0000000 --- a/inputs/slt/slt-2.ref.txt +++ /dev/null @@ -1 +0,0 @@ -0 \ No newline at end of file diff --git a/inputs/slt/slt-2.txt b/inputs/slt/slt-2.txt deleted file mode 100644 index 013d035..0000000 --- a/inputs/slt/slt-2.txt +++ /dev/null @@ -1,4 +0,0 @@ -3404FFFF -3405000B -0085102A -00000008 \ No newline at end of file diff --git a/inputs/sra/sra-1.txt b/inputs/sra/sra-1.txt index 1cb5924..d7817c1 100644 --- a/inputs/sra/sra-1.txt +++ b/inputs/sra/sra-1.txt @@ -1,3 +1,4 @@ 3C05F000 -00051083 00000008 +00051083 + diff --git a/inputs/srav/srav-1.txt b/inputs/srav/srav-1.txt index 8d6dad2..681d41b 100644 --- a/inputs/srav/srav-1.txt +++ b/inputs/srav/srav-1.txt @@ -1,4 +1,5 @@ 34040002 3C05F000 -00851007 00000008 +00851007 + diff --git a/inputs/srl/srl-1.txt b/inputs/srl/srl-1.txt index 581aa82..4ac3949 100644 --- a/inputs/srl/srl-1.txt +++ b/inputs/srl/srl-1.txt @@ -1,3 +1,3 @@ 34040010 +00000008 00041082 -00000008 \ No newline at end of file diff --git a/inputs/srlv/srlv-1.txt b/inputs/srlv/srlv-1.txt index ae99941..ebd01e3 100644 --- a/inputs/srlv/srlv-1.txt +++ b/inputs/srlv/srlv-1.txt @@ -1,4 +1,4 @@ 34040002 34050010 +00000008 00851006 -00000008 \ No newline at end of file diff --git a/inputs/subu/subu-1.txt b/inputs/subu/subu-1.txt index 7c8a7eb..d4590d9 100644 --- a/inputs/subu/subu-1.txt +++ b/inputs/subu/subu-1.txt @@ -1,4 +1,4 @@ 34040005 34050003 +00000008 00851023 -00000008 \ No newline at end of file diff --git a/inputs/xori/xori-1.txt b/inputs/xori/xori-1.txt index 4fe9205..c85639a 100644 --- a/inputs/xori/xori-1.txt +++ b/inputs/xori/xori-1.txt @@ -1,5 +1,3 @@ 34040005 -3882000F 00000008 -00000000 -00000000 \ No newline at end of file +3882000F diff --git a/reference.txt b/reference.txt deleted file mode 100644 index 493a0f9..0000000 --- a/reference.txt +++ /dev/null @@ -1,869 +0,0 @@ -== Instruction == -Assembly code -Hex code -Reference Output -================ - -==ADDIU Add immediate unsigned (no overflow)== - -ORI $4,$0,0xA -ADDIU $2,$4,20 -JR $0 - -3404000a -24820014 -00000008 - -register_v0 = 30 - -== ADDU Add unsigned (no overflow) == - -ORI $4,$0,3 -ORI $5,$0,5 -ADDU $2,$4,$5 -JR $0 - -34040003 -34050005 -00851021 -00000008 - -register_v0 = 8 - -==AND Bitwise and== - -LUI $5,0xCCCC -ORI $5,$5,0xCCCC -LUI $4,0xAAAA -ORI $4,$4,0xAAAA -AND $2,$4,$5 -JR $0 - -3c05cccc -34A5cccc -3c04aaaa -3484aaaa -00851024 -00000008 - -register_v0 = 0x88888888 - -==ANDI Bitwise and immediate== - -LUI $4,0xAAAA -ORI $4,$0,0xAAAA -ANDI $2,$4,0xCCCC -JR $0 - -3c04aaaa -3404aaaa -3082cccc -00000008 - -register_v0 = 0x00008888 - -==BEQ Branch on equal== - -ORI $4,$0,5 -ORI $5,$0,5 -BEQ $4,$5,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040005 -34050005 -10850003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BGEZ Branch on greater than or equal to zero== - -ORI $4,$0,3 -BGEZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040003 -04810003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -ORI $4,$0,3 -BGEZ $4,3 -NOP -ADDIU $2,$2,1 -NOP -ADDIU $2,$2,5 -JR $0 - -34040003 -04810003 -00000000 -24420001 -00000000 -24420005 -00000008 - -==BGEZAL Branch on non-negative (>=0) and link== - -ORI $4,$0,3 -BGEZAL $4,4 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $31 - -34040003 -04910004 -00000000 -24420001 -00000008 -00000000 -34020001 -03E00008 - -register_v0 = 2 - -==BGTZ Branch on greater than zero== - -ORI $4,$0,3 -BGTZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040003 -1C800003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BLEZ Branch on less than or equal to zero== - -LUI $4,0xFFFF -BLEZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -3C05FFFF -18800003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BLTZ Branch on less than zero== - -LUI $4,0xFFFF -BLTZ $4,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -3C04FFFF -04800003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==BLTZAL Branch on less than zero and link== - -LUI $4,0xFFFF -BLTZAL $4,4 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $31 - -3C05FFFF -04900004 -00000000 -24420001 -00000008 -00000000 -34020001 -03E00008 - -register_v0 = 2 - -==BNE Branch on not equal== - -ORI $4,$0,3 -ORI $5,$0,5 -BNE $4,$5,3 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -34040003 -34040005 -14850003 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==DIV Divide== //May need other testcases for -ve/+ve, -ve/-ve - -ORI $4,$0,3 -ORI $5,$0,9 -DIV $5,$4 -MFHI $4 -MFLO $5 -ADDU $2,$4,$5 -JR $0 - -34040003 -34050009 -00A4001A -00002010 -00002812 -00851021 -00000008 - -register_v0 = 3 - -==DIVU Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve - -LUI $4,0x8000 -ORI $5,$0,2 -DIVU $4,$5 -MFHI $4 -MFLO $5 -ADDU $2,$4,$5 -JR $0 - -3C048000 -34050002 -0085001B -00002010 -00002812 -00851021 -00000008 - -register_v0 = 0x40000000 - -==J Jump== - -J 4 -NOP -JR $0 -NOP -ORI $2,$0,1 -JR $0 - -08000004 -00000000 -00000008 -00000000 -34020001 -00000008 - -register_v0 = 1 - -==JALR Jump and link register== - -LUI $5,0xBFC0 -ORI $5,$0,0x001C -JALR $4,$5 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $4 - -3C05BCF0 -3405001C -00A02009 -00000000 -24420001 -00000008 -00000000 -34020001 -00800008 - -register_v0 = 2 - -==JAL Jump and link== - -JAL 5 -NOP -ADDIU $2,$2,1 -JR $0 -NOP -ORI $2,$0,1 -JR $31 - -0C000005 -00000000 -24420001 -00000008 -00000000 -34020001 -03E00008 - -register_v0 = 2 - -==JR Jump register== - -LUI $5,0xBFC0 -ORI $5,$5,0x0014 -JR $5 -NOP -JR $0 -NOP -ORI $2,$0,0xA -JR $0 - -3C05BFC0 -34A50014 -00A00008 -00000000 -00000008 -3402000A -00000008 - -register_v0 = 10 - -==LB Load byte== - -ORI $4,$0,0x1003 -LB $2,3($4) -JR $0 - --Instruction Hex - -34041000 -80820006 -00000008 - --Memory Hex - -00000000 -008A0000 -00000000 -00000000 - -register_v0 = 0xFFFFFF8A - -==LBU Load byte unsigned== - -ORI $4,$0,0x1003 -LBU $2,3($4) -JR $0 - --Instruction Hex - -34041003 -90820003 -00000008 - --Memory Hex - -00000000 -008A0000 -00000000 -00000000 - -register_v0 = 0x0000008A - -==LH Load half-word== - -ORI $4,$0,0x1003 -LH $2,4($4) -JR $0 - --Instruction Hex - -34041003 -84820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0xFFFF8123 - -==LHU Load half-word unsigned== - -ORI $4,$0,0x1003 -LHU $2,4($4) -JR $0 - --Instruction Hex - -34041003 -94820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0x00008123 - -==LUI Load upper immediate== - -LUI $2,0x1234 -ORI $2,$2,0x5678 -JR $0 - -3C021234 -34425678 -00000008 - -register_v0 = 0x12345678 - -==LW Load word== - -ORI $4,$0,0x1002 -LW $2, 2($4) -JR $0 - --Instruction Hex - -34041002 -8C820002 -00000008 - --Memory Hex - -00000000 -12345678 -00000000 -00000000 - -register_v0 = 0x12345678 - -==LWL Load word left== - -ORI $4,$0,0x1001 -ORI $2,$0,0x5678 -LWL $2,3($4) -JR $0 - --Instruction Hex - -34041001 -34025678 -88820003 -00000008 - --Memory Hex - -00000000 -AAAA1234 -00000000 -00000000 - -register_v0 = 0x12345678 - -==LWR Load word right== - -LUI $2,0x1234 -ORI $4,$0,0x1002 -LWR $2,3($4) -JR $0 - --Instruction Hex - -3C021234 -34041002 -98820003 -00000008 - --Memory Hex - -00000000 -5678AAAA -00000000 -00000000 - -register_v0 = 0x12345678 - -==MTHI Move to HI== - -ori $4, $0, 5 -mthi $4 -mfhi $2 -jr $0 - -34040005 -00800011 -00001010 -00000008 - -register_v0 = 5 - -==MTLO Move to LO== - -ori $4, $0, 5 -mtlo $4 -mflo $2 -jr $0 - -34040005 -00800013 -00001012 -00000008 - -register_v0 = 5 - -==MULT Multiply== - -ori $4, $0, 4 -ori $5, $0, 3 -mult $4, $5 -mflo $2 -jr $0 - -34040004 -34050003 -00850018 -00001012 -00000008 - -register_v0 = 12 - -==MULTU Multiply unsigned== - -ori $4, $0, 4 -ori $5, $0, 3 -multu $4, $5 -mflo $2 -jr $0 - -34040004 -34050003 -00850019 -00001012 -00000008 - -register_v0 = 12 - -==OR Bitwise or== - -ori $4, $0, 5 -ori $5, $0, 3 -or $2, $4, $5 -jr $0 - -34040005 -34050003 -00851025 -00000008 - -register_v0 = 7 - - -==ORI Bitwise or immediate== - -ori $2, $0, 3 -ori $2, $2, 5 -jr $0 - -34020003 -00000008 -34420005 - -register_v0 = 7 - -ori $4, $0, 0xFFFF -ori $5, $0, 0x1234 -or $2, $4, $5 -jr $0 - -register_v0 = 65535 - -==SB Store byte== - -lui $4, 0x1234 -ori $4, $0, 0x5678 -lui $5, 0xBFC0 -ori $5, $0, 0x001C -sb $4, 0($5) -lb $2, 0($5) -jr $0 - -3C041234 -34045678 -3C05BFC0 -3405001C -A0A40000 -80A20000 -00000008 - -register_v0 = 0x00000078 - -==SH Store half-word== - -lui $4, 0x1234 -ori $4, $0, 0x5678 -lui $5, 0xBFC0 -ori $5, $0, 0x001C -sh $4, 0($5) -lh $2, 0($5) -jr $0 - -3C041234 -34045678 -3C05BFC0 -3405001C -A4A40000 -84A40000 -00000008 - -register_v0 = 0x00005678 - -==SLL Shift left logical== - -ori $4,$0,3 -sll $2,$4,2 -jr $0 - -34040003 -00041080 -00000008 - -register_v0 = 12 - -==SLLV Shift left logical variable== - -ori $4,$0,2 -ori $5,$0,3 -sllv $2,$5,$4 -jr $0 - -34040002 -34050003 -00851004 -00000008 - -register_v0 = 12 - -==SLT Set on less than (signed)== - -ORI $4 $zero 0xFFFF -ORI $5 $zero 0x000B -SLT $2 $4 $5 -jr $0 - -3404FFFF -3405000B -0085102A -00000008 - -register_v0 = 0 - -==SLTI Set on less than immediate (signed)== - -ori $4, $0, 10 -slti $2, $4, 9 -jr $0 - -3404000a -28820009 -00000008 - -register_v0 = 0 - -==SLTIU Set on less than immediate unsigned== - -ori $4, $0, 10 -sltiu $2, $4, 9 -jr $0 - -3404000a -2c820009 -00000008 - -register_v0 = 0 - -==SLTU Set on less than unsigned== - -ori $4, $0, 10 -ori $5, $0, 9 -sltu $2, $4, $5 -jr $0 - -3404000a -34050009 -0085102b -00000008 - -register_v0 = 0 - -==SRA Shift right arithmetic== - -lui $5 $0,0xF000 -srav $2,$5,2 -jr $0 - -3C05F000 -00051083 -00000008 - -register_v0 = 0xFC000000 - -==SRAV Shift right arithmetic variable== - -ori $4,$0,2 -lui $5, 0xF000 -srav $2,$5,$4 -jr $0 - -F000000 -> FC000000 - -34040004 -3C05F000 -00851007 -00000008 - -register_v0 = 0xFC000000 - -==SRL Shift right logical== - -ori $4,$0,16 -srl $2,$4,2 -jr $0 - -34040010 -00041082 -00000008 - -register_v0 = 4 - -==SRLV Shift right logical variable== - -ori $4,$0,2 -ori $5,$0,16 -srlv $2,$5,$4 -jr $0 - -34040002 -34050010 -00851006 -00000008 - -register_v0 = 4 - -==SUBU Subtract unsigned== - -ori $4,$0,5 -ori $5,$0,3 -subu $2,$4,$5 -jr $0 - -34040005 -34050003 -00851023 -00000008 - -register_v0 = 2 - -==SW Store word== - -ori $4, $0, 0xFFFF -ori $5, $0, 0x1008 -sw $4, 4($5) -lw $2, 4($5) -jr $0 - -3404FFFF -34051008 -ACA40004 -8CA20004 -00000008 - -register_v0 = 0x0000FFFF - -ori $4, $0, 0xFFFF -ori $5, $0, 0x1008 -sw $4, -4($5) -lw $2, -4($5) -jr $0 - -3404FFFF -34051008 -ACA4FFFC -8CA2FFFC -00000008 - -register_v0 = 0x0000FFFF - -==XOR Bitwise exclusive or== - -ori $4, $0, 5 -ori $5, $0, 2 -xor $2, $4, $5 -jr $0 - -34040005 -34050002 -00851026 -00000008 - -register_v0 = 7 - -==XORI Bitwise exclusive or immediate== - -ori $4,$0,5 -xori $2,$4,0x000F -jr $0 - -34040005 -3882000F -00000008 - -register_v0 = 10 diff --git a/Instructions.xlsx b/reference/Instructions.xlsx similarity index 100% rename from Instructions.xlsx rename to reference/Instructions.xlsx diff --git a/mips-isa.pdf b/reference/mips-isa.pdf similarity index 100% rename from mips-isa.pdf rename to reference/mips-isa.pdf diff --git a/reference/reference.txt b/reference/reference.txt index 8583183..21d1887 100644 --- a/reference/reference.txt +++ b/reference/reference.txt @@ -1,61 +1,66 @@ == Instruction == -C code Assembly code Hex code Reference Output ================ -ADDIU Add immediate unsigned (no overflow) +==ADDIU Add immediate unsigned (no overflow)== + +ORI $4,$0,0xA +JR $0 +ADDIU $2,$4,20 + +3404000a +00000008 +24820014 + +register_v0 = 30 == ADDU Add unsigned (no overflow) == -int main(void) { - int a = 3 + 5; -} - ORI $4,$0,3 ORI $5,$0,5 -ADDU $2,$4,$5 JR $0 +ADDU $2,$4,$5 34040003 34050005 -00851021 00000008 +00851021 register_v0 = 8 ==AND Bitwise and== -ORI $5,$0,0xCCCC -LUI $5,0xCCCC -ORI $4,$0,0xAAAA -LUI $4,0xAAAA -AND $2,$4,$5 +LUI $5,0xCCCC +ORI $5,$5,0xCCCC +LUI $4,0xAAAA +ORI $4,$4,0xAAAA JR $0 +AND $2,$4,$5 -3405cccc -3c05cccc -3404aaaa +3c05cccc +34A5cccc 3c04aaaa -00851024 +3484aaaa 00000008 +00851024 -register_v0 = 0x88888888 +register_v0 = 0x88888888 / 2290649224 ==ANDI Bitwise and immediate== +LUI $4,0xAAAA ORI $4,$0,0xAAAA -LUI $4,0xAAAA -ANDI $2,$4,0xCCCC JR $0 +ANDI $2,$4,0xCCCC -3404aaaa 3c04aaaa -3082cccc +3404aaaa 00000008 +3082cccc -register_v0 = 0x00008888 +register_v0 = 0x00008888 / 34952 ==BEQ Branch on equal== @@ -171,7 +176,7 @@ NOP ORI $2,$0,1 JR $0 -3C05FFFF +3C04FFFF 04800003 00000000 00000008 @@ -247,15 +252,15 @@ register_v0 = 3 ==DIVU Divide unsigned== //May need other testcases for -ve/+ve, -ve/-ve -LUI $4,0x8000 +LUI $4,0x8000 ORI $5,$0,2 DIVU $4,$5 MFHI $4 -MFLO $5 +MFLO $5 ADDU $2,$4,$5 JR $0 -34048000 +3C048000 34050002 0085001B 00002010 @@ -263,7 +268,7 @@ JR $0 00851021 00000008 -register_v0 = 0x40000000 +register_v0 = 0x40000000 / 1073741824 ==J Jump== @@ -285,8 +290,8 @@ register_v0 = 1 ==JALR Jump and link register== -ORI $5,$0,0x001C LUI $5,0xBFC0 +ORI $5,$5,0x001C JALR $4,$5 NOP ADDIU $2,$2,1 @@ -295,8 +300,8 @@ NOP ORI $2,$0,1 JR $4 -3405001C 3C05BCF0 +34A5001C 00A02009 00000000 24420001 @@ -329,36 +334,46 @@ register_v0 = 2 ==JR Jump register== -ORI $5,$0,0x0014 LUI $5,0xBFC0 +ORI $5,$5,0x0014 JR $5 NOP JR $0 NOP -ORI $2,$0,1 +ORI $2,$0,0xA JR $0 -34050014 -3C05BCF0 +3C05BFC0 +34A50014 00A00008 00000000 00000008 -34020001 +3402000A 00000008 -register_v0 = 1 +register_v0 = 10 + +-Branch Delay slot test + +JR $0 +ORI $2,$0,5 + +00000008 +34020005 + +register_v0 = 5 ==LB Load byte== -ORI $4,$0,0x1003 -LB $2,3($4) +ORI $4,$0,0x1001 JR $0 +LB $2,5($4) -Instruction Hex -34041003 -80820003 +34041001 00000008 +80820005 -Memory Hex @@ -367,94 +382,94 @@ JR $0 00000000 00000000 -register_v0 = 0xFFFFFF8A +register_v0 = 0xFFFFFF8A / 4294967178 ==LBU Load byte unsigned== -ORI $4,$0,0x1003 -LBU $2,3($4) -JR $0 - --Instruction Hex - -34041003 -90820003 -00000008 - --Memory Hex - -00000000 -008A0000 -00000000 -00000000 - -register_v0 = 0x0000008A - -==LH Load half-word== - -ORI $4,$0,0x1003 -LH $2,4($4) -JR $0 - --Instruction Hex - -34041003 -84820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0xFFFF8123 - -==LHU Load half-word unsigned== - -ORI $4,$0,0x1003 -LHU $2,4($4) -JR $0 - --Instruction Hex - -34041003 -94820004 -00000008 - --Memory Hex - -00000000 -00008123 -00000000 -00000000 - -register_v0 = 0x00008123 - -==LUI Load upper immediate== - -ORI $2,$0,0x5678 -LUI $2,0x1234 -JR $0 - -34045678 -3C021234 -00000008 - -register_v0 = 0x12345678 - -==LW Load word== - ORI $4,$0,0x1002 -LW $2, 2($4) JR $0 +LBU $2,4($4) -Instruction Hex 34041002 -8C820002 00000008 +90820004 + +-Memory Hex + +00000000 +008A0000 +00000000 +00000000 + +register_v0 = 0x0000008A / 138 + +==LH Load half-word== + +ORI $4,$0,0x1000 +JR $0 +LH $2,4($4) + +-Instruction Hex + +34041003 +00000008 +84820004 + +-Memory Hex + +00000000 +00008123 +00000000 +00000000 + +register_v0 = 0xFFFF8123 / 4294934819 + +==LHU Load half-word unsigned== + +ORI $4,$0,0x1000 +JR $0 +LHU $2,4($4) + +-Instruction Hex + +34041000 +00000008 +94820004 + +-Memory Hex + +00000000 +00008123 +00000000 +00000000 + +register_v0 = 0x00008123 / 33059 + +==LUI Load upper immediate== + +LUI $2,0x1234 +ORI $2,$2,0x5678 +JR $0 + +3C021234 +34425678 +00000008 + +register_v0 = 0x12345678 / 305419896 + +==LW Load word== + +ORI $4,$0,0x1002 +JR $0 +LW $2, 2($4) + +-Instruction Hex + +34041002 +00000008 +8C820002 -Memory Hex @@ -463,21 +478,21 @@ JR $0 00000000 00000000 -register_v0 = 0x12345678 +register_v0 = 0x12345678 / 305419896 ==LWL Load word left== -ORI $4,$0,0x1003 +ORI $4,$0,0x1001 ORI $2,$0,0x5678 -LWL $2,3($4) JR $0 +LWL $2,3($4) -Instruction Hex -34041003 +34041001 34025678 -88820003 00000008 +88820003 -Memory Hex @@ -486,21 +501,21 @@ AAAA1234 00000000 00000000 -register_v0 = 0x12345678 +register_v0 = 0x12345678 / 305419896 ==LWR Load word right== -ORI $4,$0,0x1003 LUI $2,0x1234 -LWR $2,2($4) +ORI $4,$0,0x1002 JR $0 +LWR $2,3($4) -Instruction Hex -34041003 3C021234 -98820002 +34041002 00000008 +98820003 -Memory Hex @@ -509,56 +524,335 @@ JR $0 00000000 00000000 -register_v0 = 0x12345678 +register_v0 = 0x12345678 / 305419896 -// DIVU Divide unsigned +==MTHI Move to HI== -// DIV Divide +ori $4, $0, 5 +mthi $4 +mfhi $2 +jr $0 -//MFHI Move from Hi +34040005 +00800011 +00001010 +00000008 -//MFLO Move from lo +register_v0 = 5 -//MTHI Move to HI +==MTLO Move to LO== -//MTLO Move to LO +ori $4, $0, 5 +mtlo $4 +mflo $2 +jr $0 -//MULT Multiply** +34040005 +00800013 +00001012 +00000008 -//MULTU Multiply unsigned** +register_v0 = 5 -//OR Bitwise or +==MULT Multiply== -//ORI Bitwise or immediate +ori $4, $0, 4 +ori $5, $0, 3 +mult $4, $5 +mflo $2 +jr $0 -//SB Store byte +34040004 +34050003 +00850018 +00001012 +00000008 -//SH Store half-word** +register_v0 = 12 -//SLL Shift left logical +==MULTU Multiply unsigned== -//SLLV Shift left logical variable +ori $4, $0, 4 +ori $5, $0, 3 +multu $4, $5 +mflo $2 +jr $0 -//SLT Set on less than (signed) +34040004 +34050003 +00850019 +00001012 +00000008 -//SLTI Set on less than immediate (signed) +register_v0 = 12 -//SLTIU Set on less than immediate unsigned +==OR Bitwise or== -//SLTU Set on less than unsigned +ori $4, $0, 5 +ori $5, $0, 3 +jr $0 +or $2, $4, $5 -//SRA Shift right arithmetic +34040005 +34050003 +00000008 +00851025 -//SRAV Shift right arithmetic +register_v0 = 7 -//SRL Shift right logical +==ORI Bitwise or immediate== -//SRLV Shift right logical variable +ori $4, $0, 0xFFFF +ori $5, $0, 0x1234 +jr $0 +or $2, $4, $5 -//SUBU Subtract unsigned +3404FFFF +34051234 +00851025 +00000008 -//SW Store word +register_v0 = 65535 -//XOR Bitwise exclusive or +==SB Store byte== -//XORI Bitwise exclusive or immediate +lui $4, 0x1234 +ori $4, $0, 0x5678 +lui $5, 0xBFC0 +ori $5, $0, 0x001C +sb $4, 0($5) +lb $2, 0($5) +jr $0 + +3C041234 +34045678 +3C05BFC0 +3405001C +A0A40000 +80A20000 +00000008 + +register_v0 = 0x00000078 + +==SH Store half-word== + +lui $4, 0x1234 +ori $4, $0, 0x5678 +lui $5, 0xBFC0 +ori $5, $0, 0x001C +sh $4, 0($5) +lh $2, 0($5) +jr $0 + +3C041234 +34045678 +3C05BFC0 +3405001C +A4A40000 +84A40000 +00000008 + +register_v0 = 0x00005678 + +==SLL Shift left logical== + +ori $4,$0,3 +jr $0 +sll $2,$4,2 + + +34040003 +00000008 +00041080 + +register_v0 = 12 + +==SLLV Shift left logical variable== + +ori $4,$0,2 +ori $5,$0,3 +jr $0 +sllv $2,$5,$4 + +34040002 +34050003 +00000008 +00851004 + +register_v0 = 12 + +==SLT Set on less than (signed)== + +ORI $4 $zero 0xFFFF +ORI $5 $zero 0x000B +jr $0 +SLT $2 $4 $5 + +3404FFFF +3405000B +00000008 +0085102A + +register_v0 = 0 + +==SLTI Set on less than immediate (signed)== + +ori $4, $0, 10 +jr $0 +slti $2, $4, 9 + +3404000a +00000008 +28820009 + +register_v0 = 0 + +==SLTIU Set on less than immediate unsigned== + +ori $4, $0, 10 +jr $0 +sltiu $2, $4, 9 + +3404000a +00000008 +2c820009 + +register_v0 = 0 + +==SLTU Set on less than unsigned== + +ori $4, $0, 10 +ori $5, $0, 9 +jr $0 +sltu $2, $4, $5 + +3404000a +34050009 +00000008 +0085102b + +register_v0 = 0 + +==SRA Shift right arithmetic== + +lui $5 $0,0xF000 +jr $0 +srav $2,$5,2 + +3C05F000 +00000008 +00051083 + +register_v0 = 0xFC000000 / 4227858432 + +==SRAV Shift right arithmetic variable== + +ori $4,$0,2 +lui $5, 0xF000 +jr $0 +srav $2,$5,$4 + +34040002 +3C05F000 +00000008 +00851007 + +register_v0 = 0xFC000000 / 4227858432 + +==SRL Shift right logical== + +ori $4,$0,16 +jr $0 +srl $2,$4,2 + +34040010 +00000008 +00041082 + +register_v0 = 4 + +==SRLV Shift right logical variable== + +ori $4,$0,2 +ori $5,$0,16 +jr $0 +srlv $2,$5,$4 + +34040002 +34050010 +00000008 +00851006 + +register_v0 = 4 + +==SUBU Subtract unsigned== + +ori $4,$0,5 +ori $5,$0,3 +jr $0 +subu $2,$4,$5 + +34040005 +34050003 +00000008 +00851023 + +register_v0 = 2 + +==SW Store word== + +ori $4, $0, 0xFFFF +ori $5, $0, 0x1008 +sw $4, 4($5) +lw $2, 4($5) +jr $0 + +3404FFFF +34051008 +ACA40004 +8CA20004 +00000008 + +register_v0 = 0x0000FFFF / 65535 + +-Negative Offset + +ori $4, $0, 0xFFFF +ori $5, $0, 0x1008 +sw $4, -4($5) +lw $2, -4($5) +jr $0 + +3404FFFF +34051008 +ACA4FFFC +8CA2FFFC +00000008 + +register_v0 = 0x0000FFFF / 65535 + +==XOR Bitwise exclusive or== + +ori $4, $0, 5 +ori $5, $0, 2 +jr $0 +xor $2, $4, $5 + +34040005 +34050002 +00000008 +00851026 + +register_v0 = 7 + +==XORI Bitwise exclusive or immediate== + +ori $4,$0,5 +jr $0 +xori $2,$4,0x000F + +34040005 +00000008 +3882000F + +register_v0 = 10 diff --git a/structure.png b/reference/structure.png similarity index 100% rename from structure.png rename to reference/structure.png diff --git a/test/test_mips_cpu_harvard.sh b/test/test_mips_cpu_harvard.sh index 19cb6b7..e5cd348 100755 --- a/test/test_mips_cpu_harvard.sh +++ b/test/test_mips_cpu_harvard.sh @@ -25,7 +25,7 @@ then -s mips_cpu_harvard_tb \ -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \ -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\ ${SRC} 2> /dev/null ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference @@ -46,7 +46,7 @@ else -s mips_cpu_harvard_tb \ -P mips_cpu_harvard_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ -P mips_cpu_harvard_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v \ + -o exec/mips_cpu_harvard_tb_${TESTCASE} testbench/mips_cpu_harvard_tb.v testbench/mips_cpu_memory.v\ ${SRC} 2> /dev/null ./exec/mips_cpu_harvard_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference diff --git a/rtl/mips_cpu_memory.v b/testbench/mips_cpu_memory.v similarity index 100% rename from rtl/mips_cpu_memory.v rename to testbench/mips_cpu_memory.v From 2eccc5148ec8103e0beb13117262fac53bdefaea Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 13:58:07 +0000 Subject: [PATCH 18/28] Move bus memory from rtl to testbench folder --- test/test_mips_cpu_bus.sh | 4 ++-- {rtl => testbench}/mips_cpu_bus_memory.v | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename {rtl => testbench}/mips_cpu_bus_memory.v (100%) diff --git a/test/test_mips_cpu_bus.sh b/test/test_mips_cpu_bus.sh index 1b90fe7..a24afa6 100755 --- a/test/test_mips_cpu_bus.sh +++ b/test/test_mips_cpu_bus.sh @@ -25,7 +25,7 @@ then -s mips_cpu_bus_tb \ -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \ -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v \ + -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_bus_cpu_memory.v \ ${SRC} 2> /dev/null ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference @@ -46,7 +46,7 @@ else -s mips_cpu_bus_tb \ -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.txt\" \ -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${INSTR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v \ + -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \ ${SRC} 2> /dev/null ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${INSTR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${INSTR}/${TESTCASE}.log.txt)" > ./inputs/${INSTR}/${TESTCASE}.out.txt; # register v0 output to compare with reference diff --git a/rtl/mips_cpu_bus_memory.v b/testbench/mips_cpu_bus_memory.v similarity index 100% rename from rtl/mips_cpu_bus_memory.v rename to testbench/mips_cpu_bus_memory.v From e89087c127c619006b4c1d9a50deec9ead607437 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 06:34:42 -0800 Subject: [PATCH 19/28] Bus Memory typo in bus script --- test/test_mips_cpu_bus.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/test_mips_cpu_bus.sh b/test/test_mips_cpu_bus.sh index a24afa6..17c1dde 100755 --- a/test/test_mips_cpu_bus.sh +++ b/test/test_mips_cpu_bus.sh @@ -25,7 +25,7 @@ then -s mips_cpu_bus_tb \ -P mips_cpu_bus_tb.INSTR_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.txt\" \ -P mips_cpu_bus_tb.DATA_INIT_FILE=\"inputs/${DIR}/${TESTCASE}.data.txt\" \ - -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_bus_cpu_memory.v \ + -o exec/mips_cpu_bus_tb_${TESTCASE} testbench/mips_cpu_bus_tb.v testbench/mips_cpu_bus_memory.v \ ${SRC} 2> /dev/null ./exec/mips_cpu_bus_tb_${TESTCASE} &> ./inputs/${DIR}/${TESTCASE}.log.txt; # log file for debugging (contains $display) echo "$(tail -1 ./inputs/${DIR}/${TESTCASE}.log.txt)" > ./inputs/${DIR}/${TESTCASE}.out.txt; # register v0 output to compare with reference From 74681e88905b74980280933019c5e9144e748d67 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 07:34:32 -0800 Subject: [PATCH 20/28] Stall bus memory when reset is high --- testbench/mips_cpu_bus_memory.v | 14 ++++++++++++-- testbench/mips_cpu_bus_tb.v | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/testbench/mips_cpu_bus_memory.v b/testbench/mips_cpu_bus_memory.v index a2f47f2..822c423 100644 --- a/testbench/mips_cpu_bus_memory.v +++ b/testbench/mips_cpu_bus_memory.v @@ -1,5 +1,6 @@ module mips_cpu_bus_memory( //Avalon memory mapped bus controller (slave) input logic clk, + input logic reset, input logic[31:0] address, input logic write, input logic read, @@ -43,10 +44,20 @@ initial begin for (integer i = 0; i<$size(data_memory); i++) begin //Read out data contents to log $display("byte +%h: %h", 32'h00001000+i*4, data_memory[i]); end + + waitrequest = 1'b0; // set waitrequest low to begin + readdata = 32'h00000000; // set readdata low to begin + +end + +always_comb begin + if (reset) begin + waitrequest = 1'b0; + end end always_ff @(posedge read or posedge write) begin - waitrequest <= 1; + waitrequest <= 1'b1; end always_ff @(posedge clk) begin @@ -86,5 +97,4 @@ always_ff @(posedge clk) begin end end - endmodule \ No newline at end of file diff --git a/testbench/mips_cpu_bus_tb.v b/testbench/mips_cpu_bus_tb.v index ee7afa8..bb93aaf 100644 --- a/testbench/mips_cpu_bus_tb.v +++ b/testbench/mips_cpu_bus_tb.v @@ -10,6 +10,7 @@ logic[3:0] byteenable; mips_cpu_bus_memory #(INSTR_INIT_FILE, DATA_INIT_FILE) memInst( //Avalon memory mapped bus controller (slave) .clk(clk), // clk input to mem + .reset(reset), // reset input to stall mem during cpu reset .address(address), // addr input to mem .write(write), // write flag input .read(read), // read flag input From 1ae5d78b4d040b0442f948e117d4f7a301e3d3ba Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 07:58:33 -0800 Subject: [PATCH 21/28] Added dummy clk_enable to harvard instance, added clock kickstart after reset --- rtl/mips_cpu_bus.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index ca117dd..c120971 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -30,6 +30,7 @@ logic clk_state; // make sure posedge and negedge of clk do not occur repeatedly logic partial_write; // flag to control datapath when doing a partial write logic[31:0] partial_writedata; // modified data for partial writes (StoreHalfword or StoreByte) logic[31:0] write_data_address; // modified data address for partial writes +logic clk_enable; // unused floating wire initial begin clk_internal = 1'b0; @@ -44,6 +45,11 @@ initial begin clk_state = 0; end +always_ff @(negedge reset) begin // kickstart clock after reset + clk_internal <= 1'b1; + state <= 2'b00; +end + always_ff @(posedge clk) begin // CLK Rising Edge if (!waitrequest && !clk_state) begin case (n_state) @@ -212,7 +218,7 @@ mips_cpu_harvard mips_cpu_harvard( // Harvard CPU within wrapper .reset(reset), // CPU reset, input .active(active), // Is CPU active, output .register_v0(register_v0), // $2 / $v0 debug bus, output -.clk_enable(1'b0), // unused clock enable, input +.clk_enable(clk_enable), // unused clock enable, input .instr_address(harvard_instr_address), // instr addr from pc, output .instr_readdata(instr_reg), // cached instruction passed into harvard cpu, input .data_address(harvard_data_address), // harvard data memory address, output From 2be1978a3677b16e0a324efeaf14a51a2748eea0 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 08:43:58 -0800 Subject: [PATCH 22/28] Add initial value to npc, add JR to CtrlMemRead --- rtl/mips_cpu_control.v | 2 ++ rtl/mips_cpu_npc.v | 1 + test/test_mips_cpu_custom_bus.sh | 0 3 files changed, 3 insertions(+) mode change 100644 => 100755 test/test_mips_cpu_custom_bus.sh diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index 5ce988b..08e1eae 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -124,6 +124,8 @@ always @(*) begin CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi end else if ((op==SPECIAL)&&(funct == MFLO))begin CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo + end else if ((op==SPECIAL)&&(funct == JR))begin + CtrlMemRead = 0;//Read disabled during jump end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes $display("OP: %d, Funct: %d", op, funct); //CtrlALUOp Logic diff --git a/rtl/mips_cpu_npc.v b/rtl/mips_cpu_npc.v index 53cc2ae..1971762 100644 --- a/rtl/mips_cpu_npc.v +++ b/rtl/mips_cpu_npc.v @@ -9,6 +9,7 @@ reg[31:0] npc_curr; initial begin npc_curr = (32'hBFC00000 + 32'd4); + npc_out = 32'hBFC00000; end // initial always_comb begin diff --git a/test/test_mips_cpu_custom_bus.sh b/test/test_mips_cpu_custom_bus.sh old mode 100644 new mode 100755 From ad394c7d7d7bc67b66322895571a8934db12b6cd Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 09:02:58 -0800 Subject: [PATCH 23/28] Adding missing opcodes to CtrlMemRead --- rtl/mips_cpu_control.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index 2bab8f5..86ec213 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -117,7 +117,7 @@ always @(*) begin CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi end else if ((op==SPECIAL)&&(funct == MFLO))begin CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo - end else if ((op==SPECIAL)&&(funct == JR))begin + end else if (((op==SPECIAL)&&(funct == JR)) || (op == BEQ) || ((op==REGIMM)&&(rt==BGEZ)) || (op==BGTZ) || ((op==REGIMM)&&(rt==BLTZ)) || (op==BLEZ) || (op==BNE) || (op==J))begin CtrlMemRead = 0;//Read disabled during jump end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes From c8344184b2fc70a7a218a1b652fe6a2047e8e9a4 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 09:41:25 -0800 Subject: [PATCH 24/28] Fix sb, sh testcases Tried to write to instr mem + typo --- inputs/sb/sb-1.txt | 5 ++--- inputs/sh/sh-1.txt | 7 +++---- reference/reference.txt | 14 +++++--------- 3 files changed, 10 insertions(+), 16 deletions(-) diff --git a/inputs/sb/sb-1.txt b/inputs/sb/sb-1.txt index a2e8fd6..c42c078 100644 --- a/inputs/sb/sb-1.txt +++ b/inputs/sb/sb-1.txt @@ -1,7 +1,6 @@ 3C041234 34045678 -3C05BFC0 -3405001C +3405101C A0A40000 80A20000 -00000008 \ No newline at end of file +00000008 diff --git a/inputs/sh/sh-1.txt b/inputs/sh/sh-1.txt index 17b333d..2203c02 100644 --- a/inputs/sh/sh-1.txt +++ b/inputs/sh/sh-1.txt @@ -1,7 +1,6 @@ 3C041234 34045678 -3C05BFC0 -3405001C +3405101C A4A40000 -84A40000 -00000008 \ No newline at end of file +84A20000 +00000008 diff --git a/reference/reference.txt b/reference/reference.txt index 871f768..dd52c48 100644 --- a/reference/reference.txt +++ b/reference/reference.txt @@ -662,16 +662,14 @@ register_v0 = 65535 lui $4, 0x1234 ori $4, $0, 0x5678 -lui $5, 0xBFC0 -ori $5, $0, 0x001C +ori $5, $0, 0x101C sb $4, 0($5) lb $2, 0($5) jr $0 3C041234 34045678 -3C05BFC0 -3405001C +3405101C A0A40000 80A20000 00000008 @@ -682,18 +680,16 @@ register_v0 = 0x00000078 lui $4, 0x1234 ori $4, $0, 0x5678 -lui $5, 0xBFC0 -ori $5, $0, 0x001C +ori $5, $0, 0x101C sh $4, 0($5) lh $2, 0($5) jr $0 3C041234 34045678 -3C05BFC0 -3405001C +3405101C A4A40000 -84A40000 +84A20000 00000008 register_v0 = 0x00005678 From 6687cb8e171e7d4c896846d2663c2a565d5af7b2 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 09:43:04 -0800 Subject: [PATCH 25/28] Bring read signal low with clk during read cycle --- rtl/mips_cpu_bus.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/mips_cpu_bus.v b/rtl/mips_cpu_bus.v index c120971..478766c 100644 --- a/rtl/mips_cpu_bus.v +++ b/rtl/mips_cpu_bus.v @@ -193,7 +193,7 @@ always_comb begin end 2'b10: begin // connecting wires when in read state address = harvard_data_address; - read = 1'b1; + read = clk_internal ? 1'b1 : 1'b0; write = 1'b0; byteenable = 4'b1111; harvard_readdata = readdata; From e513096ed85d81f5717a7f46c2e18f936e63458c Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 09:43:47 -0800 Subject: [PATCH 26/28] Add missing opcodes to CtrlMemRead = 0 --- rtl/mips_cpu_control.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/mips_cpu_control.v b/rtl/mips_cpu_control.v index 86ec213..af5d76f 100644 --- a/rtl/mips_cpu_control.v +++ b/rtl/mips_cpu_control.v @@ -117,7 +117,7 @@ always @(*) begin CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi end else if ((op==SPECIAL)&&(funct == MFLO))begin CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo - end else if (((op==SPECIAL)&&(funct == JR)) || (op == BEQ) || ((op==REGIMM)&&(rt==BGEZ)) || (op==BGTZ) || ((op==REGIMM)&&(rt==BLTZ)) || (op==BLEZ) || (op==BNE) || (op==J))begin + end else if (((op==SPECIAL)&&(funct == JR)) || (op == BEQ) || (op==SW) ||((op==REGIMM)&&(rt==BGEZ)) || (op==BGTZ) || ((op==REGIMM)&&(rt==BLTZ)) || (op==BLEZ) || (op==BNE) || (op==J) || ((op==SPECIAL)&&(funct==MTHI)) || ((op==SPECIAL)&&(funct==MTLO)) || ((op==SPECIAL)&&(funct==MULT)) || ((op==SPECIAL)&&(funct==MULTU)) || ((op==SPECIAL)&&(funct==DIV)) || ((op==SPECIAL)&&(funct==DIVU)) || (op==SB) || (op==SH))begin CtrlMemRead = 0;//Read disabled during jump end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes From 5c29ec2be186ec91f070a4a6bb9e8feb0c3b400f Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 09:44:31 -0800 Subject: [PATCH 27/28] Shorten testbench limit, remove custom bus script --- test/test_mips_cpu_custom_bus.sh | 67 -------------------------------- testbench/mips_cpu_bus_tb.v | 2 +- 2 files changed, 1 insertion(+), 68 deletions(-) delete mode 100755 test/test_mips_cpu_custom_bus.sh diff --git a/test/test_mips_cpu_custom_bus.sh b/test/test_mips_cpu_custom_bus.sh deleted file mode 100755 index 2fca13f..0000000 --- a/test/test_mips_cpu_custom_bus.sh +++ /dev/null @@ -1,67 +0,0 @@ -#!/bin/bash - -# arithmetic -./test/test_mips_cpu_bus.sh rtl addu #Pass -./test/test_mips_cpu_bus.sh rtl addiu #Pass -./test/test_mips_cpu_bus.sh rtl subu #Pass -./test/test_mips_cpu_bus.sh rtl and #Pass -./test/test_mips_cpu_bus.sh rtl andi #Pass -./test/test_mips_cpu_bus.sh rtl or #Pass -./test/test_mips_cpu_bus.sh rtl ori #Pass -./test/test_mips_cpu_bus.sh rtl xor #Pass -./test/test_mips_cpu_bus.sh rtl xori #Pass -./test/test_mips_cpu_bus.sh rtl div #Pass -./test/test_mips_cpu_bus.sh rtl divu #pass -./test/test_mips_cpu_bus.sh rtl mthi #Pass -./test/test_mips_cpu_bus.sh rtl mtlo #Pass -./test/test_mips_cpu_bus.sh rtl mult #Pass -./test/test_mips_cpu_bus.sh rtl multu #Pass - - -# branches -./test/test_mips_cpu_bus.sh rtl beq #Pass -./test/test_mips_cpu_bus.sh rtl bgez #Pass -./test/test_mips_cpu_bus.sh rtl bgezal #Pass -./test/test_mips_cpu_bus.sh rtl bgtz #Pass -./test/test_mips_cpu_bus.sh rtl blez #Pass -./test/test_mips_cpu_bus.sh rtl bltz #Pass -./test/test_mips_cpu_bus.sh rtl bltzal #Pass -./test/test_mips_cpu_bus.sh rtl bne #Pass - -# jumps -./test/test_mips_cpu_bus.sh rtl j #Pass -./test/test_mips_cpu_bus.sh rtl jalr #Pass -./test/test_mips_cpu_bus.sh rtl jal #Pass -./test/test_mips_cpu_bus.sh rtl jr #Pass - -# shift -./test/test_mips_cpu_bus.sh rtl sll #Pass -./test/test_mips_cpu_bus.sh rtl srl #Pass -./test/test_mips_cpu_bus.sh rtl sra #Pass -./test/test_mips_cpu_bus.sh rtl srav #Pass -./test/test_mips_cpu_bus.sh rtl sllv #Pass -./test/test_mips_cpu_bus.sh rtl srlv #Pass - - - -# load & store -./test/test_mips_cpu_bus.sh rtl lw #Pass -./test/test_mips_cpu_bus.sh rtl lb #Pass -./test/test_mips_cpu_bus.sh rtl lbu #Pass -./test/test_mips_cpu_bus.sh rtl lh #Pass -./test/test_mips_cpu_bus.sh rtl lhu #Pass -./test/test_mips_cpu_bus.sh rtl lui #Pass -./test/test_mips_cpu_bus.sh rtl lwl #Pass -./test/test_mips_cpu_bus.sh rtl lwr #Pass -./test/test_mips_cpu_bus.sh rtl sw #Pass -./test/test_mips_cpu_bus.sh rtl sb #Once switched to bus -./test/test_mips_cpu_bus.sh rtl sh #Once switched to bus - - -# set on less than **Branch delay slots dont work on these... -./test/test_mips_cpu_bus.sh rtl slti #Pass -./test/test_mips_cpu_bus.sh rtl sltiu #Pass -./test/test_mips_cpu_bus.sh rtl slt #Pass -./test/test_mips_cpu_bus.sh rtl sltu #Pass - - diff --git a/testbench/mips_cpu_bus_tb.v b/testbench/mips_cpu_bus_tb.v index bb93aaf..4bd0d89 100644 --- a/testbench/mips_cpu_bus_tb.v +++ b/testbench/mips_cpu_bus_tb.v @@ -2,7 +2,7 @@ module mips_cpu_bus_tb; parameter INSTR_INIT_FILE = ""; parameter DATA_INIT_FILE = ""; -parameter TIMEOUT_CYCLES = 1000; // Timeout cycles are higher to account for memory stall delays +parameter TIMEOUT_CYCLES = 100; // Timeout cycles are higher to account for memory stall delays logic clk, reset, active, write, read, waitrequest; logic[31:0] address, register_v0, writedata, readdata; From 1be11d6c199fad8385b7d085a93a4bd17ec0bc21 Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 17 Dec 2020 09:52:51 -0800 Subject: [PATCH 28/28] Add second store halfword testcase Checks that only half the word is written using load word after store halfword --- inputs/sh/sh-2.ref.txt | 1 + inputs/sh/sh-2.txt | 6 ++++++ reference/reference.txt | 16 ++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 inputs/sh/sh-2.ref.txt create mode 100644 inputs/sh/sh-2.txt diff --git a/inputs/sh/sh-2.ref.txt b/inputs/sh/sh-2.ref.txt new file mode 100644 index 0000000..2bb616a --- /dev/null +++ b/inputs/sh/sh-2.ref.txt @@ -0,0 +1 @@ +22136 \ No newline at end of file diff --git a/inputs/sh/sh-2.txt b/inputs/sh/sh-2.txt new file mode 100644 index 0000000..bbbbdf7 --- /dev/null +++ b/inputs/sh/sh-2.txt @@ -0,0 +1,6 @@ +3C041234 +34045678 +3405101C +A4A40000 +8CA20000 +00000008 diff --git a/reference/reference.txt b/reference/reference.txt index dd52c48..8d2d791 100644 --- a/reference/reference.txt +++ b/reference/reference.txt @@ -692,6 +692,22 @@ A4A40000 84A20000 00000008 +-Load Entire Word Version + +lui $4, 0x1234 +ori $4, $0, 0x5678 +ori $5, $0, 0x101C +sh $4, 0($5) +lw $2, 0($5) +jr $0 + +3C041234 +34045678 +3405101C +A4A40000 +8CA20000 +00000008 + register_v0 = 0x00005678 ==SLL Shift left logical==