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Debug mult/div to work

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it works now
This commit is contained in:
jl7719 2020-12-16 08:38:46 +00:00
parent 4ff160db1a
commit 0891f7e653
25 changed files with 146 additions and 59 deletions
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4
inputs/and/and-1.txt
View file

@ -1,6 +1,6 @@
3c05cccc 3c05cccc
3405cccc 34A5cccc
3c04aaaa 3c04aaaa
3404aaaa 3484aaaa
00851024 00851024
00000008 00000008

1
inputs/bgez/bgez-2.ref.txt Normal file
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@ -0,0 +1 @@
5

7
inputs/bgez/bgez-2.txt Normal file
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@ -0,0 +1,7 @@
34040003
04810003
00000000
24420001
00000000
24420005
00000008

3
inputs/bltz/bltz-1.txt
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@ -1,4 +1,5 @@
3C05FFFF 3C04FFFF
00000000
04800003 04800003
00000000 00000000
00000008 00000008

2
inputs/divu/divu-1.txt
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@ -1,4 +1,4 @@
34048000 3C048000
34050002 34050002
0085001B 0085001B
00002010 00002010

2
inputs/jr/jr-1.txt
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@ -3,5 +3,5 @@
00A00008 00A00008
00000000 00000000
00000008 00000008
34020001 3402000A
00000008 00000008

2
inputs/lwl/lwl-1.txt
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@ -1,4 +1,4 @@
34041003 34041001
34025678 34025678
88820003 88820003
00000008 00000008

1
inputs/mult/mult-1.txt
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@ -2,4 +2,5 @@
34050003 34050003
00850018 00850018
00001012 00001012
00000000
00000008 00000008

2
inputs/ori/ori-1.txt
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@ -1,3 +1,3 @@
34020003 34020003
34420005
00000008 00000008
34020005

1
inputs/ori/ori-2.ref.txt Normal file
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@ -0,0 +1 @@
65535

4
inputs/ori/ori-2.txt Normal file
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@ -0,0 +1,4 @@
3404FFFF
34052134
00851025
00000008

2
inputs/slt/slt-1.txt
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@ -1,4 +1,4 @@
3404FFFF 3404000F
3405000B 3405000B
0085102A 0085102A
00000008 00000008

1
inputs/slt/slt-2.ref.txt Normal file
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@ -0,0 +1 @@
0

4
inputs/slt/slt-2.txt Normal file
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@ -0,0 +1,4 @@
3404FFFF
3405000B
0085102A
00000008

2
inputs/srav/srav-1.txt
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@ -1,4 +1,4 @@
34040004 34040002
3C05F000 3C05F000
00851007 00851007
00000008 00000008

2
inputs/sw/sw-1.txt
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@ -1,5 +1,5 @@
3404FFFF 3404FFFF
34051008 34051008
ACA40000 ACA40004
8CA20004 8CA20004
00000008 00000008

1
inputs/sw/sw-2.ref.txt Normal file
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@ -0,0 +1 @@
65535

5
inputs/sw/sw-2.txt Normal file
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@ -0,0 +1,5 @@
3404FFFF
34051008
ACA4FFFC
8CA2FFFC
00000008

76
reference.txt
View file

@ -33,16 +33,16 @@ register_v0 = 8
==AND Bitwise and== ==AND Bitwise and==
LUI $5,0xCCCC LUI $5,0xCCCC
ORI $5,$0,0xCCCC ORI $5,$5,0xCCCC
LUI $4,0xAAAA LUI $4,0xAAAA
ORI $4,$0,0xAAAA ORI $4,$4,0xAAAA
AND $2,$4,$5 AND $2,$4,$5
JR $0 JR $0
3c05cccc 3c05cccc
3405cccc 34A5cccc
3c04aaaa 3c04aaaa
3404aaaa 3484aaaa
00851024 00851024
00000008 00000008
@ -104,6 +104,22 @@ JR $0
register_v0 = 1 register_v0 = 1
ORI $4,$0,3
BGEZ $4,3
NOP
ADDIU $2,$2,1
NOP
ADDIU $2,$2,5
JR $0
34040003
04810003
00000000
24420001
00000000
24420005
00000008
==BGEZAL Branch on non-negative (>=0) and link== ==BGEZAL Branch on non-negative (>=0) and link==
ORI $4,$0,3 ORI $4,$0,3
@ -176,7 +192,7 @@ NOP
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
3C05FFFF 3C04FFFF
04800003 04800003
00000000 00000000
00000008 00000008
@ -260,7 +276,7 @@ MFLO $5
ADDU $2,$4,$5 ADDU $2,$4,$5
JR $0 JR $0
34048000 3C048000
34050002 34050002
0085001B 0085001B
00002010 00002010
@ -343,12 +359,14 @@ NOP
ORI $2,$0,1 ORI $2,$0,1
JR $0 JR $0
3C05BFC0 BFC00014
34050014 0,4,8,c,10,14
00A00008 3C05BFC0 0
00000000 34050014 4
00000008 00A00008 8
34020001 00000000 c
00000008 10
34020001 14
00000008 00000008
register_v0 = 1 register_v0 = 1
@ -472,14 +490,14 @@ register_v0 = 0x12345678
==LWL Load word left== ==LWL Load word left==
ORI $4,$0,0x1003 ORI $4,$0,0x1001
ORI $2,$0,0x5678 ORI $2,$0,0x5678
LWL $2,3($4) LWL $2,3($4)
JR $0 JR $0
-Instruction Hex -Instruction Hex
34041003 34041001
34025678 34025678
88820003 88820003
00000008 00000008
@ -590,18 +608,26 @@ jr $0
register_v0 = 7 register_v0 = 7
==ORI Bitwise or immediate== ==ORI Bitwise or immediate==
ori $2, $0, 3 ori $2, $0, 3
ori $2, $0, 5 ori $2, $2, 5
jr $0 jr $0
34020003 34020003
00000008 00000008
34020005 34420005
register_v0 = 7 register_v0 = 7
ori $4, $0, 0xFFFF
ori $5, $0, 0x1234
or $2, $4, $5
jr $0
register_v0 = 65535
==SB Store byte== ==SB Store byte==
lui $4, 0x1234 lui $4, 0x1234
@ -735,10 +761,12 @@ register_v0 = 0xFC000000
==SRAV Shift right arithmetic variable== ==SRAV Shift right arithmetic variable==
ori $4,$0,2 ori $4,$0,2
lui $5 $0,0xF000 lui $5, 0xF000
srav $2,$5,$4 srav $2,$5,$4
jr $0 jr $0
F000000 -> FC000000
34040004 34040004
3C05F000 3C05F000
00851007 00851007
@ -802,6 +830,20 @@ ACA40004
register_v0 = 0x0000FFFF register_v0 = 0x0000FFFF
ori $4, $0, 0xFFFF
ori $5, $0, 0x1008
sw $4, -4($5)
lw $2, -4($5)
jr $0
3404FFFF
34051008
ACA4FFFC
8CA2FFFC
00000008
register_v0 = 0x0000FFFF
==XOR Bitwise exclusive or== ==XOR Bitwise exclusive or==
ori $4, $0, 5 ori $4, $0, 5

12
rtl/mips_cpu_alu.v
View file

@ -73,8 +73,8 @@ Alu Operations:
// PAS = 5'd19, no need for PAS as it was based on faulty reasoning that speical registers Hi and Lo are in the reg file. // PAS = 5'd19, no need for PAS as it was based on faulty reasoning that speical registers Hi and Lo are in the reg file.
SLT = 5'd20,//signed compare SLT = 5'd20,//signed compare
SLTU = 5'd21,//unsigned compare SLTU = 5'd21,//unsigned compare
MULU = 5'd22,//unsigned divide MULU = 5'd22,//unsigned multiply
DIVU = 5'd23,//unsigned multiply DIVU = 5'd23,//unsigned divide
MTHI = 5'd24, MTHI = 5'd24,
MTLO = 5'd25 MTLO = 5'd25
@ -168,6 +168,7 @@ end
end end
LES: begin LES: begin
$display("ALU A: %h B: %h", $signed(A), $signed(B));
if ($signed(A) < $signed(B)) begin if ($signed(A) < $signed(B)) begin
ALUCond = 1; ALUCond = 1;
end end
@ -225,12 +226,18 @@ end
if ($signed(A) < $signed(B)) begin if ($signed(A) < $signed(B)) begin
ALURes = 1; ALURes = 1;
end end
else begin
ALURes = 0;
end
end end
SLTU: begin SLTU: begin
if (A < B) begin if (A < B) begin
ALURes = 1; ALURes = 1;
end end
else begin
ALURes = 0;
end
end end
MULU: begin MULU: begin
@ -240,6 +247,7 @@ end
end end
DIVU: begin DIVU: begin
$display("ALU A: %h B: %h", A, B);
temp_Lo = A / B; temp_Lo = A / B;
temp_Hi = A % B; temp_Hi = A % B;
end end

21
rtl/mips_cpu_control.v
View file

@ -9,7 +9,7 @@ module mips_cpu_control(
output logic[4:0] CtrlALUOp, output logic[4:0] CtrlALUOp,
output logic[4:0] Ctrlshamt, output logic[4:0] Ctrlshamt,
output logic CtrlMemWrite, output logic CtrlMemWrite,
output logic CtrlALUSrc, output logic[1:0] CtrlALUSrc,
output logic CtrlRegWrite, output logic CtrlRegWrite,
output logic CtrlSpcRegWriteEn output logic CtrlSpcRegWriteEn
); );
@ -104,9 +104,9 @@ always @(*) begin
end else if((op==J) || (op==JAL))begin end else if((op==J) || (op==JAL))begin
CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
$display("Jump PC Ctrl"); $display("Jump PC Ctrl");
end else if((op==SPECIAL)&&(funct==JR) || (funct==JALR))begin end else if((op==SPECIAL)&&((funct==JR) || (funct==JALR)))begin
CtrlPC = 2'd3; // Jumps using Register. CtrlPC = 2'd3; // Jumps using Register.
//$display("Ctrl PC Jump Register"); $display("Ctrl PC Jump Register");
end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word end else begin CtrlPC = 2'd0; /*/$display("Ctrl PC No Jump/Branch");*/end // No jumps or branches, just increment to next word
//CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic where both are concerned. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled. //CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic where both are concerned. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
@ -120,12 +120,12 @@ always @(*) begin
$display("Memory read disabled"); $display("Memory read disabled");
end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)))begin end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)))begin
CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8 CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8
end else if ((op==SPECIAL)&&(funct == MTHI))begin end else if ((op==SPECIAL)&&(funct == MFHI))begin
CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi
end else if ((op==SPECIAL)&&(funct == MTLO))begin end else if ((op==SPECIAL)&&(funct == MFLO))begin
CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo
end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
$display("OP: %d, Funct: %d", op, funct);
//CtrlALUOp Logic //CtrlALUOp Logic
if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin
CtrlALUOp = 5'd0; //ADD from ALUOps CtrlALUOp = 5'd0; //ADD from ALUOps
@ -146,6 +146,7 @@ always @(*) begin
CtrlALUOp = 5'd18;//NEQ from ALUOps CtrlALUOp = 5'd18;//NEQ from ALUOps
end else if((op==SPECIAL)&&(funct==DIV))begin end else if((op==SPECIAL)&&(funct==DIV))begin
CtrlALUOp = 5'd3;//DIV from ALUOps CtrlALUOp = 5'd3;//DIV from ALUOps
$display("DIV CONTROL ALUOps");
end else if((op==SPECIAL)&&(funct==DIVU))begin end else if((op==SPECIAL)&&(funct==DIVU))begin
CtrlALUOp = 5'd23;//DIVU from ALUOps CtrlALUOp = 5'd23;//DIVU from ALUOps
end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
@ -207,20 +208,24 @@ always @(*) begin
end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting. end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting.
//CtrlSpcRegWriteEn logic //CtrlSpcRegWriteEn logic
if((op==SPECIAL)&&((funct==MTHI) || (funct==MTLO)))begin if((op==SPECIAL)&&((funct==MTHI) || (funct==MTLO) || (funct==MULT) || (funct==MULTU) || (funct==DIV) || (funct==DIVU)))begin
CtrlSpcRegWriteEn = 1;//Special register Hi and Lo are write enabled CtrlSpcRegWriteEn = 1;//Special register Hi and Lo are write enabled
$display("Temp being written");
end else begin CtrlSpcRegWriteEn = 0;end//default is 0 to ensure no accidental overwriting. end else begin CtrlSpcRegWriteEn = 0;end//default is 0 to ensure no accidental overwriting.
//CtrlALUSrc logic //CtrlALUSrc logic
if((op==ADDIU) || (op==ANDI) || (op==LUI) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin if((op==ADDIU) || (op==LUI) || (op==SLTI) || (op==SLTIU) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0] CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
end else if((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL))))begin end else if((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL))))begin
CtrlALUSrc = 0;///ALU Bus B is fed from rt. CtrlALUSrc = 0;///ALU Bus B is fed from rt.
end else if ((op==ORI) || (op==ANDI) || (op==XORI)) begin
CtrlALUSrc = 2;
end else begin CtrlALUSrc = 1'bx;end end else begin CtrlALUSrc = 1'bx;end
//CtrlRegWrite logic //CtrlRegWrite logic
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))) begin
CtrlRegWrite = 1;//The Registers are Write Enabled CtrlRegWrite = 1;//The Registers are Write Enabled
$display("OPcode mflo: %h", op);
end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
end end
endmodule endmodule

11
rtl/mips_cpu_harvard.v
View file

@ -29,8 +29,8 @@ assign data_writedata = out_readdata2;
logic[31:0] out_pc_out, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata, out_ALUHi, out_ALULo; logic[31:0] out_pc_out, out_ALURes, out_readdata1, out_readdata2, in_B, in_writedata, out_ALUHi, out_ALULo;
logic[4:0] in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp; logic[4:0] in_readreg1, in_readreg2, in_writereg, out_shamt, out_ALUOp;
logic[5:0] in_opcode; logic[5:0] in_opcode;
logic out_ALUCond, out_RegWrite, out_ALUSrc, out_MemWrite, out_MemRead, out_SpcRegWriteEn; logic out_ALUCond, out_RegWrite, out_MemWrite, out_MemRead, out_SpcRegWriteEn;
logic[1:0] out_RegDst, out_PC; logic[1:0] out_RegDst, out_PC, out_ALUSrc;
logic[2:0] out_MemtoReg; logic[2:0] out_MemtoReg;
assign in_readreg1 = instr_readdata[25:21]; assign in_readreg1 = instr_readdata[25:21];
@ -72,10 +72,13 @@ always @(*) begin
//Picking which output should be taken as the second operand for ALU. //Picking which output should be taken as the second operand for ALU.
case(out_ALUSrc) case(out_ALUSrc)
1'b1:begin 2'd2: begin
in_B = {16'd0,instr_readdata[15:0]};
end
2'd1:begin
in_B = {{16{instr_readdata[15]}},instr_readdata[15:0]};//Output from the 16-bit immediate values sign extened to 32bits. in_B = {{16{instr_readdata[15]}},instr_readdata[15:0]};//Output from the 16-bit immediate values sign extened to 32bits.
end end
1'b0:begin 2'd0:begin
in_B = out_readdata2;//Output from 'Read data 2' port of regfile. in_B = out_readdata2;//Output from 'Read data 2' port of regfile.
end end
endcase endcase

2
rtl/mips_cpu_memory.v
View file

@ -56,7 +56,7 @@ module mips_cpu_memory(
//Synchronous write path //Synchronous write path
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
//$display("Instruction Read: %h", instr_readdata); //$display("Instruction: %h", instr_readdata);
//$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]); //$display("RAM : INFO : data_read=%h, data_address = %h, mem=%h", data_read, data_address, memory[data_address]);
if (data_write) begin //cannot read and write to memory in the same cycle if (data_write) begin //cannot read and write to memory in the same cycle
if (instr_address != data_address) begin //cannot modify the instruction being read if (instr_address != data_address) begin //cannot modify the instruction being read

5
rtl/mips_cpu_regfile.v
View file

@ -77,7 +77,10 @@ always_ff @(negedge clk) begin
2'b11: memory[writereg][7:0] <= writedata[31:24]; 2'b11: memory[writereg][7:0] <= writedata[31:24];
endcase // readdata1[1:0] endcase // readdata1[1:0]
end end
default: memory[writereg] <= writedata; //most instructions default: begin
memory[writereg] <= writedata; //most instructions
$display("Write %d in regfile", writedata);
end
endcase // opcode endcase // opcode
end end
end end

14
test/test_mips_cpu_custom.sh
View file

@ -10,12 +10,12 @@
./test/test_mips_cpu_harvard.sh rtl ori #Pass ./test/test_mips_cpu_harvard.sh rtl ori #Pass
./test/test_mips_cpu_harvard.sh rtl xor #Pass ./test/test_mips_cpu_harvard.sh rtl xor #Pass
./test/test_mips_cpu_harvard.sh rtl xori #Pass ./test/test_mips_cpu_harvard.sh rtl xori #Pass
#./test/test_mips_cpu_harvard.sh rtl div ./test/test_mips_cpu_harvard.sh rtl div #Pass
#./test/test_mips_cpu_harvard.sh rtl divu ./test/test_mips_cpu_harvard.sh rtl divu #pass
#./test/test_mips_cpu_harvard.sh rtl mthi ./test/test_mips_cpu_harvard.sh rtl mthi #Pass
#./test/test_mips_cpu_harvard.sh rtl mtlo ./test/test_mips_cpu_harvard.sh rtl mtlo #Pass
#./test/test_mips_cpu_harvard.sh rtl mult ./test/test_mips_cpu_harvard.sh rtl mult #Pass
#./test/test_mips_cpu_harvard.sh rtl multu ./test/test_mips_cpu_harvard.sh rtl multu #Pass
# branches # branches
@ -24,7 +24,7 @@
#./test/test_mips_cpu_harvard.sh rtl bgezal #Place return address thing how?? #./test/test_mips_cpu_harvard.sh rtl bgezal #Place return address thing how??
./test/test_mips_cpu_harvard.sh rtl bgtz #Pass ./test/test_mips_cpu_harvard.sh rtl bgtz #Pass
./test/test_mips_cpu_harvard.sh rtl blez #Pass ./test/test_mips_cpu_harvard.sh rtl blez #Pass
#./test/test_mips_cpu_harvard.sh rtl bltz #Probably fails due to jump register thing? ./test/test_mips_cpu_harvard.sh rtl bltz #Probably fails due to jump register thing?
./test/test_mips_cpu_harvard.sh rtl bltzal #Pass ./test/test_mips_cpu_harvard.sh rtl bltzal #Pass
./test/test_mips_cpu_harvard.sh rtl bne #Pass ./test/test_mips_cpu_harvard.sh rtl bne #Pass