ELEC50010-IAC-CW/rtl/mips_cpu_control.v

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module mips_cpu_control(
input logic[31:0] Instr,
input logic ALUCond,
output logic[1:0] CtrlRegDst,
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output logic[1:0] CtrlPC,
output logic CtrlMemRead,
output logic[2:0] CtrlMemtoReg,
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output logic[4:0] CtrlALUOp,
output logic[4:0] Ctrlshamt,
output logic CtrlMemWrite,
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output logic[1:0] CtrlALUSrc,
output logic CtrlRegWrite,
output logic CtrlSpcRegWriteEn
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);
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typedef enum logic[5:0]{
SPECIAL = 6'd0,
REGIMM = 6'd1,
J = 6'd2,
JAL = 6'd3,
BEQ = 6'd4,
BNE = 6'd5,
BLEZ = 6'd6,
BGTZ = 6'd7,
ADDI = 6'd8,
ADDIU = 6'd9,
SLTI = 6'd10,
SLTIU = 6'd11,
ANDI = 6'd12,
ORI = 6'd13,
XORI = 6'd14,
LUI = 6'd15,
LB = 6'd32,
LH = 6'd33,
LWL = 6'd34,
LW = 6'd35,
LBU = 6'd36,
LHU = 6'd37,
LWR = 6'd38,
SB = 6'd40,
SH = 6'd41,
SW = 6'd43
} op_enum;
op_enum op;
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typedef enum logic[5:0]{
SLL = 6'd0,
SRL = 6'd2,
SRA = 6'd3,
SLLV = 6'd4,
SRLV = 6'd6,
SRAV = 6'd7,
JR = 6'd8,
JALR = 6'd9,
MFLO = 6'd18,
MFHI = 6'd16,
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MTHI = 6'd17,
MTLO = 6'd19,
MULT = 6'd24,
MULTU = 6'd25,
DIV = 6'd26,
DIVU = 6'd27,
ADDU = 6'd33,
SUBU = 6'd35,
AND = 6'd36,
OR = 6'd37,
XOR = 6'd38,
SLT = 6'd42,
SLTU = 6'd43
} funct_enum;
funct_enum funct;
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typedef enum logic[4:0]{
BLTZ = 5'd0,
BGEZ = 5'd1,
BLTZAL = 5'd16,
BGEZAL = 5'd17
} rt_enum;
rt_enum rt;
always @(*) begin
assign op = Instr[31:26];
assign funct = Instr[5:0];
assign rt = Instr[20:16];
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//CtrlRegDst logic
if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==SLTI) || (op==SLTIU) || (op==XORI))begin
CtrlRegDst = 2'd0; //Write address comes from rt
end else if ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==JALR) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR)))begin
CtrlRegDst = 2'd1; //Write address comes from rd
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end else if ((op == JAL) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
CtrlRegDst = 2'd2; //const reg 31, for writing to the link register
end else begin CtrlRegDst = 1'bx; end//Not all instructions are encompassed so, added incase for debug purposes
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//CtrlPC logic
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if(ALUCond && ((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL)))))begin
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CtrlPC = 2'd1; // Branches - Jumps relative to PC
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end else if((op==J) || (op==JAL))begin
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CtrlPC = 2'd2; // Jumps within 256MB Region using 26-bit immediate in J type instruction
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end else if((op==SPECIAL)&&((funct==JR) || (funct==JALR)))begin
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CtrlPC = 2'd3; // Jumps using Register.
end else begin CtrlPC = 2'd0; end // No jumps or branches, just increment to next word
//CtrlMemRead and CtrlMemtoReg logic -- Interesting quirk that they have the same logic where both are concerned. Makes sense bc you'd only want to select the read data out when the memory itself is read enabled.
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if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR))begin
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CtrlMemRead = 1;//Memory is read enabled
CtrlMemtoReg = 3'd1;//write data port of regfile is fed from data memory
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end else if ((op==ADDIU) || (op==ANDI) || (op==ORI) || (op==LUI) || (op==SLTI) || (op==SLTIU) || (op==XORI) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))))begin
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CtrlMemRead = 0;//Memory is read disabled
CtrlMemtoReg = 3'd0;//write data port of regfile is fed from ALURes
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end else if ((op==JAL) || ((op==SPECIAL)&&(funct == JALR)) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))))begin
CtrlMemtoReg = 3'd2;//write data port of regfile is fed from PC + 8
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end else if ((op==SPECIAL)&&(funct == MFHI))begin
CtrlMemtoReg = 3'd3;//write data port of regfile is fed from ALUHi
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end else if ((op==SPECIAL)&&(funct == MFLO))begin
CtrlMemtoReg = 3'd4;//write data port of regfile is fed from ALULo
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end else if (((op==SPECIAL)&&(funct == JR)) || (op == BEQ) || (op==SW) ||((op==REGIMM)&&(rt==BGEZ)) || (op==BGTZ) || ((op==REGIMM)&&(rt==BLTZ)) || (op==BLEZ) || (op==BNE) || (op==J) || ((op==SPECIAL)&&(funct==MTHI)) || ((op==SPECIAL)&&(funct==MTLO)) || ((op==SPECIAL)&&(funct==MULT)) || ((op==SPECIAL)&&(funct==MULTU)) || ((op==SPECIAL)&&(funct==DIV)) || ((op==SPECIAL)&&(funct==DIVU)) || (op==SB) || (op==SH))begin
CtrlMemRead = 0;//Read disabled during jump
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end else begin CtrlMemRead = 1'bx;end//Not all instructions are encompassed so, added incase for debug purposes
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//CtrlALUOp Logic
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if((op==ADDIU) || ((op==SPECIAL)&&(funct==ADDU)))begin
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CtrlALUOp = 5'd0; //ADD from ALUOps
end else if((op==ANDI) || ((op==SPECIAL)&&(funct==AND)))begin
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CtrlALUOp = 5'd4;//AND from ALUOps
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end else if(op==BEQ) begin
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CtrlALUOp = 5'd13;//EQ from ALUOps
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end else if((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL)))begin
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CtrlALUOp = 5'd17;//GEQ from ALUOps
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end else if(op==BGTZ)begin
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CtrlALUOp = 5'd16;//GRT from ALUOps
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end else if(op==BLEZ)begin
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CtrlALUOp = 5'd15;//LEQ from ALUOps
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end else if((op==REGIMM)&&((rt==BLTZ) || (rt==BLTZAL)))begin
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CtrlALUOp = 5'd14;//LES from ALUOps
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end else if(op==BNE)begin
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CtrlALUOp = 5'd18;//NEQ from ALUOps
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end else if((op==SPECIAL)&&(funct==DIV))begin
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CtrlALUOp = 5'd3;//DIV from ALUOps
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end else if((op==SPECIAL)&&(funct==DIVU))begin
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CtrlALUOp = 5'd23;//DIVU from ALUOps
end else if((op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
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CtrlALUOp = 5'd0;//ADD from ALUOps
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end else if(op==LUI)begin
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CtrlALUOp = 5'd7;//SLL from ALUOps
end else if((op==SPECIAL)&&((funct==MTHI)))begin
CtrlALUOp = 5'd24;//MTHI from ALUOps
end else if((op==SPECIAL)&&((funct==MTLO)))begin
CtrlALUOp = 5'd25;//MTLO from ALUOps
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end else if((op==SPECIAL)&&(funct==MULT))begin
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CtrlALUOp = 5'd2;//MUL from ALUOps
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end else if((op==SPECIAL)&&(funct==MULTU))begin
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CtrlALUOp = 5'd22;//MULU from ALUOps
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end else if((op==ORI) || ((op==SPECIAL)&&(funct==OR)))begin
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CtrlALUOp = 5'd5;//OR from ALUOps
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end else if((op==SPECIAL)&&(funct==SLL))begin
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CtrlALUOp = 5'd7;//SLL from ALUOps
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end else if((op==SPECIAL)&&(funct==SLLV))begin
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CtrlALUOp = 5'd8;//SLLV from ALUOps
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end else if((op==SPECIAL)&&(funct==SRA))begin
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CtrlALUOp = 5'd11;//SRA from ALUOps
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end else if((op==SPECIAL)&&(funct==SRAV))begin
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CtrlALUOp = 5'd12;//SRAV from ALUOps
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end else if((op==SPECIAL)&&(funct==SRL))begin
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CtrlALUOp = 5'd9;//SRL from ALUOps
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end else if((op==SPECIAL)&&(funct==SRLV))begin
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CtrlALUOp = 5'd10;//SRLV from ALUOps
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end else if((op==SLTI) || ((op==SPECIAL)&&(funct==SLT)))begin
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CtrlALUOp = 5'd20;//SLT from ALUOps
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end else if((op==SLTIU) || ((op==SPECIAL)&&(funct==SLTU)))begin
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CtrlALUOp = 5'd21;//SLTU from ALUOps
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end else if((op==SPECIAL)&&(funct==SUBU))begin
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CtrlALUOp = 5'd1;//SUB from ALUOps
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end else if((op==XORI) || ((op==SPECIAL)&&(funct==XOR)))begin
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CtrlALUOp = 5'd6;//XOR from ALUOps
end else begin
CtrlALUOp = 5'bxxxxx;
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end
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//Ctrlshamt logic
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if((op==SPECIAL)&&((funct==SRA) || (funct==SRL) || (funct==SLL)))begin
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Ctrlshamt = Instr[10:6];// Shift amount piped in from the instruction
end else if(op == LUI)begin
Ctrlshamt = 5'd16;//Used specifically to implement LUI as the instruction itslef does not include shamt
end else begin Ctrlshamt = 5'bxxxxx;end
//CtrlMemWrite logic
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if((op==SB) || (op==SH) || (op==SW))begin
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CtrlMemWrite = 1;//Memory is write enabled
end else begin CtrlMemWrite = 0;end//default is 0 to ensure no accidental overwriting.
//CtrlSpcRegWriteEn logic
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if((op==SPECIAL)&&((funct==MTHI) || (funct==MTLO) || (funct==MULT) || (funct==MULTU) || (funct==DIV) || (funct==DIVU)))begin
CtrlSpcRegWriteEn = 1;//Special register Hi and Lo are write enabled
end else begin CtrlSpcRegWriteEn = 0;end//default is 0 to ensure no accidental overwriting.
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//CtrlALUSrc logic
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if((op==ADDIU) || (op==LUI) || (op==SLTI) || (op==SLTIU) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LW) || (op==LWL) || (op==LWR) || (op==SB) || (op==SH) || (op==SW))begin
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CtrlALUSrc = 1;//ALU Bus B is fed from the 16-bit immediate sign extended to 32-bit value taken from Instr[15-0]
end else if((op==BEQ) || (op==BGTZ) || (op==BLEZ) || (op==BNE) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==DIV) || (funct==DIVU) || (funct==MULT) || (funct==MULTU) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==XOR))) || ((op==REGIMM)&&((rt==BGEZ) || (rt==BGEZAL) || (rt==BLTZ) || (rt==BLTZAL))))begin
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CtrlALUSrc = 0;///ALU Bus B is fed from rt.
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end else if ((op==ORI) || (op==ANDI) || (op==XORI)) begin
CtrlALUSrc = 2;
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end else begin CtrlALUSrc = 1'bx;end
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//CtrlRegWrite logic
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if((op==ADDIU) || (op==ANDI) || (op==LB) || (op==LBU) || (op==LH) || (op==LHU) || (op==LUI) || (op==LW) || (op==LWL) || (op==LWR) || (op==ORI) || (op==JAL) || (op==SLTI) || (op==XORI) || ((op==REGIMM)&&((rt==BGEZAL) || (rt==BLTZAL))) || ((op==SPECIAL)&&((funct==ADDU) || (funct==AND) || (funct==MFLO) || (funct==MFHI) || (funct==OR) || (funct==SLL) || (funct==SLLV) || (funct==SLT) || (funct==SLTU) || (funct==SRA) || (funct==SRAV) || (funct==SRL) || (funct==SRLV) || (funct==SUBU) || (funct==JALR) || (funct==XOR)))) begin
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CtrlRegWrite = 1;//The Registers are Write Enabled
end else begin CtrlRegWrite = 0;end // The Registers are Write Disabled
end
endmodule