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83 lines
1.8 KiB
Verilog
83 lines
1.8 KiB
Verilog
module FpsMonitor(
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input clk50,
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input vs,
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// output frame pixel data
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output reg [7:0] fps,
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output wire [6:0] hex_fps_h,
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output wire [6:0] hex_fps_l
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);
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parameter ONE_SEC = 32'd50_000_000;
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reg [3:0] fps_h;
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reg [3:0] fps_l;
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reg [7:0] rfps;
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reg [3:0] rfps_l;
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reg [3:0] rfps_h;
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reg [26:0] sec_cnt;
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reg pre_vs;
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wire one_sec_mask;
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assign one_sec_mask = (sec_cnt>= (ONE_SEC - 1'b1) )?1'b1:1'b0;
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always @(posedge clk50)
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if(one_sec_mask) sec_cnt <= 27'h0;
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else sec_cnt <= sec_cnt + 1'b1;
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always @(posedge clk50) begin
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pre_vs <= vs;
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if(sec_cnt == 27'd0) begin
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rfps <= 8'd0;
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rfps_h <= 4'd0;
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rfps_l <= 4'd0;
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end
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else if({pre_vs,vs} == 2'b01) begin
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rfps <= rfps + 1'b1;
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if(rfps_l == 4'd9) begin
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rfps_l <= 4'd0;
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rfps_h <= rfps_h + 1'b1;
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end
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else rfps_l <= rfps_l + 1'b1;
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end
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end
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always @ (posedge clk50)
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if(one_sec_mask) begin
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fps <= rfps;
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fps_h <= rfps_h;
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fps_l <= rfps_l;
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end
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assign hex_fps_h = (fps_h == 4'd0)?7'h40: //0
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(fps_h == 4'd1)?7'h79: //1
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(fps_h == 4'd2)?7'h24: //2
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(fps_h == 4'd3)?7'h30: //3
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(fps_h == 4'd4)?7'h19: //4
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(fps_h == 4'd5)?7'h12: //5
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(fps_h == 4'd6)?7'h02: //6
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(fps_h == 4'd7)?7'h78: //7
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(fps_h == 4'd8)?7'h00: //8
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7'h10; //9
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assign hex_fps_l = (fps_l == 4'd0)?7'h40: //0
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(fps_l == 4'd1)?7'h79: //1
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(fps_l == 4'd2)?7'h24: //2
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(fps_l == 4'd3)?7'h30: //3
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(fps_l == 4'd4)?7'h19: //4
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(fps_l == 4'd5)?7'h12: //5
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(fps_l == 4'd6)?7'h02: //6
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(fps_l == 4'd7)?7'h78: //7
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(fps_l == 4'd8)?7'h00: //8
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7'h10; //9
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endmodule
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