mirror of
https://github.com/supleed2/ELEC50003-P1-CW.git
synced 2024-12-22 13:35:49 +00:00
Add Vision initial files from vision resource repo
This commit is contained in:
parent
e4b6e0dc0d
commit
dce62bdd77
11
Vision/.gitignore
vendored
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11
Vision/.gitignore
vendored
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*/db/*
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*/output_files/*
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*/incremental_db/*
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*~
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*.bak
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*/Qsys/synthesis/*
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*/Qsys/testbench/*
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*/simulation/*
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**/obj/*
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**/.metadata/*
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2167
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml
Normal file
2167
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml
Normal file
File diff suppressed because it is too large
Load diff
54
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv
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54
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv
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# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
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#
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preplace inst Qsys.nios2_gen2.clock_bridge -pg 1
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preplace inst Qsys.altpll_0 -pg 1 -lvl 3 -y 250
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preplace inst Qsys.i2c_opencores_camera -pg 1 -lvl 7 -y 30
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preplace inst Qsys.alt_vip_itc_0 -pg 1 -lvl 7 -y 810
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preplace inst Qsys.onchip_memory2_0 -pg 1 -lvl 7 -y 540
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preplace inst Qsys.led -pg 1 -lvl 7 -y 1390
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preplace inst Qsys.clk_50 -pg 1 -lvl 1 -y 720
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preplace inst Qsys.sysid_qsys -pg 1 -lvl 7 -y 1010
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preplace inst Qsys.sdram -pg 1 -lvl 7 -y 910
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preplace inst Qsys.nios2_gen2.reset_bridge -pg 1
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preplace inst Qsys.jtag_uart -pg 1 -lvl 7 -y 330
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preplace inst Qsys.TERASIC_CAMERA_0 -pg 1 -lvl 4 -y 740
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preplace inst Qsys.mipi_reset_n -pg 1 -lvl 7 -y 1190
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preplace inst Qsys.alt_vip_vfb_0 -pg 1 -lvl 5 -y 620
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preplace inst Qsys -pg 1 -lvl 1 -y 40 -regy -20
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preplace inst Qsys.timer -pg 1 -lvl 7 -y 440
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preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 7 -y 1090
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preplace inst Qsys.key -pg 1 -lvl 7 -y 620
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preplace inst Qsys.sw -pg 1 -lvl 7 -y 1290
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preplace inst Qsys.TERASIC_AUTO_FOCUS_0 -pg 1 -lvl 6 -y 560
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preplace inst Qsys.nios2_gen2.cpu -pg 1
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preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 470
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preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 7 -y 170
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preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)sdram.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)led.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)mipi_pwdn_n.reset,(MASTER)clk_50.clk_reset,(SLAVE)mipi_reset_n.reset,(SLAVE)sysid_qsys.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)sw.reset,(SLAVE)key.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)nios2_gen2.reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)jtag_uart.reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(SLAVE)timer.reset) 1 1 6 430 670 870 530 1170 730 1650 730 1890 800 2230
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preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)alt_vip_itc_0.din,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 2190
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)clk_50.clk_in_reset,(SLAVE)Qsys.reset) 1 0 1 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 7 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)sdram.wire,(SLAVE)Qsys.sdram_wire) 1 0 7 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)led.external_connection,(SLAVE)Qsys.led_external_connection) 1 0 7 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.clk_sdram,(MASTER)altpll_0.c1) 1 3 5 NJ 210 NJ 210 NJ 210 NJ 160 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.altpll_0_locked_conduit,(SLAVE)altpll_0.locked_conduit) 1 0 3 NJ 410 NJ 410 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit,(SLAVE)Qsys.terasic_auto_focus_0_conduit) 1 0 6 NJ 630 NJ 630 NJ 570 NJ 570 NJ 570 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)altpll_0.areset_conduit,(SLAVE)Qsys.altpll_0_areset_conduit) 1 0 3 NJ 260 NJ 260 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)mipi_reset_n.external_connection,(SLAVE)Qsys.mipi_reset_n_external_connection) 1 0 7 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.sw_external_connection,(SLAVE)sw.external_connection) 1 0 7 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.mipi_pwdn_n_external_connection,(SLAVE)mipi_pwdn_n.external_connection) 1 0 7 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.clk_vga,(MASTER)altpll_0.c3) 1 3 5 NJ 360 NJ 360 NJ 360 NJ 320 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)key.external_connection,(SLAVE)Qsys.key_external_connection) 1 0 7 NJ 650 NJ 650 NJ 650 NJ 650 NJ 750 NJ 750 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 7 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.alt_vip_itc_0_clocked_video,(SLAVE)alt_vip_itc_0.clocked_video) 1 0 7 NJ 830 NJ 830 NJ 830 NJ 830 NJ 820 NJ 820 NJ
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preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)sdram.clk,(SLAVE)alt_vip_itc_0.is_clk_rst,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)alt_vip_vfb_0.clock,(SLAVE)TERASIC_CAMERA_0.clock_reset,(MASTER)altpll_0.c2) 1 3 4 1190 340 1630 710 1870 780 2150
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preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)TERASIC_AUTO_FOCUS_0.din,(MASTER)alt_vip_vfb_0.dout) 1 5 1 1830
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)clk_50.clk_in,(SLAVE)Qsys.clk) 1 0 1 NJ
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preplace netloc FAN_IN<net_container>Qsys</net_container>(MASTER)alt_vip_vfb_0.read_master,(MASTER)alt_vip_vfb_0.write_master,(SLAVE)sdram.s1) 1 5 2 1830 960 NJ
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preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)jtag_uart.irq,(SLAVE)timer.irq,(MASTER)nios2_gen2.irq,(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)i2c_opencores_camera.interrupt_sender) 1 2 5 NJ 550 NJ 550 NJ 550 NJ 550 2170
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preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(MASTER)TERASIC_CAMERA_0.avalon_streaming_source,(SLAVE)alt_vip_vfb_0.din) 1 4 1 1610
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preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.d8m_xclkin,(MASTER)altpll_0.c4) 1 3 5 NJ 380 NJ 380 NJ 380 NJ 300 NJ
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preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_camera.clock,(SLAVE)led.clk,(SLAVE)onchip_memory2_0.clk1,(SLAVE)timer.clk,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)sw.clk,(SLAVE)sysid_qsys.clk,(SLAVE)mipi_pwdn_n.clk,(SLAVE)nios2_gen2.clk,(SLAVE)jtag_uart.clk,(MASTER)clk_50.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)key.clk) 1 1 6 410 430 850 400 NJ 400 NJ 400 NJ 400 2210
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preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)altpll_0.pll_slave,(SLAVE)led.s1,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)i2c_opencores_mipi.avalon_slave_0,(SLAVE)mipi_reset_n.s1,(MASTER)nios2_gen2.data_master,(SLAVE)sysid_qsys.control_slave,(SLAVE)timer.s1,(SLAVE)sw.s1,(SLAVE)onchip_memory2_0.s1,(SLAVE)key.s1,(SLAVE)mipi_pwdn_n.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(MASTER)nios2_gen2.instruction_master,(SLAVE)nios2_gen2.debug_mem_slave) 1 1 6 450 610 890 510 NJ 510 NJ 510 1850 690 2130
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preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.terasic_camera_0_conduit_end,(SLAVE)TERASIC_CAMERA_0.conduit_end) 1 0 4 NJ 790 NJ 790 NJ 790 NJ
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levelinfo -pg 1 0 200 2570
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levelinfo -hier Qsys 210 240 590 980 1300 1680 1980 2320 2470
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2
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/filters.xml
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2
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/filters.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<filters version="16.1" />
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14
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml
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14
Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<preferences>
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<debug showDebugMenu="0" />
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<systemtable filter="All Interfaces">
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<columns>
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<connections preferredWidth="319" />
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<irq preferredWidth="34" />
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<name preferredWidth="201" />
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<export preferredWidth="267" />
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</columns>
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</systemtable>
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<library expandedCategories="Project,Library" />
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<window width="1971" height="1159" x="8" y="31" />
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</preferences>
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13
Vision/DE10_LITE_D8M_VIP_16/Chain.cdf
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13
Vision/DE10_LITE_D8M_VIP_16/Chain.cdf
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/* Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition */
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JedecChain;
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FileRevision(JESD32A);
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DefaultMfr(6E);
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P ActionCode(Cfg)
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Device PartName(10M50DAF484) Path("F:/Ed/Stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/output_files/") File("DE10_LITE_D8M_VIP_time_limited.sof") MfrSpec(OpMask(1));
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ChainEnd;
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AlteraBegin;
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ChainType(JTAG);
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AlteraEnd;
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128
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.SDC
Normal file
128
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.SDC
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#**************************************************************
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# This .sdc file is created by Terasic Tool.
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# Users are recommended to modify this file to match users logic.
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#**************************************************************
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
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create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
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create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
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#SDRAM CLK
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create_generated_clock -source [get_pins { u0|altpll_0|sd1|pll7|clk[1] }] \
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-name clk_dram_ext [get_ports {DRAM_CLK}]
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#VGA CLK
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#create_generated_clock -source [get_pins { u0|pll_sys|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk }] \
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-name clk_vga_ext [get_ports {VGA_CLK}] -invert
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#D8M
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create_clock -period "25.0 MHz" -name MIPI_PIXEL_CLK [get_ports MIPI_PIXEL_CLK]
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create_clock -period "25.0 MHz" -name MIPI_PIXEL_CLK_ext
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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# tpd min 1ns ,max 6ns
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set_input_delay -max 6.0 -clock MIPI_PIXEL_CLK_ext [get_ports {MIPI_PIXEL_VS MIPI_PIXEL_HS MIPI_PIXEL_D[*]}]
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set_input_delay -min 1.0 -clock MIPI_PIXEL_CLK_ext [get_ports {MIPI_PIXEL_VS MIPI_PIXEL_HS MIPI_PIXEL_D[*]}]
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# SDRAM
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# max 5.4(max) +0.4(trace delay) +0.1 = 5.9
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# min 2.7(min) +0.4(trace delay) -0.1 = 3.0
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set_input_delay -max -clock clk_dram_ext 5.9 [get_ports DRAM_DQ*]
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set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*]
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#shift-window
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set_multicycle_path -from [get_clocks {clk_dram_ext}] \
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-to [get_clocks { u0|altpll_0|sd1|pll7|clk[2] }] \
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-setup 2
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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# suppose +- 100 ps skew
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# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)
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# min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
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#SDRAM
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# max 1.5+0.1 = 1.6
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# min -0.8-0.1 = -0.9
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set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_DQ* DRAM_*DQM}]
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set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_DQ* DRAM_*DQM}]
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set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]
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set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]
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#VGA
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# max 0.2+0.1 = 0.3
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# min -1.5-0.1 = -1.6
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set_output_delay -max -clock clk_vga_ext 0.3 [get_ports {VGA_R* VGA_G* VGA_B* VGA_HS VGA_VS}]
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set_output_delay -min -clock clk_vga_ext -1.6 [get_ports {VGA_R* VGA_G* VGA_B* VGA_HS VGA_VS}]
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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set_clock_groups -asynchronous -group [get_clocks { u0|altpll_0|sd1|pll7|clk[2] }] \
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-group [get_clocks {MIPI_PIXEL_CLK}]
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#**************************************************************
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# Set False Path
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#**************************************************************
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set_false_path -from [get_ports {KEY* SW*}] -to *
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set_false_path -from * -to [get_ports {LED* HEX*}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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#**************************************************************
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# Set Load
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#**************************************************************
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1193
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.htm
Normal file
1193
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.htm
Normal file
File diff suppressed because it is too large
Load diff
6
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qpf
Normal file
6
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qpf
Normal file
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DATE = "15:21:37 August 23, 2016"
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QUARTUS_VERSION = "15.1.0"
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# Revisions
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PROJECT_REVISION = "DE10_LITE_D8M_VIP"
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426
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qsf
Normal file
426
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qsf
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#============================================================
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# Build by Terasic System Builder
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#============================================================
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set_global_assignment -name FAMILY "MAX 10"
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set_global_assignment -name DEVICE 10M50DAF484C7G
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set_global_assignment -name TOP_LEVEL_ENTITY DE10_LITE_D8M_VIP
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
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set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:21:37 AUGUST 23,2016"
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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#set_global_assignment -name ENABLE_ERAM_PRELOAD ON
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#============================================================
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# CLOCK
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#============================================================
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
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set_location_assignment PIN_N5 -to ADC_CLK_10
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set_location_assignment PIN_P11 -to MAX10_CLK1_50
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set_location_assignment PIN_N14 -to MAX10_CLK2_50
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#============================================================
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# SDRAM
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
|
||||
set_location_assignment PIN_U17 -to DRAM_ADDR[0]
|
||||
set_location_assignment PIN_W19 -to DRAM_ADDR[1]
|
||||
set_location_assignment PIN_V18 -to DRAM_ADDR[2]
|
||||
set_location_assignment PIN_U18 -to DRAM_ADDR[3]
|
||||
set_location_assignment PIN_U19 -to DRAM_ADDR[4]
|
||||
set_location_assignment PIN_T18 -to DRAM_ADDR[5]
|
||||
set_location_assignment PIN_T19 -to DRAM_ADDR[6]
|
||||
set_location_assignment PIN_R18 -to DRAM_ADDR[7]
|
||||
set_location_assignment PIN_P18 -to DRAM_ADDR[8]
|
||||
set_location_assignment PIN_P19 -to DRAM_ADDR[9]
|
||||
set_location_assignment PIN_T20 -to DRAM_ADDR[10]
|
||||
set_location_assignment PIN_P20 -to DRAM_ADDR[11]
|
||||
set_location_assignment PIN_R20 -to DRAM_ADDR[12]
|
||||
set_location_assignment PIN_T21 -to DRAM_BA[0]
|
||||
set_location_assignment PIN_T22 -to DRAM_BA[1]
|
||||
set_location_assignment PIN_U21 -to DRAM_CAS_N
|
||||
set_location_assignment PIN_N22 -to DRAM_CKE
|
||||
set_location_assignment PIN_L14 -to DRAM_CLK
|
||||
set_location_assignment PIN_U20 -to DRAM_CS_N
|
||||
set_location_assignment PIN_Y21 -to DRAM_DQ[0]
|
||||
set_location_assignment PIN_Y20 -to DRAM_DQ[1]
|
||||
set_location_assignment PIN_AA22 -to DRAM_DQ[2]
|
||||
set_location_assignment PIN_AA21 -to DRAM_DQ[3]
|
||||
set_location_assignment PIN_Y22 -to DRAM_DQ[4]
|
||||
set_location_assignment PIN_W22 -to DRAM_DQ[5]
|
||||
set_location_assignment PIN_W20 -to DRAM_DQ[6]
|
||||
set_location_assignment PIN_V21 -to DRAM_DQ[7]
|
||||
set_location_assignment PIN_P21 -to DRAM_DQ[8]
|
||||
set_location_assignment PIN_J22 -to DRAM_DQ[9]
|
||||
set_location_assignment PIN_H21 -to DRAM_DQ[10]
|
||||
set_location_assignment PIN_H22 -to DRAM_DQ[11]
|
||||
set_location_assignment PIN_G22 -to DRAM_DQ[12]
|
||||
set_location_assignment PIN_G20 -to DRAM_DQ[13]
|
||||
set_location_assignment PIN_G19 -to DRAM_DQ[14]
|
||||
set_location_assignment PIN_F22 -to DRAM_DQ[15]
|
||||
set_location_assignment PIN_V22 -to DRAM_LDQM
|
||||
set_location_assignment PIN_U22 -to DRAM_RAS_N
|
||||
set_location_assignment PIN_J21 -to DRAM_UDQM
|
||||
set_location_assignment PIN_V20 -to DRAM_WE_N
|
||||
|
||||
#============================================================
|
||||
# SEG7
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
|
||||
set_location_assignment PIN_C14 -to HEX0[0]
|
||||
set_location_assignment PIN_E15 -to HEX0[1]
|
||||
set_location_assignment PIN_C15 -to HEX0[2]
|
||||
set_location_assignment PIN_C16 -to HEX0[3]
|
||||
set_location_assignment PIN_E16 -to HEX0[4]
|
||||
set_location_assignment PIN_D17 -to HEX0[5]
|
||||
set_location_assignment PIN_C17 -to HEX0[6]
|
||||
set_location_assignment PIN_D15 -to HEX0[7]
|
||||
set_location_assignment PIN_C18 -to HEX1[0]
|
||||
set_location_assignment PIN_D18 -to HEX1[1]
|
||||
set_location_assignment PIN_E18 -to HEX1[2]
|
||||
set_location_assignment PIN_B16 -to HEX1[3]
|
||||
set_location_assignment PIN_A17 -to HEX1[4]
|
||||
set_location_assignment PIN_A18 -to HEX1[5]
|
||||
set_location_assignment PIN_B17 -to HEX1[6]
|
||||
set_location_assignment PIN_A16 -to HEX1[7]
|
||||
set_location_assignment PIN_B20 -to HEX2[0]
|
||||
set_location_assignment PIN_A20 -to HEX2[1]
|
||||
set_location_assignment PIN_B19 -to HEX2[2]
|
||||
set_location_assignment PIN_A21 -to HEX2[3]
|
||||
set_location_assignment PIN_B21 -to HEX2[4]
|
||||
set_location_assignment PIN_C22 -to HEX2[5]
|
||||
set_location_assignment PIN_B22 -to HEX2[6]
|
||||
set_location_assignment PIN_A19 -to HEX2[7]
|
||||
set_location_assignment PIN_F21 -to HEX3[0]
|
||||
set_location_assignment PIN_E22 -to HEX3[1]
|
||||
set_location_assignment PIN_E21 -to HEX3[2]
|
||||
set_location_assignment PIN_C19 -to HEX3[3]
|
||||
set_location_assignment PIN_C20 -to HEX3[4]
|
||||
set_location_assignment PIN_D19 -to HEX3[5]
|
||||
set_location_assignment PIN_E17 -to HEX3[6]
|
||||
set_location_assignment PIN_D22 -to HEX3[7]
|
||||
set_location_assignment PIN_F18 -to HEX4[0]
|
||||
set_location_assignment PIN_E20 -to HEX4[1]
|
||||
set_location_assignment PIN_E19 -to HEX4[2]
|
||||
set_location_assignment PIN_J18 -to HEX4[3]
|
||||
set_location_assignment PIN_H19 -to HEX4[4]
|
||||
set_location_assignment PIN_F19 -to HEX4[5]
|
||||
set_location_assignment PIN_F20 -to HEX4[6]
|
||||
set_location_assignment PIN_F17 -to HEX4[7]
|
||||
set_location_assignment PIN_J20 -to HEX5[0]
|
||||
set_location_assignment PIN_K20 -to HEX5[1]
|
||||
set_location_assignment PIN_L18 -to HEX5[2]
|
||||
set_location_assignment PIN_N18 -to HEX5[3]
|
||||
set_location_assignment PIN_M20 -to HEX5[4]
|
||||
set_location_assignment PIN_N19 -to HEX5[5]
|
||||
set_location_assignment PIN_N20 -to HEX5[6]
|
||||
set_location_assignment PIN_L19 -to HEX5[7]
|
||||
|
||||
#============================================================
|
||||
# KEY
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
|
||||
set_location_assignment PIN_B8 -to KEY[0]
|
||||
set_location_assignment PIN_A7 -to KEY[1]
|
||||
|
||||
#============================================================
|
||||
# LED
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
|
||||
set_location_assignment PIN_A8 -to LEDR[0]
|
||||
set_location_assignment PIN_A9 -to LEDR[1]
|
||||
set_location_assignment PIN_A10 -to LEDR[2]
|
||||
set_location_assignment PIN_B10 -to LEDR[3]
|
||||
set_location_assignment PIN_D13 -to LEDR[4]
|
||||
set_location_assignment PIN_C13 -to LEDR[5]
|
||||
set_location_assignment PIN_E14 -to LEDR[6]
|
||||
set_location_assignment PIN_D14 -to LEDR[7]
|
||||
set_location_assignment PIN_A11 -to LEDR[8]
|
||||
set_location_assignment PIN_B11 -to LEDR[9]
|
||||
|
||||
#============================================================
|
||||
# SW
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
|
||||
set_location_assignment PIN_C10 -to SW[0]
|
||||
set_location_assignment PIN_C11 -to SW[1]
|
||||
set_location_assignment PIN_D12 -to SW[2]
|
||||
set_location_assignment PIN_C12 -to SW[3]
|
||||
set_location_assignment PIN_A12 -to SW[4]
|
||||
set_location_assignment PIN_B12 -to SW[5]
|
||||
set_location_assignment PIN_A13 -to SW[6]
|
||||
set_location_assignment PIN_A14 -to SW[7]
|
||||
set_location_assignment PIN_B14 -to SW[8]
|
||||
set_location_assignment PIN_F15 -to SW[9]
|
||||
|
||||
#============================================================
|
||||
# VGA
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
|
||||
set_location_assignment PIN_P1 -to VGA_B[0]
|
||||
set_location_assignment PIN_T1 -to VGA_B[1]
|
||||
set_location_assignment PIN_P4 -to VGA_B[2]
|
||||
set_location_assignment PIN_N2 -to VGA_B[3]
|
||||
set_location_assignment PIN_W1 -to VGA_G[0]
|
||||
set_location_assignment PIN_T2 -to VGA_G[1]
|
||||
set_location_assignment PIN_R2 -to VGA_G[2]
|
||||
set_location_assignment PIN_R1 -to VGA_G[3]
|
||||
set_location_assignment PIN_N3 -to VGA_HS
|
||||
set_location_assignment PIN_AA1 -to VGA_R[0]
|
||||
set_location_assignment PIN_V1 -to VGA_R[1]
|
||||
set_location_assignment PIN_Y2 -to VGA_R[2]
|
||||
set_location_assignment PIN_Y1 -to VGA_R[3]
|
||||
set_location_assignment PIN_N1 -to VGA_VS
|
||||
|
||||
#============================================================
|
||||
# Accelerometer
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO
|
||||
set_location_assignment PIN_AB16 -to GSENSOR_CS_N
|
||||
set_location_assignment PIN_Y14 -to GSENSOR_INT[1]
|
||||
set_location_assignment PIN_Y13 -to GSENSOR_INT[2]
|
||||
set_location_assignment PIN_AB15 -to GSENSOR_SCLK
|
||||
set_location_assignment PIN_V11 -to GSENSOR_SDI
|
||||
set_location_assignment PIN_V12 -to GSENSOR_SDO
|
||||
|
||||
#============================================================
|
||||
# Arduino
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
|
||||
set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
|
||||
set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
|
||||
set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
|
||||
set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
|
||||
set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
|
||||
set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
|
||||
set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
|
||||
set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
|
||||
set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
|
||||
set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
|
||||
set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
|
||||
set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
|
||||
set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
|
||||
set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
|
||||
set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
|
||||
set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
|
||||
set_location_assignment PIN_F16 -to ARDUINO_RESET_N
|
||||
|
||||
#============================================================
|
||||
# GPIO, GPIO connect to D8M-GPIO
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAMERA_I2C_SCL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAMERA_I2C_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAMERA_PWDN_n
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_CS_n
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_I2C_SCL
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_I2C_SDA
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_MCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_CLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_HS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_VS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_REFCLK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_RESET_n
|
||||
set_location_assignment PIN_AA7 -to CAMERA_I2C_SCL
|
||||
set_location_assignment PIN_Y6 -to CAMERA_I2C_SDA
|
||||
set_location_assignment PIN_Y7 -to CAMERA_PWDN_n
|
||||
set_location_assignment PIN_Y8 -to MIPI_CS_n
|
||||
set_location_assignment PIN_AA5 -to MIPI_I2C_SCL
|
||||
set_location_assignment PIN_Y4 -to MIPI_I2C_SDA
|
||||
set_location_assignment PIN_AA6 -to MIPI_MCLK
|
||||
set_location_assignment PIN_W10 -to MIPI_PIXEL_CLK
|
||||
set_location_assignment PIN_W9 -to MIPI_PIXEL_D[0]
|
||||
set_location_assignment PIN_V8 -to MIPI_PIXEL_D[1]
|
||||
set_location_assignment PIN_W8 -to MIPI_PIXEL_D[2]
|
||||
set_location_assignment PIN_V7 -to MIPI_PIXEL_D[3]
|
||||
set_location_assignment PIN_W7 -to MIPI_PIXEL_D[4]
|
||||
set_location_assignment PIN_W6 -to MIPI_PIXEL_D[5]
|
||||
set_location_assignment PIN_V5 -to MIPI_PIXEL_D[6]
|
||||
set_location_assignment PIN_W5 -to MIPI_PIXEL_D[7]
|
||||
set_location_assignment PIN_AA15 -to MIPI_PIXEL_D[8]
|
||||
set_location_assignment PIN_AA14 -to MIPI_PIXEL_D[9]
|
||||
set_location_assignment PIN_AA9 -to MIPI_PIXEL_HS
|
||||
set_location_assignment PIN_AB10 -to MIPI_PIXEL_VS
|
||||
set_location_assignment PIN_AB11 -to MIPI_REFCLK
|
||||
set_location_assignment PIN_AA8 -to MIPI_RESET_n
|
||||
|
||||
#============================================================
|
||||
# End of pin assignments by Terasic System Builder
|
||||
#============================================================
|
||||
|
||||
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
set_global_assignment -name OPTIMIZATION_MODE BALANCED
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name VERILOG_FILE FpsMonitor.v
|
||||
set_global_assignment -name QSYS_FILE Qsys.qsys
|
||||
set_global_assignment -name SDC_FILE DE10_LITE_D8M_VIP.SDC
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name VERILOG_FILE ip/EEE_IMGPROC/STREAM_REG.v
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE ip/EEE_IMGPROC/STREAM_REG_TEST.vwf
|
||||
set_global_assignment -name VERILOG_FILE DE10_LITE_D8M_VIP.v
|
||||
set_global_assignment -name VERILOG_FILE ip/EEE_IMGPROC/STREAM_REG_TEST.v
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name QIP_FILE ip/EEE_IMGPROC/MSG_FIFO.qip
|
||||
set_global_assignment -name VERILOG_FILE ip/EEE_IMGPROC/EEE_IMGPROC.v
|
||||
set_global_assignment -name CDF_FILE Chain.cdf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
BIN
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws
Normal file
BIN
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws
Normal file
Binary file not shown.
196
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v
Normal file
196
Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
|
||||
//=======================================================
|
||||
// This code is generated by Terasic System Builder
|
||||
//=======================================================
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module DE10_LITE_D8M_VIP(
|
||||
|
||||
//////////// CLOCK //////////
|
||||
input ADC_CLK_10,
|
||||
input MAX10_CLK1_50,
|
||||
input MAX10_CLK2_50,
|
||||
|
||||
//////////// SDRAM //////////
|
||||
output [12:0] DRAM_ADDR,
|
||||
output [1:0] DRAM_BA,
|
||||
output DRAM_CAS_N,
|
||||
output DRAM_CKE,
|
||||
output DRAM_CLK,
|
||||
output DRAM_CS_N,
|
||||
inout [15:0] DRAM_DQ,
|
||||
output DRAM_LDQM,
|
||||
output DRAM_RAS_N,
|
||||
output DRAM_UDQM,
|
||||
output DRAM_WE_N,
|
||||
|
||||
//////////// SEG7 //////////
|
||||
output [7:0] HEX0,
|
||||
output [7:0] HEX1,
|
||||
output [7:0] HEX2,
|
||||
output [7:0] HEX3,
|
||||
output [7:0] HEX4,
|
||||
output [7:0] HEX5,
|
||||
|
||||
//////////// KEY //////////
|
||||
input [1:0] KEY,
|
||||
|
||||
//////////// LED //////////
|
||||
output [9:0] LEDR,
|
||||
|
||||
//////////// SW //////////
|
||||
input [9:0] SW,
|
||||
|
||||
//////////// VGA //////////
|
||||
output [3:0] VGA_B,
|
||||
output [3:0] VGA_G,
|
||||
output VGA_HS,
|
||||
output [3:0] VGA_R,
|
||||
output VGA_VS,
|
||||
|
||||
//////////// Accelerometer //////////
|
||||
output GSENSOR_CS_N,
|
||||
input [2:1] GSENSOR_INT,
|
||||
output GSENSOR_SCLK,
|
||||
inout GSENSOR_SDI,
|
||||
inout GSENSOR_SDO,
|
||||
|
||||
//////////// Arduino //////////
|
||||
inout [15:0] ARDUINO_IO,
|
||||
inout ARDUINO_RESET_N,
|
||||
|
||||
//////////// GPIO, GPIO connect to D8M-GPIO //////////
|
||||
inout CAMERA_I2C_SCL,
|
||||
inout CAMERA_I2C_SDA,
|
||||
output CAMERA_PWDN_n,
|
||||
output MIPI_CS_n,
|
||||
inout MIPI_I2C_SCL,
|
||||
inout MIPI_I2C_SDA,
|
||||
output MIPI_MCLK,
|
||||
input MIPI_PIXEL_CLK,
|
||||
input [9:0] MIPI_PIXEL_D,
|
||||
input MIPI_PIXEL_HS,
|
||||
input MIPI_PIXEL_VS,
|
||||
output MIPI_REFCLK,
|
||||
output MIPI_RESET_n
|
||||
);
|
||||
|
||||
|
||||
|
||||
//=======================================================
|
||||
// REG/WIRE declarations
|
||||
//=======================================================
|
||||
wire disp_clk;
|
||||
wire disp_hs;
|
||||
wire disp_vs;
|
||||
wire [23:0] disp_data;
|
||||
wire [7 :0] mVGA_R;
|
||||
wire [7 :0] mVGA_G;
|
||||
wire [7 :0] mVGA_B;
|
||||
|
||||
|
||||
|
||||
//=======================================================
|
||||
// Structural coding
|
||||
//=======================================================
|
||||
assign VGA_HS = disp_hs;
|
||||
assign VGA_VS = disp_vs;
|
||||
assign {mVGA_R, mVGA_G, mVGA_B} = disp_data;
|
||||
|
||||
assign VGA_R = mVGA_R[7:4];
|
||||
assign VGA_G = mVGA_G[7:4];
|
||||
assign VGA_B = mVGA_B[7:4];
|
||||
|
||||
assign MIPI_CS_n = 1'b0;
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////
|
||||
wire MIPI_PIXEL_CLK_d;
|
||||
reg MIPI_PIXEL_VS_d;
|
||||
reg MIPI_PIXEL_HS_d;
|
||||
reg [9:0] MIPI_PIXEL_D_d;
|
||||
|
||||
assign MIPI_PIXEL_CLK_d = ~MIPI_PIXEL_CLK;
|
||||
|
||||
always @ (posedge MIPI_PIXEL_CLK_d) begin
|
||||
MIPI_PIXEL_VS_d <= MIPI_PIXEL_VS;
|
||||
MIPI_PIXEL_HS_d <= MIPI_PIXEL_HS;
|
||||
MIPI_PIXEL_D_d <= MIPI_PIXEL_D;
|
||||
end
|
||||
|
||||
|
||||
|
||||
Qsys u0 (
|
||||
.clk_clk (MAX10_CLK1_50), // clk.clk
|
||||
.reset_reset_n (1'b1), // reset.reset_n
|
||||
|
||||
.clk_sdram_clk (DRAM_CLK), // clk_sdram.clk
|
||||
.clk_vga_clk (disp_clk), // clk_vga.clk
|
||||
.d8m_xclkin_clk (MIPI_REFCLK), // d8m_xclkin.clk
|
||||
|
||||
.key_external_connection_export (KEY), // key_external_connection.export
|
||||
.led_external_connection_export (), // led_external_connection.export
|
||||
.sw_external_connection_export (SW), // sw_external_connection.export
|
||||
|
||||
.i2c_opencores_camera_export_scl_pad_io (CAMERA_I2C_SCL), // i2c_opencores_camera_export.scl_pad_io
|
||||
.i2c_opencores_camera_export_sda_pad_io (CAMERA_I2C_SDA), // .sda_pad_io
|
||||
|
||||
.i2c_opencores_mipi_export_scl_pad_io (MIPI_I2C_SCL), // i2c_opencores_mipi_export.scl_pad_io
|
||||
.i2c_opencores_mipi_export_sda_pad_io (MIPI_I2C_SDA), // .sda_pad_io
|
||||
|
||||
.mipi_pwdn_n_external_connection_export (CAMERA_PWDN_n), // mipi_pwdn_n_external_connection.export
|
||||
.mipi_reset_n_external_connection_export (MIPI_RESET_n), // mipi_reset_n_external_connection.export
|
||||
|
||||
.sdram_wire_addr (DRAM_ADDR), // sdram_wire.addr
|
||||
.sdram_wire_ba (DRAM_BA), // .ba
|
||||
.sdram_wire_cas_n (DRAM_CAS_N), // .cas_n
|
||||
.sdram_wire_cke (DRAM_CKE), // .cke
|
||||
.sdram_wire_cs_n (DRAM_CS_N), // .cs_n
|
||||
.sdram_wire_dq (DRAM_DQ), // .dq
|
||||
.sdram_wire_dqm ({DRAM_UDQM, DRAM_LDQM}), // .dqm
|
||||
.sdram_wire_ras_n (DRAM_RAS_N), // .ras_n
|
||||
.sdram_wire_we_n (DRAM_WE_N), // .we_n
|
||||
|
||||
.terasic_camera_0_conduit_end_D ({MIPI_PIXEL_D_d[9:0], 2'b00}),// terasic_camera_0_conduit_end.D
|
||||
.terasic_camera_0_conduit_end_FVAL (MIPI_PIXEL_VS_d), // .FVAL
|
||||
.terasic_camera_0_conduit_end_LVAL (MIPI_PIXEL_HS_d), // .LVAL
|
||||
.terasic_camera_0_conduit_end_PIXCLK (~MIPI_PIXEL_CLK_d), // .PIXCLK
|
||||
|
||||
.terasic_auto_focus_0_conduit_vcm_i2c_sda (CAMERA_I2C_SDA), // terasic_auto_focus_0_conduit.vcm_i2c_sda
|
||||
.terasic_auto_focus_0_conduit_clk50 (MAX10_CLK1_50), // .clk50
|
||||
.terasic_auto_focus_0_conduit_vcm_i2c_scl (CAMERA_I2C_SCL), // .vcm_i2c_scl
|
||||
|
||||
.alt_vip_itc_0_clocked_video_vid_clk (disp_clk), // alt_vip_itc_0_clocked_video.vid_clk
|
||||
.alt_vip_itc_0_clocked_video_vid_data (disp_data), // .vid_data
|
||||
.alt_vip_itc_0_clocked_video_underflow (), // .underflow
|
||||
.alt_vip_itc_0_clocked_video_vid_datavalid (), // .vid_datavalid
|
||||
.alt_vip_itc_0_clocked_video_vid_v_sync (disp_vs), // .vid_v_sync
|
||||
.alt_vip_itc_0_clocked_video_vid_h_sync (disp_hs), // .vid_h_sync
|
||||
.alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
|
||||
.alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
|
||||
.alt_vip_itc_0_clocked_video_vid_v (), // .vid_v
|
||||
|
||||
.altpll_0_areset_conduit_export (), // altpll_0_areset_conduit.export
|
||||
.altpll_0_locked_conduit_export (), // altpll_0_locked_conduit.export
|
||||
.altpll_0_phasedone_conduit_export (), // altpll_0_phasedone_conduit.export
|
||||
|
||||
.eee_imgproc_0_conduit_mode_new_signal (SW[0])
|
||||
);
|
||||
|
||||
FpsMonitor uFps(
|
||||
.clk50(MAX10_CLK2_50),
|
||||
.vs(MIPI_PIXEL_VS),
|
||||
|
||||
.fps(),
|
||||
.hex_fps_h(HEX1),
|
||||
.hex_fps_l(HEX0)
|
||||
);
|
||||
|
||||
assign HEX2 = 7'h7F;
|
||||
assign HEX3 = 7'h7F;
|
||||
assign HEX4 = 7'h7F;
|
||||
assign HEX5 = 7'h7F;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,808 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2020 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
|
||||
# Date created = 13:06:40 March 09, 2021
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Note:
|
||||
#
|
||||
# 1) Do not modify this file. This file was generated
|
||||
# automatically by the Quartus Prime software and is used
|
||||
# to preserve global assignments across Quartus Prime versions.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
|
||||
set_global_assignment -name IP_COMPONENT_INTERNAL Off
|
||||
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
||||
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
||||
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
|
||||
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
||||
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
||||
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
||||
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
||||
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
||||
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
||||
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
||||
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
||||
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
||||
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
|
||||
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
|
||||
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
||||
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
||||
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
||||
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
||||
set_global_assignment -name DO_COMBINED_ANALYSIS Off
|
||||
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
|
||||
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
|
||||
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
|
||||
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
|
||||
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZATION_MODE Balanced
|
||||
set_global_assignment -name ALLOW_REGISTER_MERGING On
|
||||
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
|
||||
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
|
||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||
set_global_assignment -name ENABLE_IP_DEBUG Off
|
||||
set_global_assignment -name SAVE_DISK_SPACE On
|
||||
set_global_assignment -name OCP_HW_EVAL -value OFF
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||
set_global_assignment -name FAMILY "Cyclone V"
|
||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||
set_global_assignment -name SAFE_STATE_MACHINE Off
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
||||
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||
set_global_assignment -name AUTO_CARRY_CHAINS On
|
||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
|
||||
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
|
||||
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name PRPOF_ID Off
|
||||
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
|
||||
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||
set_global_assignment -name ADCE_ENABLED Auto
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS Off
|
||||
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
||||
set_global_assignment -name DEVICE AUTO
|
||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
|
||||
set_global_assignment -name CVP_MODE Off
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
|
||||
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
|
||||
set_global_assignment -name USE_CONF_DONE AUTO
|
||||
set_global_assignment -name USE_PWRMGT_SCL AUTO
|
||||
set_global_assignment -name USE_PWRMGT_SDA AUTO
|
||||
set_global_assignment -name USE_PWRMGT_ALERT AUTO
|
||||
set_global_assignment -name USE_INIT_DONE AUTO
|
||||
set_global_assignment -name USE_CVP_CONFDONE AUTO
|
||||
set_global_assignment -name USE_SEU_ERROR AUTO
|
||||
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
|
||||
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
|
||||
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
|
||||
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
|
||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||
set_global_assignment -name ENABLE_NCE_PIN Off
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
|
||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
|
||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_SSN Off
|
||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
||||
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
|
||||
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
|
||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||
set_global_assignment -name PCI_IO Off
|
||||
set_global_assignment -name TURBO_BIT On
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
|
||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
|
||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
|
||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||
set_global_assignment -name ENABLE_PR_PINS Off
|
||||
set_global_assignment -name RESERVE_PR_PINS Off
|
||||
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
|
||||
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||
set_global_assignment -name CLAMPING_DIODE Off
|
||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
|
||||
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
|
||||
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
|
||||
set_global_assignment -name SEU_FIT_REPORT Off
|
||||
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
|
||||
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||
set_global_assignment -name COMPRESSION_MODE Off
|
||||
set_global_assignment -name CLOCK_SOURCE Internal
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||
set_global_assignment -name SECURITY_BIT Off
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
|
||||
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
|
||||
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
|
||||
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
|
||||
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
|
||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
|
||||
set_global_assignment -name POR_SCHEME "Instant ON"
|
||||
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
|
||||
set_global_assignment -name POF_VERIFY_PROTECT Off
|
||||
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
|
||||
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
|
||||
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
|
||||
set_global_assignment -name GENERATE_PMSF_FILES On
|
||||
set_global_assignment -name START_TIME 0ns
|
||||
set_global_assignment -name SIMULATION_MODE TIMING
|
||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||
set_global_assignment -name CHECK_OUTPUTS Off
|
||||
set_global_assignment -name SIMULATION_COVERAGE On
|
||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name GLITCH_DETECTION Off
|
||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
||||
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
||||
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
||||
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||
set_global_assignment -name MERGE_HEX_FILE Off
|
||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
|
||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_USE_PVA On
|
||||
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
||||
set_global_assignment -name POWER_TJ_VALUE 25
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 25
|
||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
|
||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
||||
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_BBOX_MERGE On
|
||||
set_global_assignment -name EQC_LVDS_MERGE On
|
||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||
set_global_assignment -name EQC_RENAMING_RULES On
|
||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
|
||||
183
Vision/DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl
Normal file
183
Vision/DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl
Normal file
|
|
@ -0,0 +1,183 @@
|
|||
# TCL File Generated by Component Editor 16.0
|
||||
# Fri Apr 23 12:07:51 BST 2021
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
#
|
||||
# EEE_IMGPROC "EEE_IMGPROC" v1.0
|
||||
# 2021.04.23.12:07:51
|
||||
#
|
||||
#
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 16.0
|
||||
#
|
||||
package require -exact qsys 16.0
|
||||
|
||||
|
||||
#
|
||||
# module EEE_IMGPROC
|
||||
#
|
||||
set_module_property DESCRIPTION ""
|
||||
set_module_property NAME EEE_IMGPROC
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property AUTHOR ""
|
||||
set_module_property DISPLAY_NAME EEE_IMGPROC
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL EEE_IMGPROC
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file EEE_IMGPROC.v VERILOG PATH ip/EEE_IMGPROC/EEE_IMGPROC.v TOP_LEVEL_FILE
|
||||
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point clock
|
||||
#
|
||||
add_interface clock clock end
|
||||
set_interface_property clock clockRate 0
|
||||
set_interface_property clock ENABLED true
|
||||
set_interface_property clock EXPORT_OF ""
|
||||
set_interface_property clock PORT_NAME_MAP ""
|
||||
set_interface_property clock CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clock SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset
|
||||
#
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
set_interface_property reset ENABLED true
|
||||
set_interface_property reset EXPORT_OF ""
|
||||
set_interface_property reset PORT_NAME_MAP ""
|
||||
set_interface_property reset CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset reset_n reset_n Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_streaming_sink
|
||||
#
|
||||
add_interface avalon_streaming_sink avalon_streaming end
|
||||
set_interface_property avalon_streaming_sink associatedClock clock
|
||||
set_interface_property avalon_streaming_sink associatedReset reset
|
||||
set_interface_property avalon_streaming_sink dataBitsPerSymbol 8
|
||||
set_interface_property avalon_streaming_sink errorDescriptor ""
|
||||
set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true
|
||||
set_interface_property avalon_streaming_sink maxChannel 0
|
||||
set_interface_property avalon_streaming_sink readyLatency 1
|
||||
set_interface_property avalon_streaming_sink ENABLED true
|
||||
set_interface_property avalon_streaming_sink EXPORT_OF ""
|
||||
set_interface_property avalon_streaming_sink PORT_NAME_MAP ""
|
||||
set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_streaming_sink sink_data data Input 24
|
||||
add_interface_port avalon_streaming_sink sink_valid valid Input 1
|
||||
add_interface_port avalon_streaming_sink sink_ready ready Output 1
|
||||
add_interface_port avalon_streaming_sink sink_sop startofpacket Input 1
|
||||
add_interface_port avalon_streaming_sink sink_eop endofpacket Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_streaming_source
|
||||
#
|
||||
add_interface avalon_streaming_source avalon_streaming start
|
||||
set_interface_property avalon_streaming_source associatedClock clock
|
||||
set_interface_property avalon_streaming_source associatedReset reset
|
||||
set_interface_property avalon_streaming_source dataBitsPerSymbol 8
|
||||
set_interface_property avalon_streaming_source errorDescriptor ""
|
||||
set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true
|
||||
set_interface_property avalon_streaming_source maxChannel 0
|
||||
set_interface_property avalon_streaming_source readyLatency 1
|
||||
set_interface_property avalon_streaming_source ENABLED true
|
||||
set_interface_property avalon_streaming_source EXPORT_OF ""
|
||||
set_interface_property avalon_streaming_source PORT_NAME_MAP ""
|
||||
set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port avalon_streaming_source source_data data Output 24
|
||||
add_interface_port avalon_streaming_source source_eop endofpacket Output 1
|
||||
add_interface_port avalon_streaming_source source_ready ready Input 1
|
||||
add_interface_port avalon_streaming_source source_sop startofpacket Output 1
|
||||
add_interface_port avalon_streaming_source source_valid valid Output 1
|
||||
|
||||
|
||||
#
|
||||
# connection point s1
|
||||
#
|
||||
add_interface s1 avalon end
|
||||
set_interface_property s1 addressUnits WORDS
|
||||
set_interface_property s1 associatedClock clock
|
||||
set_interface_property s1 associatedReset reset
|
||||
set_interface_property s1 bitsPerSymbol 8
|
||||
set_interface_property s1 burstOnBurstBoundariesOnly false
|
||||
set_interface_property s1 burstcountUnits WORDS
|
||||
set_interface_property s1 explicitAddressSpan 0
|
||||
set_interface_property s1 holdTime 0
|
||||
set_interface_property s1 linewrapBursts false
|
||||
set_interface_property s1 maximumPendingReadTransactions 0
|
||||
set_interface_property s1 maximumPendingWriteTransactions 0
|
||||
set_interface_property s1 readLatency 0
|
||||
set_interface_property s1 readWaitTime 1
|
||||
set_interface_property s1 setupTime 0
|
||||
set_interface_property s1 timingUnits Cycles
|
||||
set_interface_property s1 writeWaitTime 0
|
||||
set_interface_property s1 ENABLED true
|
||||
set_interface_property s1 EXPORT_OF ""
|
||||
set_interface_property s1 PORT_NAME_MAP ""
|
||||
set_interface_property s1 CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property s1 SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port s1 s_chipselect chipselect Input 1
|
||||
add_interface_port s1 s_read read Input 1
|
||||
add_interface_port s1 s_write write Input 1
|
||||
add_interface_port s1 s_readdata readdata Output 32
|
||||
add_interface_port s1 s_writedata writedata Input 32
|
||||
add_interface_port s1 s_address address Input 3
|
||||
set_interface_assignment s1 embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment s1 embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment s1 embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment s1 embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
|
||||
#
|
||||
# connection point conduit_mode
|
||||
#
|
||||
add_interface conduit_mode conduit end
|
||||
set_interface_property conduit_mode associatedClock clock
|
||||
set_interface_property conduit_mode associatedReset ""
|
||||
set_interface_property conduit_mode ENABLED true
|
||||
set_interface_property conduit_mode EXPORT_OF ""
|
||||
set_interface_property conduit_mode PORT_NAME_MAP ""
|
||||
set_interface_property conduit_mode CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property conduit_mode SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port conduit_mode mode new_signal Input 1
|
||||
|
||||
82
Vision/DE10_LITE_D8M_VIP_16/FpsMonitor.v
Normal file
82
Vision/DE10_LITE_D8M_VIP_16/FpsMonitor.v
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
module FpsMonitor(
|
||||
input clk50,
|
||||
input vs,
|
||||
|
||||
// output frame pixel data
|
||||
output reg [7:0] fps,
|
||||
output wire [6:0] hex_fps_h,
|
||||
output wire [6:0] hex_fps_l
|
||||
|
||||
);
|
||||
|
||||
|
||||
parameter ONE_SEC = 32'd50_000_000;
|
||||
|
||||
reg [3:0] fps_h;
|
||||
reg [3:0] fps_l;
|
||||
|
||||
reg [7:0] rfps;
|
||||
reg [3:0] rfps_l;
|
||||
reg [3:0] rfps_h;
|
||||
|
||||
reg [26:0] sec_cnt;
|
||||
reg pre_vs;
|
||||
wire one_sec_mask;
|
||||
|
||||
assign one_sec_mask = (sec_cnt>= (ONE_SEC - 1'b1) )?1'b1:1'b0;
|
||||
|
||||
always @(posedge clk50)
|
||||
if(one_sec_mask) sec_cnt <= 27'h0;
|
||||
else sec_cnt <= sec_cnt + 1'b1;
|
||||
|
||||
|
||||
always @(posedge clk50) begin
|
||||
pre_vs <= vs;
|
||||
if(sec_cnt == 27'd0) begin
|
||||
rfps <= 8'd0;
|
||||
rfps_h <= 4'd0;
|
||||
rfps_l <= 4'd0;
|
||||
end
|
||||
else if({pre_vs,vs} == 2'b01) begin
|
||||
rfps <= rfps + 1'b1;
|
||||
|
||||
if(rfps_l == 4'd9) begin
|
||||
rfps_l <= 4'd0;
|
||||
rfps_h <= rfps_h + 1'b1;
|
||||
end
|
||||
else rfps_l <= rfps_l + 1'b1;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge clk50)
|
||||
if(one_sec_mask) begin
|
||||
fps <= rfps;
|
||||
fps_h <= rfps_h;
|
||||
fps_l <= rfps_l;
|
||||
end
|
||||
|
||||
assign hex_fps_h = (fps_h == 4'd0)?7'h40: //0
|
||||
(fps_h == 4'd1)?7'h79: //1
|
||||
(fps_h == 4'd2)?7'h24: //2
|
||||
(fps_h == 4'd3)?7'h30: //3
|
||||
(fps_h == 4'd4)?7'h19: //4
|
||||
(fps_h == 4'd5)?7'h12: //5
|
||||
(fps_h == 4'd6)?7'h02: //6
|
||||
(fps_h == 4'd7)?7'h78: //7
|
||||
(fps_h == 4'd8)?7'h00: //8
|
||||
7'h10; //9
|
||||
|
||||
assign hex_fps_l = (fps_l == 4'd0)?7'h40: //0
|
||||
(fps_l == 4'd1)?7'h79: //1
|
||||
(fps_l == 4'd2)?7'h24: //2
|
||||
(fps_l == 4'd3)?7'h30: //3
|
||||
(fps_l == 4'd4)?7'h19: //4
|
||||
(fps_l == 4'd5)?7'h12: //5
|
||||
(fps_l == 4'd6)?7'h02: //6
|
||||
(fps_l == 4'd7)?7'h78: //7
|
||||
(fps_l == 4'd8)?7'h00: //8
|
||||
7'h10; //9
|
||||
endmodule
|
||||
|
||||
1471
Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys
Normal file
1471
Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys
Normal file
File diff suppressed because one or more lines are too long
21866
Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo
Normal file
21866
Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo
Normal file
File diff suppressed because one or more lines are too long
431
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf
Normal file
431
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf
Normal file
|
|
@ -0,0 +1,431 @@
|
|||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
the Altera MegaCore Function License Agreement, or other
|
||||
applicable license agreement, including, without limitation,
|
||||
that your use is for the sole purpose of programming logic
|
||||
devices manufactured by Altera and sold by Altera or its
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|
||||
(text "sda_pad_io" (rect 245 467 550 944)(font "Arial" (color 0 0 0)))
|
||||
(text "key_external_connection" (rect 98 483 334 979)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 245 507 526 1024)(font "Arial" (color 0 0 0)))
|
||||
(text "led_external_connection" (rect 101 523 340 1059)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 245 547 526 1104)(font "Arial" (color 0 0 0)))
|
||||
(text "mipi_pwdn_n_external_connection" (rect 40 563 266 1139)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 245 587 526 1184)(font "Arial" (color 0 0 0)))
|
||||
(text "mipi_reset_n_external_connection" (rect 41 603 274 1219)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 245 627 526 1264)(font "Arial" (color 0 0 0)))
|
||||
(text "reset" (rect 211 643 452 1299)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "reset_n" (rect 245 667 532 1344)(font "Arial" (color 0 0 0)))
|
||||
(text "sdram_wire" (rect 171 683 402 1379)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "addr" (rect 245 707 514 1424)(font "Arial" (color 0 0 0)))
|
||||
(text "ba" (rect 245 723 502 1456)(font "Arial" (color 0 0 0)))
|
||||
(text "cas_n" (rect 245 739 520 1488)(font "Arial" (color 0 0 0)))
|
||||
(text "cke" (rect 245 755 508 1520)(font "Arial" (color 0 0 0)))
|
||||
(text "cs_n" (rect 245 771 514 1552)(font "Arial" (color 0 0 0)))
|
||||
(text "dq" (rect 245 787 502 1584)(font "Arial" (color 0 0 0)))
|
||||
(text "dqm" (rect 245 803 508 1616)(font "Arial" (color 0 0 0)))
|
||||
(text "ras_n" (rect 245 819 520 1648)(font "Arial" (color 0 0 0)))
|
||||
(text "we_n" (rect 245 835 514 1680)(font "Arial" (color 0 0 0)))
|
||||
(text "sw_external_connection" (rect 101 851 334 1715)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "export" (rect 245 875 526 1760)(font "Arial" (color 0 0 0)))
|
||||
(text "terasic_auto_focus_0_conduit" (rect 65 891 298 1795)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "vcm_i2c_sda" (rect 245 915 556 1840)(font "Arial" (color 0 0 0)))
|
||||
(text "clk50" (rect 245 931 520 1872)(font "Arial" (color 0 0 0)))
|
||||
(text "vcm_i2c_scl" (rect 245 947 556 1904)(font "Arial" (color 0 0 0)))
|
||||
(text "terasic_camera_0_conduit_end" (rect 58 963 284 1939)(font "Arial" (color 128 0 0)(font_size 9)))
|
||||
(text "D" (rect 245 987 496 1984)(font "Arial" (color 0 0 0)))
|
||||
(text "FVAL" (rect 245 1003 514 2016)(font "Arial" (color 0 0 0)))
|
||||
(text "LVAL" (rect 245 1019 514 2048)(font "Arial" (color 0 0 0)))
|
||||
(text "PIXCLK" (rect 245 1035 526 2080)(font "Arial" (color 0 0 0)))
|
||||
(text " system " (rect 541 1056 1130 2122)(font "Arial" ))
|
||||
(line (pt 240 32)(pt 336 32)(line_width 1))
|
||||
(line (pt 336 32)(pt 336 1056)(line_width 1))
|
||||
(line (pt 240 1056)(pt 336 1056)(line_width 1))
|
||||
(line (pt 240 32)(pt 240 1056)(line_width 1))
|
||||
(line (pt 241 52)(pt 241 204)(line_width 1))
|
||||
(line (pt 242 52)(pt 242 204)(line_width 1))
|
||||
(line (pt 241 220)(pt 241 244)(line_width 1))
|
||||
(line (pt 242 220)(pt 242 244)(line_width 1))
|
||||
(line (pt 241 260)(pt 241 284)(line_width 1))
|
||||
(line (pt 242 260)(pt 242 284)(line_width 1))
|
||||
(line (pt 241 300)(pt 241 324)(line_width 1))
|
||||
(line (pt 242 300)(pt 242 324)(line_width 1))
|
||||
(line (pt 335 52)(pt 335 76)(line_width 1))
|
||||
(line (pt 334 52)(pt 334 76)(line_width 1))
|
||||
(line (pt 335 92)(pt 335 116)(line_width 1))
|
||||
(line (pt 334 92)(pt 334 116)(line_width 1))
|
||||
(line (pt 335 132)(pt 335 156)(line_width 1))
|
||||
(line (pt 334 132)(pt 334 156)(line_width 1))
|
||||
(line (pt 241 340)(pt 241 364)(line_width 1))
|
||||
(line (pt 242 340)(pt 242 364)(line_width 1))
|
||||
(line (pt 241 380)(pt 241 420)(line_width 1))
|
||||
(line (pt 242 380)(pt 242 420)(line_width 1))
|
||||
(line (pt 241 436)(pt 241 476)(line_width 1))
|
||||
(line (pt 242 436)(pt 242 476)(line_width 1))
|
||||
(line (pt 241 492)(pt 241 516)(line_width 1))
|
||||
(line (pt 242 492)(pt 242 516)(line_width 1))
|
||||
(line (pt 241 532)(pt 241 556)(line_width 1))
|
||||
(line (pt 242 532)(pt 242 556)(line_width 1))
|
||||
(line (pt 241 572)(pt 241 596)(line_width 1))
|
||||
(line (pt 242 572)(pt 242 596)(line_width 1))
|
||||
(line (pt 241 612)(pt 241 636)(line_width 1))
|
||||
(line (pt 242 612)(pt 242 636)(line_width 1))
|
||||
(line (pt 241 652)(pt 241 676)(line_width 1))
|
||||
(line (pt 242 652)(pt 242 676)(line_width 1))
|
||||
(line (pt 241 692)(pt 241 844)(line_width 1))
|
||||
(line (pt 242 692)(pt 242 844)(line_width 1))
|
||||
(line (pt 241 860)(pt 241 884)(line_width 1))
|
||||
(line (pt 242 860)(pt 242 884)(line_width 1))
|
||||
(line (pt 241 900)(pt 241 956)(line_width 1))
|
||||
(line (pt 242 900)(pt 242 956)(line_width 1))
|
||||
(line (pt 241 972)(pt 241 1044)(line_width 1))
|
||||
(line (pt 242 972)(pt 242 1044)(line_width 1))
|
||||
(line (pt 0 0)(pt 576 0)(line_width 1))
|
||||
(line (pt 576 0)(pt 576 1072)(line_width 1))
|
||||
(line (pt 0 1072)(pt 576 1072)(line_width 1))
|
||||
(line (pt 0 0)(pt 0 1072)(line_width 1))
|
||||
)
|
||||
)
|
||||
47
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp
Normal file
47
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
component Qsys is
|
||||
port (
|
||||
alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
|
||||
alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(23 downto 0); -- vid_data
|
||||
alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
|
||||
alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
|
||||
alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
|
||||
alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
|
||||
alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
|
||||
alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
|
||||
alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
|
||||
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
|
||||
altpll_0_locked_conduit_export : out std_logic; -- export
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
clk_sdram_clk : out std_logic; -- clk
|
||||
clk_vga_clk : out std_logic; -- clk
|
||||
d8m_xclkin_clk : out std_logic; -- clk
|
||||
eee_imgproc_0_conduit_mode_new_signal : in std_logic := 'X'; -- new_signal
|
||||
i2c_opencores_camera_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
|
||||
i2c_opencores_camera_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
|
||||
i2c_opencores_mipi_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
|
||||
i2c_opencores_mipi_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
|
||||
key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
|
||||
led_external_connection_export : out std_logic_vector(9 downto 0); -- export
|
||||
mipi_pwdn_n_external_connection_export : out std_logic; -- export
|
||||
mipi_reset_n_external_connection_export : out std_logic; -- export
|
||||
reset_reset_n : in std_logic := 'X'; -- reset_n
|
||||
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
|
||||
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
|
||||
sdram_wire_cas_n : out std_logic; -- cas_n
|
||||
sdram_wire_cke : out std_logic; -- cke
|
||||
sdram_wire_cs_n : out std_logic; -- cs_n
|
||||
sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
|
||||
sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
|
||||
sdram_wire_ras_n : out std_logic; -- ras_n
|
||||
sdram_wire_we_n : out std_logic; -- we_n
|
||||
sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_sda : inout std_logic := 'X'; -- vcm_i2c_sda
|
||||
terasic_auto_focus_0_conduit_clk50 : in std_logic := 'X'; -- clk50
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_scl : inout std_logic := 'X'; -- vcm_i2c_scl
|
||||
terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
|
||||
terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
|
||||
terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
|
||||
terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X' -- PIXCLK
|
||||
);
|
||||
end component Qsys;
|
||||
|
||||
5416
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html
Normal file
5416
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html
Normal file
File diff suppressed because one or more lines are too long
5410
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml
Normal file
5410
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml
Normal file
File diff suppressed because one or more lines are too long
88
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v
Normal file
88
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
|
||||
module Qsys (
|
||||
alt_vip_itc_0_clocked_video_vid_clk,
|
||||
alt_vip_itc_0_clocked_video_vid_data,
|
||||
alt_vip_itc_0_clocked_video_underflow,
|
||||
alt_vip_itc_0_clocked_video_vid_datavalid,
|
||||
alt_vip_itc_0_clocked_video_vid_v_sync,
|
||||
alt_vip_itc_0_clocked_video_vid_h_sync,
|
||||
alt_vip_itc_0_clocked_video_vid_f,
|
||||
alt_vip_itc_0_clocked_video_vid_h,
|
||||
alt_vip_itc_0_clocked_video_vid_v,
|
||||
altpll_0_areset_conduit_export,
|
||||
altpll_0_locked_conduit_export,
|
||||
clk_clk,
|
||||
clk_sdram_clk,
|
||||
clk_vga_clk,
|
||||
d8m_xclkin_clk,
|
||||
eee_imgproc_0_conduit_mode_new_signal,
|
||||
i2c_opencores_camera_export_scl_pad_io,
|
||||
i2c_opencores_camera_export_sda_pad_io,
|
||||
i2c_opencores_mipi_export_scl_pad_io,
|
||||
i2c_opencores_mipi_export_sda_pad_io,
|
||||
key_external_connection_export,
|
||||
led_external_connection_export,
|
||||
mipi_pwdn_n_external_connection_export,
|
||||
mipi_reset_n_external_connection_export,
|
||||
reset_reset_n,
|
||||
sdram_wire_addr,
|
||||
sdram_wire_ba,
|
||||
sdram_wire_cas_n,
|
||||
sdram_wire_cke,
|
||||
sdram_wire_cs_n,
|
||||
sdram_wire_dq,
|
||||
sdram_wire_dqm,
|
||||
sdram_wire_ras_n,
|
||||
sdram_wire_we_n,
|
||||
sw_external_connection_export,
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_sda,
|
||||
terasic_auto_focus_0_conduit_clk50,
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_scl,
|
||||
terasic_camera_0_conduit_end_D,
|
||||
terasic_camera_0_conduit_end_FVAL,
|
||||
terasic_camera_0_conduit_end_LVAL,
|
||||
terasic_camera_0_conduit_end_PIXCLK);
|
||||
|
||||
input alt_vip_itc_0_clocked_video_vid_clk;
|
||||
output [23:0] alt_vip_itc_0_clocked_video_vid_data;
|
||||
output alt_vip_itc_0_clocked_video_underflow;
|
||||
output alt_vip_itc_0_clocked_video_vid_datavalid;
|
||||
output alt_vip_itc_0_clocked_video_vid_v_sync;
|
||||
output alt_vip_itc_0_clocked_video_vid_h_sync;
|
||||
output alt_vip_itc_0_clocked_video_vid_f;
|
||||
output alt_vip_itc_0_clocked_video_vid_h;
|
||||
output alt_vip_itc_0_clocked_video_vid_v;
|
||||
input altpll_0_areset_conduit_export;
|
||||
output altpll_0_locked_conduit_export;
|
||||
input clk_clk;
|
||||
output clk_sdram_clk;
|
||||
output clk_vga_clk;
|
||||
output d8m_xclkin_clk;
|
||||
input eee_imgproc_0_conduit_mode_new_signal;
|
||||
inout i2c_opencores_camera_export_scl_pad_io;
|
||||
inout i2c_opencores_camera_export_sda_pad_io;
|
||||
inout i2c_opencores_mipi_export_scl_pad_io;
|
||||
inout i2c_opencores_mipi_export_sda_pad_io;
|
||||
input [1:0] key_external_connection_export;
|
||||
output [9:0] led_external_connection_export;
|
||||
output mipi_pwdn_n_external_connection_export;
|
||||
output mipi_reset_n_external_connection_export;
|
||||
input reset_reset_n;
|
||||
output [12:0] sdram_wire_addr;
|
||||
output [1:0] sdram_wire_ba;
|
||||
output sdram_wire_cas_n;
|
||||
output sdram_wire_cke;
|
||||
output sdram_wire_cs_n;
|
||||
inout [15:0] sdram_wire_dq;
|
||||
output [1:0] sdram_wire_dqm;
|
||||
output sdram_wire_ras_n;
|
||||
output sdram_wire_we_n;
|
||||
input [9:0] sw_external_connection_export;
|
||||
inout terasic_auto_focus_0_conduit_vcm_i2c_sda;
|
||||
input terasic_auto_focus_0_conduit_clk50;
|
||||
inout terasic_auto_focus_0_conduit_vcm_i2c_scl;
|
||||
input [11:0] terasic_camera_0_conduit_end_D;
|
||||
input terasic_camera_0_conduit_end_FVAL;
|
||||
input terasic_camera_0_conduit_end_LVAL;
|
||||
input terasic_camera_0_conduit_end_PIXCLK;
|
||||
endmodule
|
||||
129
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt
Normal file
129
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
Info: Starting: Create block symbol file (.bsf)
|
||||
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G
|
||||
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
|
||||
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
|
||||
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
|
||||
Progress: Parameterizing module TERASIC_CAMERA_0
|
||||
Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
|
||||
Progress: Parameterizing module alt_vip_itc_0
|
||||
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
|
||||
Progress: Parameterizing module alt_vip_vfb_0
|
||||
Progress: Adding altpll_0 [altpll 16.0]
|
||||
Progress: Parameterizing module altpll_0
|
||||
Progress: Adding clk_50 [clock_source 16.0]
|
||||
Progress: Parameterizing module clk_50
|
||||
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_camera
|
||||
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_mipi
|
||||
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
|
||||
Progress: Parameterizing module jtag_uart
|
||||
Progress: Adding key [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module key
|
||||
Progress: Adding led [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module led
|
||||
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_pwdn_n
|
||||
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_reset_n
|
||||
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
|
||||
Progress: Parameterizing module nios2_gen2
|
||||
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
|
||||
Progress: Parameterizing module onchip_memory2_0
|
||||
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
|
||||
Progress: Parameterizing module sdram
|
||||
Progress: Adding sw [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module sw
|
||||
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
|
||||
Progress: Parameterizing module sysid_qsys
|
||||
Progress: Adding timer [altera_avalon_timer 16.0]
|
||||
Progress: Parameterizing module timer
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
|
||||
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
|
||||
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
|
||||
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create block symbol file (.bsf)
|
||||
Info:
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G
|
||||
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
|
||||
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
|
||||
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
|
||||
Progress: Parameterizing module TERASIC_CAMERA_0
|
||||
Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
|
||||
Progress: Parameterizing module alt_vip_itc_0
|
||||
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
|
||||
Progress: Parameterizing module alt_vip_vfb_0
|
||||
Progress: Adding altpll_0 [altpll 16.0]
|
||||
Progress: Parameterizing module altpll_0
|
||||
Progress: Adding clk_50 [clock_source 16.0]
|
||||
Progress: Parameterizing module clk_50
|
||||
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_camera
|
||||
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_mipi
|
||||
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
|
||||
Progress: Parameterizing module jtag_uart
|
||||
Progress: Adding key [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module key
|
||||
Progress: Adding led [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module led
|
||||
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_pwdn_n
|
||||
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_reset_n
|
||||
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
|
||||
Progress: Parameterizing module nios2_gen2
|
||||
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
|
||||
Progress: Parameterizing module onchip_memory2_0
|
||||
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
|
||||
Progress: Parameterizing module sdram
|
||||
Progress: Adding sw [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module sw
|
||||
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
|
||||
Progress: Parameterizing module sysid_qsys
|
||||
Progress: Adding timer [altera_avalon_timer 16.0]
|
||||
Progress: Parameterizing module timer
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
|
||||
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
|
||||
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
|
||||
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
|
||||
Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
|
||||
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
|
||||
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
|
||||
Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
|
||||
Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
|
||||
Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
|
||||
Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
|
||||
Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
|
||||
Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092322619640" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
|
||||
Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing
|
||||
Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
|
||||
Error: Peak virtual memory: 1399 megabytes
|
||||
Error: Processing ended: Tue Mar 30 09:18:43 2021
|
||||
Error: Elapsed time: 00:00:01
|
||||
Error: Total CPU time (on all processors): 00:00:00
|
||||
Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
|
||||
Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory)
|
||||
Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
|
||||
Error: Generation stopped, 218 or more modules remaining
|
||||
Info: Qsys: Done "Qsys" with 33 modules, 34 files
|
||||
Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
129
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt
Normal file
129
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
Info: Starting: Create block symbol file (.bsf)
|
||||
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G
|
||||
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
|
||||
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
|
||||
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
|
||||
Progress: Parameterizing module TERASIC_CAMERA_0
|
||||
Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
|
||||
Progress: Parameterizing module alt_vip_itc_0
|
||||
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
|
||||
Progress: Parameterizing module alt_vip_vfb_0
|
||||
Progress: Adding altpll_0 [altpll 16.0]
|
||||
Progress: Parameterizing module altpll_0
|
||||
Progress: Adding clk_50 [clock_source 16.0]
|
||||
Progress: Parameterizing module clk_50
|
||||
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_camera
|
||||
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_mipi
|
||||
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
|
||||
Progress: Parameterizing module jtag_uart
|
||||
Progress: Adding key [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module key
|
||||
Progress: Adding led [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module led
|
||||
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_pwdn_n
|
||||
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_reset_n
|
||||
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
|
||||
Progress: Parameterizing module nios2_gen2
|
||||
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
|
||||
Progress: Parameterizing module onchip_memory2_0
|
||||
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
|
||||
Progress: Parameterizing module sdram
|
||||
Progress: Adding sw [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module sw
|
||||
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
|
||||
Progress: Parameterizing module sysid_qsys
|
||||
Progress: Adding timer [altera_avalon_timer 16.0]
|
||||
Progress: Parameterizing module timer
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
|
||||
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
|
||||
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
|
||||
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
|
||||
Info: qsys-generate succeeded.
|
||||
Info: Finished: Create block symbol file (.bsf)
|
||||
Info:
|
||||
Info: Starting: Create HDL design files for synthesis
|
||||
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G
|
||||
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
|
||||
Progress: Reading input file
|
||||
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
|
||||
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
|
||||
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
|
||||
Progress: Parameterizing module TERASIC_CAMERA_0
|
||||
Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
|
||||
Progress: Parameterizing module alt_vip_itc_0
|
||||
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
|
||||
Progress: Parameterizing module alt_vip_vfb_0
|
||||
Progress: Adding altpll_0 [altpll 16.0]
|
||||
Progress: Parameterizing module altpll_0
|
||||
Progress: Adding clk_50 [clock_source 16.0]
|
||||
Progress: Parameterizing module clk_50
|
||||
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_camera
|
||||
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
|
||||
Progress: Parameterizing module i2c_opencores_mipi
|
||||
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
|
||||
Progress: Parameterizing module jtag_uart
|
||||
Progress: Adding key [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module key
|
||||
Progress: Adding led [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module led
|
||||
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_pwdn_n
|
||||
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module mipi_reset_n
|
||||
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
|
||||
Progress: Parameterizing module nios2_gen2
|
||||
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
|
||||
Progress: Parameterizing module onchip_memory2_0
|
||||
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
|
||||
Progress: Parameterizing module sdram
|
||||
Progress: Adding sw [altera_avalon_pio 16.0]
|
||||
Progress: Parameterizing module sw
|
||||
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
|
||||
Progress: Parameterizing module sysid_qsys
|
||||
Progress: Adding timer [altera_avalon_timer 16.0]
|
||||
Progress: Parameterizing module timer
|
||||
Progress: Building connections
|
||||
Progress: Parameterizing connections
|
||||
Progress: Validating
|
||||
Progress: Done reading input file
|
||||
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
|
||||
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
|
||||
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
||||
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
|
||||
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
|
||||
Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
|
||||
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
|
||||
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
|
||||
Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
|
||||
Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
|
||||
Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
|
||||
Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
|
||||
Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
|
||||
Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092145442977" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
|
||||
Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v is missing
|
||||
Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
|
||||
Error: Peak virtual memory: 1399 megabytes
|
||||
Error: Processing ended: Tue Mar 30 09:15:46 2021
|
||||
Error: Elapsed time: 00:00:00
|
||||
Error: Total CPU time (on all processors): 00:00:00
|
||||
Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
|
||||
Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v (No such file or directory)
|
||||
Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
|
||||
Error: Generation stopped, 218 or more modules remaining
|
||||
Info: Qsys: Done "Qsys" with 33 modules, 34 files
|
||||
Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning
|
||||
Info: Finished: Create HDL design files for synthesis
|
||||
45
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v
Normal file
45
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
Qsys u0 (
|
||||
.alt_vip_itc_0_clocked_video_vid_clk (<connected-to-alt_vip_itc_0_clocked_video_vid_clk>), // alt_vip_itc_0_clocked_video.vid_clk
|
||||
.alt_vip_itc_0_clocked_video_vid_data (<connected-to-alt_vip_itc_0_clocked_video_vid_data>), // .vid_data
|
||||
.alt_vip_itc_0_clocked_video_underflow (<connected-to-alt_vip_itc_0_clocked_video_underflow>), // .underflow
|
||||
.alt_vip_itc_0_clocked_video_vid_datavalid (<connected-to-alt_vip_itc_0_clocked_video_vid_datavalid>), // .vid_datavalid
|
||||
.alt_vip_itc_0_clocked_video_vid_v_sync (<connected-to-alt_vip_itc_0_clocked_video_vid_v_sync>), // .vid_v_sync
|
||||
.alt_vip_itc_0_clocked_video_vid_h_sync (<connected-to-alt_vip_itc_0_clocked_video_vid_h_sync>), // .vid_h_sync
|
||||
.alt_vip_itc_0_clocked_video_vid_f (<connected-to-alt_vip_itc_0_clocked_video_vid_f>), // .vid_f
|
||||
.alt_vip_itc_0_clocked_video_vid_h (<connected-to-alt_vip_itc_0_clocked_video_vid_h>), // .vid_h
|
||||
.alt_vip_itc_0_clocked_video_vid_v (<connected-to-alt_vip_itc_0_clocked_video_vid_v>), // .vid_v
|
||||
.altpll_0_areset_conduit_export (<connected-to-altpll_0_areset_conduit_export>), // altpll_0_areset_conduit.export
|
||||
.altpll_0_locked_conduit_export (<connected-to-altpll_0_locked_conduit_export>), // altpll_0_locked_conduit.export
|
||||
.clk_clk (<connected-to-clk_clk>), // clk.clk
|
||||
.clk_sdram_clk (<connected-to-clk_sdram_clk>), // clk_sdram.clk
|
||||
.clk_vga_clk (<connected-to-clk_vga_clk>), // clk_vga.clk
|
||||
.d8m_xclkin_clk (<connected-to-d8m_xclkin_clk>), // d8m_xclkin.clk
|
||||
.eee_imgproc_0_conduit_mode_new_signal (<connected-to-eee_imgproc_0_conduit_mode_new_signal>), // eee_imgproc_0_conduit_mode.new_signal
|
||||
.i2c_opencores_camera_export_scl_pad_io (<connected-to-i2c_opencores_camera_export_scl_pad_io>), // i2c_opencores_camera_export.scl_pad_io
|
||||
.i2c_opencores_camera_export_sda_pad_io (<connected-to-i2c_opencores_camera_export_sda_pad_io>), // .sda_pad_io
|
||||
.i2c_opencores_mipi_export_scl_pad_io (<connected-to-i2c_opencores_mipi_export_scl_pad_io>), // i2c_opencores_mipi_export.scl_pad_io
|
||||
.i2c_opencores_mipi_export_sda_pad_io (<connected-to-i2c_opencores_mipi_export_sda_pad_io>), // .sda_pad_io
|
||||
.key_external_connection_export (<connected-to-key_external_connection_export>), // key_external_connection.export
|
||||
.led_external_connection_export (<connected-to-led_external_connection_export>), // led_external_connection.export
|
||||
.mipi_pwdn_n_external_connection_export (<connected-to-mipi_pwdn_n_external_connection_export>), // mipi_pwdn_n_external_connection.export
|
||||
.mipi_reset_n_external_connection_export (<connected-to-mipi_reset_n_external_connection_export>), // mipi_reset_n_external_connection.export
|
||||
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
|
||||
.sdram_wire_addr (<connected-to-sdram_wire_addr>), // sdram_wire.addr
|
||||
.sdram_wire_ba (<connected-to-sdram_wire_ba>), // .ba
|
||||
.sdram_wire_cas_n (<connected-to-sdram_wire_cas_n>), // .cas_n
|
||||
.sdram_wire_cke (<connected-to-sdram_wire_cke>), // .cke
|
||||
.sdram_wire_cs_n (<connected-to-sdram_wire_cs_n>), // .cs_n
|
||||
.sdram_wire_dq (<connected-to-sdram_wire_dq>), // .dq
|
||||
.sdram_wire_dqm (<connected-to-sdram_wire_dqm>), // .dqm
|
||||
.sdram_wire_ras_n (<connected-to-sdram_wire_ras_n>), // .ras_n
|
||||
.sdram_wire_we_n (<connected-to-sdram_wire_we_n>), // .we_n
|
||||
.sw_external_connection_export (<connected-to-sw_external_connection_export>), // sw_external_connection.export
|
||||
.terasic_auto_focus_0_conduit_vcm_i2c_sda (<connected-to-terasic_auto_focus_0_conduit_vcm_i2c_sda>), // terasic_auto_focus_0_conduit.vcm_i2c_sda
|
||||
.terasic_auto_focus_0_conduit_clk50 (<connected-to-terasic_auto_focus_0_conduit_clk50>), // .clk50
|
||||
.terasic_auto_focus_0_conduit_vcm_i2c_scl (<connected-to-terasic_auto_focus_0_conduit_vcm_i2c_scl>), // .vcm_i2c_scl
|
||||
.terasic_camera_0_conduit_end_D (<connected-to-terasic_camera_0_conduit_end_D>), // terasic_camera_0_conduit_end.D
|
||||
.terasic_camera_0_conduit_end_FVAL (<connected-to-terasic_camera_0_conduit_end_FVAL>), // .FVAL
|
||||
.terasic_camera_0_conduit_end_LVAL (<connected-to-terasic_camera_0_conduit_end_LVAL>), // .LVAL
|
||||
.terasic_camera_0_conduit_end_PIXCLK (<connected-to-terasic_camera_0_conduit_end_PIXCLK>) // .PIXCLK
|
||||
);
|
||||
|
||||
93
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd
Normal file
93
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
component Qsys is
|
||||
port (
|
||||
alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
|
||||
alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(23 downto 0); -- vid_data
|
||||
alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
|
||||
alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
|
||||
alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
|
||||
alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
|
||||
alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
|
||||
alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
|
||||
alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
|
||||
altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
|
||||
altpll_0_locked_conduit_export : out std_logic; -- export
|
||||
clk_clk : in std_logic := 'X'; -- clk
|
||||
clk_sdram_clk : out std_logic; -- clk
|
||||
clk_vga_clk : out std_logic; -- clk
|
||||
d8m_xclkin_clk : out std_logic; -- clk
|
||||
eee_imgproc_0_conduit_mode_new_signal : in std_logic := 'X'; -- new_signal
|
||||
i2c_opencores_camera_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
|
||||
i2c_opencores_camera_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
|
||||
i2c_opencores_mipi_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
|
||||
i2c_opencores_mipi_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
|
||||
key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
|
||||
led_external_connection_export : out std_logic_vector(9 downto 0); -- export
|
||||
mipi_pwdn_n_external_connection_export : out std_logic; -- export
|
||||
mipi_reset_n_external_connection_export : out std_logic; -- export
|
||||
reset_reset_n : in std_logic := 'X'; -- reset_n
|
||||
sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
|
||||
sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
|
||||
sdram_wire_cas_n : out std_logic; -- cas_n
|
||||
sdram_wire_cke : out std_logic; -- cke
|
||||
sdram_wire_cs_n : out std_logic; -- cs_n
|
||||
sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
|
||||
sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
|
||||
sdram_wire_ras_n : out std_logic; -- ras_n
|
||||
sdram_wire_we_n : out std_logic; -- we_n
|
||||
sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_sda : inout std_logic := 'X'; -- vcm_i2c_sda
|
||||
terasic_auto_focus_0_conduit_clk50 : in std_logic := 'X'; -- clk50
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_scl : inout std_logic := 'X'; -- vcm_i2c_scl
|
||||
terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
|
||||
terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
|
||||
terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
|
||||
terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X' -- PIXCLK
|
||||
);
|
||||
end component Qsys;
|
||||
|
||||
u0 : component Qsys
|
||||
port map (
|
||||
alt_vip_itc_0_clocked_video_vid_clk => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_clk, -- alt_vip_itc_0_clocked_video.vid_clk
|
||||
alt_vip_itc_0_clocked_video_vid_data => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_data, -- .vid_data
|
||||
alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_alt_vip_itc_0_clocked_video_underflow, -- .underflow
|
||||
alt_vip_itc_0_clocked_video_vid_datavalid => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_datavalid, -- .vid_datavalid
|
||||
alt_vip_itc_0_clocked_video_vid_v_sync => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_v_sync, -- .vid_v_sync
|
||||
alt_vip_itc_0_clocked_video_vid_h_sync => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_h_sync, -- .vid_h_sync
|
||||
alt_vip_itc_0_clocked_video_vid_f => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_f, -- .vid_f
|
||||
alt_vip_itc_0_clocked_video_vid_h => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_h, -- .vid_h
|
||||
alt_vip_itc_0_clocked_video_vid_v => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_v, -- .vid_v
|
||||
altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
|
||||
altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
|
||||
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
|
||||
clk_sdram_clk => CONNECTED_TO_clk_sdram_clk, -- clk_sdram.clk
|
||||
clk_vga_clk => CONNECTED_TO_clk_vga_clk, -- clk_vga.clk
|
||||
d8m_xclkin_clk => CONNECTED_TO_d8m_xclkin_clk, -- d8m_xclkin.clk
|
||||
eee_imgproc_0_conduit_mode_new_signal => CONNECTED_TO_eee_imgproc_0_conduit_mode_new_signal, -- eee_imgproc_0_conduit_mode.new_signal
|
||||
i2c_opencores_camera_export_scl_pad_io => CONNECTED_TO_i2c_opencores_camera_export_scl_pad_io, -- i2c_opencores_camera_export.scl_pad_io
|
||||
i2c_opencores_camera_export_sda_pad_io => CONNECTED_TO_i2c_opencores_camera_export_sda_pad_io, -- .sda_pad_io
|
||||
i2c_opencores_mipi_export_scl_pad_io => CONNECTED_TO_i2c_opencores_mipi_export_scl_pad_io, -- i2c_opencores_mipi_export.scl_pad_io
|
||||
i2c_opencores_mipi_export_sda_pad_io => CONNECTED_TO_i2c_opencores_mipi_export_sda_pad_io, -- .sda_pad_io
|
||||
key_external_connection_export => CONNECTED_TO_key_external_connection_export, -- key_external_connection.export
|
||||
led_external_connection_export => CONNECTED_TO_led_external_connection_export, -- led_external_connection.export
|
||||
mipi_pwdn_n_external_connection_export => CONNECTED_TO_mipi_pwdn_n_external_connection_export, -- mipi_pwdn_n_external_connection.export
|
||||
mipi_reset_n_external_connection_export => CONNECTED_TO_mipi_reset_n_external_connection_export, -- mipi_reset_n_external_connection.export
|
||||
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
|
||||
sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
|
||||
sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
|
||||
sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
|
||||
sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
|
||||
sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
|
||||
sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
|
||||
sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
|
||||
sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
|
||||
sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
|
||||
sw_external_connection_export => CONNECTED_TO_sw_external_connection_export, -- sw_external_connection.export
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_sda => CONNECTED_TO_terasic_auto_focus_0_conduit_vcm_i2c_sda, -- terasic_auto_focus_0_conduit.vcm_i2c_sda
|
||||
terasic_auto_focus_0_conduit_clk50 => CONNECTED_TO_terasic_auto_focus_0_conduit_clk50, -- .clk50
|
||||
terasic_auto_focus_0_conduit_vcm_i2c_scl => CONNECTED_TO_terasic_auto_focus_0_conduit_vcm_i2c_scl, -- .vcm_i2c_scl
|
||||
terasic_camera_0_conduit_end_D => CONNECTED_TO_terasic_camera_0_conduit_end_D, -- terasic_camera_0_conduit_end.D
|
||||
terasic_camera_0_conduit_end_FVAL => CONNECTED_TO_terasic_camera_0_conduit_end_FVAL, -- .FVAL
|
||||
terasic_camera_0_conduit_end_LVAL => CONNECTED_TO_terasic_camera_0_conduit_end_LVAL, -- .LVAL
|
||||
terasic_camera_0_conduit_end_PIXCLK => CONNECTED_TO_terasic_camera_0_conduit_end_PIXCLK -- .PIXCLK
|
||||
);
|
||||
|
||||
BIN
Vision/DE10_LITE_D8M_VIP_16/demo_batch/D8M_Camera_Test.elf
Normal file
BIN
Vision/DE10_LITE_D8M_VIP_16/demo_batch/D8M_Camera_Test.elf
Normal file
Binary file not shown.
BIN
Vision/DE10_LITE_D8M_VIP_16/demo_batch/DE10_LITE_D8M_VIP.sof
Normal file
BIN
Vision/DE10_LITE_D8M_VIP_16/demo_batch/DE10_LITE_D8M_VIP.sof
Normal file
Binary file not shown.
26
Vision/DE10_LITE_D8M_VIP_16/demo_batch/test.bat
Normal file
26
Vision/DE10_LITE_D8M_VIP_16/demo_batch/test.bat
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
|
||||
@ REM ######################################
|
||||
@ REM # Variable to ignore <CR> in DOS
|
||||
@ REM # line endings
|
||||
@ set SHELLOPTS=igncr
|
||||
|
||||
@ REM ######################################
|
||||
@ REM # Variable to ignore mixed paths
|
||||
@ REM # i.e. G:/$SOPC_KIT_NIOS2/bin
|
||||
@ set CYGWIN=nodosfilewarning
|
||||
|
||||
@set QUARTUS_BIN=%QUARTUS_ROOTDIR%\\bin
|
||||
@if exist %QUARTUS_BIN%\\quartus_pgm.exe (goto DownLoad)
|
||||
|
||||
@set QUARTUS_BIN=%QUARTUS_ROOTDIR%\\bin64
|
||||
@if exist %QUARTUS_BIN%\\quartus_pgm.exe (goto DownLoad)
|
||||
|
||||
:: Prepare for future use (if exes are in bin32)
|
||||
@set QUARTUS_BIN=%QUARTUS_ROOTDIR%\\bin32
|
||||
|
||||
:DownLoad
|
||||
%QUARTUS_BIN%\\quartus_pgm.exe -m jtag -c 1 -o "p;DE10_LITE_D8M_VIP.sof"
|
||||
@ set SOPC_BUILDER_PATH=%SOPC_KIT_NIOS2%+%SOPC_BUILDER_PATH%
|
||||
@ "%QUARTUS_BIN%\\cygwin\bin\bash.exe" --rcfile ".\test.sh"
|
||||
|
||||
pause
|
||||
6
Vision/DE10_LITE_D8M_VIP_16/demo_batch/test.sh
Normal file
6
Vision/DE10_LITE_D8M_VIP_16/demo_batch/test.sh
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# file: nios2_sdk_shell_bashrc
|
||||
|
||||
"$SOPC_KIT_NIOS2/nios2_command_shell.sh" nios2-download D8M_Camera_Test.elf -c 1 -g
|
||||
"$SOPC_KIT_NIOS2/nios2_command_shell.sh" nios2-terminal -c 1
|
||||
|
||||
# End of file
|
||||
61
Vision/DE10_LITE_D8M_VIP_16/greybox_tmp/cbx_args.txt
Normal file
61
Vision/DE10_LITE_D8M_VIP_16/greybox_tmp/cbx_args.txt
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
BANDWIDTH_TYPE=AUTO
|
||||
CLK0_DIVIDE_BY=1
|
||||
CLK0_DUTY_CYCLE=50
|
||||
CLK0_MULTIPLY_BY=1
|
||||
CLK0_PHASE_SHIFT=0
|
||||
COMPENSATE_CLOCK=CLK0
|
||||
INCLK0_INPUT_FREQUENCY=10000
|
||||
INTENDED_DEVICE_FAMILY="MAX 10"
|
||||
LPM_TYPE=altpll
|
||||
OPERATION_MODE=NORMAL
|
||||
PLL_TYPE=AUTO
|
||||
PORT_ACTIVECLOCK=PORT_UNUSED
|
||||
PORT_ARESET=PORT_USED
|
||||
PORT_CLKBAD0=PORT_UNUSED
|
||||
PORT_CLKBAD1=PORT_UNUSED
|
||||
PORT_CLKLOSS=PORT_UNUSED
|
||||
PORT_CLKSWITCH=PORT_UNUSED
|
||||
PORT_CONFIGUPDATE=PORT_UNUSED
|
||||
PORT_FBIN=PORT_UNUSED
|
||||
PORT_INCLK0=PORT_USED
|
||||
PORT_INCLK1=PORT_UNUSED
|
||||
PORT_LOCKED=PORT_USED
|
||||
PORT_PFDENA=PORT_UNUSED
|
||||
PORT_PHASECOUNTERSELECT=PORT_UNUSED
|
||||
PORT_PHASEDONE=PORT_UNUSED
|
||||
PORT_PHASESTEP=PORT_UNUSED
|
||||
PORT_PHASEUPDOWN=PORT_UNUSED
|
||||
PORT_PLLENA=PORT_UNUSED
|
||||
PORT_SCANACLR=PORT_UNUSED
|
||||
PORT_SCANCLK=PORT_UNUSED
|
||||
PORT_SCANCLKENA=PORT_UNUSED
|
||||
PORT_SCANDATA=PORT_UNUSED
|
||||
PORT_SCANDATAOUT=PORT_UNUSED
|
||||
PORT_SCANDONE=PORT_UNUSED
|
||||
PORT_SCANREAD=PORT_UNUSED
|
||||
PORT_SCANWRITE=PORT_UNUSED
|
||||
PORT_clk0=PORT_USED
|
||||
PORT_clk1=PORT_UNUSED
|
||||
PORT_clk2=PORT_UNUSED
|
||||
PORT_clk3=PORT_UNUSED
|
||||
PORT_clk4=PORT_UNUSED
|
||||
PORT_clk5=PORT_UNUSED
|
||||
PORT_clkena0=PORT_UNUSED
|
||||
PORT_clkena1=PORT_UNUSED
|
||||
PORT_clkena2=PORT_UNUSED
|
||||
PORT_clkena3=PORT_UNUSED
|
||||
PORT_clkena4=PORT_UNUSED
|
||||
PORT_clkena5=PORT_UNUSED
|
||||
PORT_extclk0=PORT_UNUSED
|
||||
PORT_extclk1=PORT_UNUSED
|
||||
PORT_extclk2=PORT_UNUSED
|
||||
PORT_extclk3=PORT_UNUSED
|
||||
SELF_RESET_ON_LOSS_LOCK=OFF
|
||||
WIDTH_CLOCK=5
|
||||
DEVICE_FAMILY="MAX 10"
|
||||
CBX_AUTO_BLACKBOX=ALL
|
||||
areset
|
||||
inclk
|
||||
inclk
|
||||
clk
|
||||
locked
|
||||
1085
Vision/DE10_LITE_D8M_VIP_16/hs_err_pid13062.log
Normal file
1085
Vision/DE10_LITE_D8M_VIP_16/hs_err_pid13062.log
Normal file
File diff suppressed because it is too large
Load diff
305
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v
Normal file
305
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v
Normal file
|
|
@ -0,0 +1,305 @@
|
|||
module EEE_IMGPROC(
|
||||
// global clock & reset
|
||||
clk,
|
||||
reset_n,
|
||||
|
||||
// mm slave
|
||||
s_chipselect,
|
||||
s_read,
|
||||
s_write,
|
||||
s_readdata,
|
||||
s_writedata,
|
||||
s_address,
|
||||
|
||||
// stream sink
|
||||
sink_data,
|
||||
sink_valid,
|
||||
sink_ready,
|
||||
sink_sop,
|
||||
sink_eop,
|
||||
|
||||
// streaming source
|
||||
source_data,
|
||||
source_valid,
|
||||
source_ready,
|
||||
source_sop,
|
||||
source_eop,
|
||||
|
||||
// conduit
|
||||
mode
|
||||
|
||||
);
|
||||
|
||||
|
||||
// global clock & reset
|
||||
input clk;
|
||||
input reset_n;
|
||||
|
||||
// mm slave
|
||||
input s_chipselect;
|
||||
input s_read;
|
||||
input s_write;
|
||||
output reg [31:0] s_readdata;
|
||||
input [31:0] s_writedata;
|
||||
input [2:0] s_address;
|
||||
|
||||
|
||||
// streaming sink
|
||||
input [23:0] sink_data;
|
||||
input sink_valid;
|
||||
output sink_ready;
|
||||
input sink_sop;
|
||||
input sink_eop;
|
||||
|
||||
// streaming source
|
||||
output [23:0] source_data;
|
||||
output source_valid;
|
||||
input source_ready;
|
||||
output source_sop;
|
||||
output source_eop;
|
||||
|
||||
// conduit export
|
||||
input mode;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
parameter IMAGE_W = 11'd640;
|
||||
parameter IMAGE_H = 11'd480;
|
||||
parameter MESSAGE_BUF_MAX = 256;
|
||||
parameter MSG_INTERVAL = 6;
|
||||
parameter BB_COL_DEFAULT = 24'h00ff00;
|
||||
|
||||
|
||||
wire [7:0] red, green, blue, grey;
|
||||
wire [7:0] red_out, green_out, blue_out;
|
||||
|
||||
wire sop, eop, in_valid, out_ready;
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detect red areas
|
||||
wire red_detect;
|
||||
assign red_detect = red[7] & ~green[7] & ~blue[7];
|
||||
|
||||
// Find boundary of cursor box
|
||||
|
||||
// Highlight detected areas
|
||||
wire [23:0] red_high;
|
||||
assign grey = green[7:1] + red[7:2] + blue[7:2]; //Grey = green/2 + red/4 + blue/4
|
||||
assign red_high = red_detect ? {8'hff, 8'h0, 8'h0} : {grey, grey, grey};
|
||||
|
||||
// Show bounding box
|
||||
wire [23:0] new_image;
|
||||
wire bb_active;
|
||||
assign bb_active = (x == left) | (x == right) | (y == top) | (y == bottom);
|
||||
assign new_image = bb_active ? bb_col : red_high;
|
||||
|
||||
// Switch output pixels depending on mode switch
|
||||
// Don't modify the start-of-packet word - it's a packet discriptor
|
||||
// Don't modify data in non-video packets
|
||||
assign {red_out, green_out, blue_out} = (mode & ~sop & packet_video) ? new_image : {red,green,blue};
|
||||
|
||||
//Count valid pixels to tget the image coordinates. Reset and detect packet type on Start of Packet.
|
||||
reg [10:0] x, y;
|
||||
reg packet_video;
|
||||
always@(posedge clk) begin
|
||||
if (sop) begin
|
||||
x <= 11'h0;
|
||||
y <= 11'h0;
|
||||
packet_video <= (blue[3:0] == 3'h0);
|
||||
end
|
||||
else if (in_valid) begin
|
||||
if (x == IMAGE_W-1) begin
|
||||
x <= 11'h0;
|
||||
y <= y + 11'h1;
|
||||
end
|
||||
else begin
|
||||
x <= x + 11'h1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
//Find first and last red pixels
|
||||
reg [10:0] x_min, y_min, x_max, y_max;
|
||||
always@(posedge clk) begin
|
||||
if (red_detect & in_valid) begin //Update bounds when the pixel is red
|
||||
if (x < x_min) x_min <= x;
|
||||
if (x > x_max) x_max <= x;
|
||||
if (y < y_min) y_min <= y;
|
||||
y_max <= y;
|
||||
end
|
||||
if (sop & in_valid) begin //Reset bounds on start of packet
|
||||
x_min <= IMAGE_W-11'h1;
|
||||
x_max <= 0;
|
||||
y_min <= IMAGE_H-11'h1;
|
||||
y_max <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
//Process bounding box at the end of the frame.
|
||||
reg [1:0] msg_state;
|
||||
reg [10:0] left, right, top, bottom;
|
||||
reg [7:0] frame_count;
|
||||
always@(posedge clk) begin
|
||||
if (eop & in_valid & packet_video) begin //Ignore non-video packets
|
||||
|
||||
//Latch edges for display overlay on next frame
|
||||
left <= x_min;
|
||||
right <= x_max;
|
||||
top <= y_min;
|
||||
bottom <= y_max;
|
||||
|
||||
|
||||
//Start message writer FSM once every MSG_INTERVAL frames, if there is room in the FIFO
|
||||
frame_count <= frame_count - 1;
|
||||
|
||||
if (frame_count == 0 && msg_buf_size < MESSAGE_BUF_MAX - 3) begin
|
||||
msg_state <= 2'b01;
|
||||
frame_count <= MSG_INTERVAL-1;
|
||||
end
|
||||
end
|
||||
|
||||
//Cycle through message writer states once started
|
||||
if (msg_state != 2'b00) msg_state <= msg_state + 2'b01;
|
||||
|
||||
end
|
||||
|
||||
//Generate output messages for CPU
|
||||
reg [31:0] msg_buf_in;
|
||||
wire [31:0] msg_buf_out;
|
||||
reg msg_buf_wr;
|
||||
wire msg_buf_rd, msg_buf_flush;
|
||||
wire [7:0] msg_buf_size;
|
||||
wire msg_buf_empty;
|
||||
|
||||
`define RED_BOX_MSG_ID "RBB"
|
||||
|
||||
always@(*) begin //Write words to FIFO as state machine advances
|
||||
case(msg_state)
|
||||
2'b00: begin
|
||||
msg_buf_in = 32'b0;
|
||||
msg_buf_wr = 1'b0;
|
||||
end
|
||||
2'b01: begin
|
||||
msg_buf_in = `RED_BOX_MSG_ID; //Message ID
|
||||
msg_buf_wr = 1'b1;
|
||||
end
|
||||
2'b10: begin
|
||||
msg_buf_in = {5'b0, x_min, 5'b0, y_min}; //Top left coordinate
|
||||
msg_buf_wr = 1'b1;
|
||||
end
|
||||
2'b11: begin
|
||||
msg_buf_in = {5'b0, x_max, 5'b0, y_max}; //Bottom right coordinate
|
||||
msg_buf_wr = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
//Output message FIFO
|
||||
MSG_FIFO MSG_FIFO_inst (
|
||||
.clock (clk),
|
||||
.data (msg_buf_in),
|
||||
.rdreq (msg_buf_rd),
|
||||
.sclr (~reset_n | msg_buf_flush),
|
||||
.wrreq (msg_buf_wr),
|
||||
.q (msg_buf_out),
|
||||
.usedw (msg_buf_size),
|
||||
.empty (msg_buf_empty)
|
||||
);
|
||||
|
||||
|
||||
//Streaming registers to buffer video signal
|
||||
STREAM_REG #(.DATA_WIDTH(26)) in_reg (
|
||||
.clk(clk),
|
||||
.rst_n(reset_n),
|
||||
.ready_out(sink_ready),
|
||||
.valid_out(in_valid),
|
||||
.data_out({red,green,blue,sop,eop}),
|
||||
.ready_in(out_ready),
|
||||
.valid_in(sink_valid),
|
||||
.data_in({sink_data,sink_sop,sink_eop})
|
||||
);
|
||||
|
||||
STREAM_REG #(.DATA_WIDTH(26)) out_reg (
|
||||
.clk(clk),
|
||||
.rst_n(reset_n),
|
||||
.ready_out(out_ready),
|
||||
.valid_out(source_valid),
|
||||
.data_out({source_data,source_sop,source_eop}),
|
||||
.ready_in(source_ready),
|
||||
.valid_in(in_valid),
|
||||
.data_in({red_out, green_out, blue_out, sop, eop})
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////
|
||||
/// Memory-mapped port /////
|
||||
/////////////////////////////////
|
||||
|
||||
// Addresses
|
||||
`define REG_STATUS 0
|
||||
`define READ_MSG 1
|
||||
`define READ_ID 2
|
||||
`define REG_BBCOL 3
|
||||
|
||||
//Status register bits
|
||||
// 31:16 - unimplemented
|
||||
// 15:8 - number of words in message buffer (read only)
|
||||
// 7:5 - unused
|
||||
// 4 - flush message buffer (write only - read as 0)
|
||||
// 3:0 - unused
|
||||
|
||||
|
||||
// Process write
|
||||
|
||||
reg [7:0] reg_status;
|
||||
reg [23:0] bb_col;
|
||||
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (~reset_n)
|
||||
begin
|
||||
reg_status <= 8'b0;
|
||||
bb_col <= BB_COL_DEFAULT;
|
||||
end
|
||||
else begin
|
||||
if(s_chipselect & s_write) begin
|
||||
if (s_address == `REG_STATUS) reg_status <= s_writedata[7:0];
|
||||
if (s_address == `REG_BBCOL) bb_col <= s_writedata[23:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//Flush the message buffer if 1 is written to status register bit 4
|
||||
assign msg_buf_flush = (s_chipselect & s_write & (s_address == `REG_STATUS) & s_writedata[4]);
|
||||
|
||||
|
||||
// Process reads
|
||||
reg read_d; //Store the read signal for correct updating of the message buffer
|
||||
|
||||
// Copy the requested word to the output port when there is a read.
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (~reset_n) begin
|
||||
s_readdata <= {32'b0};
|
||||
read_d <= 1'b0;
|
||||
end
|
||||
|
||||
else if (s_chipselect & s_read) begin
|
||||
if (s_address == `REG_STATUS) s_readdata <= {16'b0,msg_buf_size,reg_status};
|
||||
if (s_address == `READ_MSG) s_readdata <= {msg_buf_out};
|
||||
if (s_address == `READ_ID) s_readdata <= 32'h1234EEE2;
|
||||
if (s_address == `REG_BBCOL) s_readdata <= {8'h0, bb_col};
|
||||
end
|
||||
|
||||
read_d <= s_read;
|
||||
end
|
||||
|
||||
//Fetch next word from message buffer after read from READ_MSG
|
||||
assign msg_buf_rd = s_chipselect & s_read & ~read_d & ~msg_buf_empty & (s_address == `READ_MSG);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
6
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO.qip
Normal file
6
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO.qip
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "FIFO"
|
||||
set_global_assignment -name IP_TOOL_VERSION "16.0"
|
||||
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "MSG_FIFO.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "MSG_FIFO_inst.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "MSG_FIFO_bb.v"]
|
||||
163
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO.v
Normal file
163
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO.v
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: scfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: MSG_FIFO.v
|
||||
// Megafunction Name(s):
|
||||
// scfifo
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 16.0.2 Build 222 07/20/2016 SJ Standard Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
//the Altera MegaCore Function License Agreement, or other
|
||||
//applicable license agreement, including, without limitation,
|
||||
//that your use is for the sole purpose of programming logic
|
||||
//devices manufactured by Altera and sold by Altera or its
|
||||
//authorized distributors. Please refer to the applicable
|
||||
//agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module MSG_FIFO (
|
||||
clock,
|
||||
data,
|
||||
rdreq,
|
||||
sclr,
|
||||
wrreq,
|
||||
empty,
|
||||
q,
|
||||
usedw);
|
||||
|
||||
input clock;
|
||||
input [31:0] data;
|
||||
input rdreq;
|
||||
input sclr;
|
||||
input wrreq;
|
||||
output empty;
|
||||
output [31:0] q;
|
||||
output [7:0] usedw;
|
||||
|
||||
wire sub_wire0;
|
||||
wire [31:0] sub_wire1;
|
||||
wire [7:0] sub_wire2;
|
||||
wire empty = sub_wire0;
|
||||
wire [31:0] q = sub_wire1[31:0];
|
||||
wire [7:0] usedw = sub_wire2[7:0];
|
||||
|
||||
scfifo scfifo_component (
|
||||
.clock (clock),
|
||||
.data (data),
|
||||
.rdreq (rdreq),
|
||||
.sclr (sclr),
|
||||
.wrreq (wrreq),
|
||||
.empty (sub_wire0),
|
||||
.q (sub_wire1),
|
||||
.usedw (sub_wire2),
|
||||
.aclr (),
|
||||
.almost_empty (),
|
||||
.almost_full (),
|
||||
.eccstatus (),
|
||||
.full ());
|
||||
defparam
|
||||
scfifo_component.add_ram_output_register = "OFF",
|
||||
scfifo_component.intended_device_family = "MAX 10",
|
||||
scfifo_component.lpm_numwords = 256,
|
||||
scfifo_component.lpm_showahead = "ON",
|
||||
scfifo_component.lpm_type = "scfifo",
|
||||
scfifo_component.lpm_width = 32,
|
||||
scfifo_component.lpm_widthu = 8,
|
||||
scfifo_component.overflow_checking = "ON",
|
||||
scfifo_component.underflow_checking = "ON",
|
||||
scfifo_component.use_eab = "ON";
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
|
||||
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
|
||||
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
|
||||
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
|
||||
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
124
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO_bb.v
Normal file
124
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO_bb.v
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
// megafunction wizard: %FIFO%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: scfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: MSG_FIFO.v
|
||||
// Megafunction Name(s):
|
||||
// scfifo
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 16.0.2 Build 222 07/20/2016 SJ Standard Edition
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, the Altera Quartus Prime License Agreement,
|
||||
//the Altera MegaCore Function License Agreement, or other
|
||||
//applicable license agreement, including, without limitation,
|
||||
//that your use is for the sole purpose of programming logic
|
||||
//devices manufactured by Altera and sold by Altera or its
|
||||
//authorized distributors. Please refer to the applicable
|
||||
//agreement for further details.
|
||||
|
||||
module MSG_FIFO (
|
||||
clock,
|
||||
data,
|
||||
rdreq,
|
||||
sclr,
|
||||
wrreq,
|
||||
empty,
|
||||
q,
|
||||
usedw);
|
||||
|
||||
input clock;
|
||||
input [31:0] data;
|
||||
input rdreq;
|
||||
input sclr;
|
||||
input wrreq;
|
||||
output empty;
|
||||
output [31:0] q;
|
||||
output [7:0] usedw;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "256"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "32"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
|
||||
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
|
||||
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
|
||||
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
|
||||
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO_inst.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL MSG_FIFO_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
10
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO_inst.v
Normal file
10
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO_inst.v
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
MSG_FIFO MSG_FIFO_inst (
|
||||
.clock ( clock_sig ),
|
||||
.data ( data_sig ),
|
||||
.rdreq ( rdreq_sig ),
|
||||
.sclr ( sclr_sig ),
|
||||
.wrreq ( wrreq_sig ),
|
||||
.empty ( empty_sig ),
|
||||
.q ( q_sig ),
|
||||
.usedw ( usedw_sig )
|
||||
);
|
||||
39
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG.v
Normal file
39
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG.v
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
module STREAM_REG(ready_out, valid_out, data_out, ready_in, valid_in, data_in, clk, rst_n);
|
||||
|
||||
// Input Port(s)
|
||||
input clk, rst_n;
|
||||
input ready_in, valid_in;
|
||||
input [DATA_WIDTH-1:0] data_in;
|
||||
|
||||
// Output Port(s)
|
||||
output ready_out, valid_out;
|
||||
output reg [DATA_WIDTH-1:0] data_out;
|
||||
|
||||
// Parameter Declaration(s)
|
||||
parameter DATA_WIDTH = 26;
|
||||
|
||||
reg data_valid, ready_in_d;
|
||||
|
||||
always@(posedge clk) begin
|
||||
if (~rst_n) begin
|
||||
data_out <= 1'b0;
|
||||
data_valid <= 0;
|
||||
ready_in_d <= 0;
|
||||
end
|
||||
else begin
|
||||
ready_in_d <= ready_in;
|
||||
if (valid_in & (~data_valid | ready_in_d)) begin
|
||||
data_out <= data_in;
|
||||
data_valid <= 1;
|
||||
end
|
||||
else if (ready_in_d) begin
|
||||
data_valid <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign ready_out = (~data_valid & ~valid_in) | ready_in;
|
||||
assign valid_out = ready_in_d & data_valid;
|
||||
|
||||
|
||||
endmodule
|
||||
51
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG_TEST.v
Normal file
51
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG_TEST.v
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
module STREAM_REG_TEST (
|
||||
input clk,
|
||||
input reset_n,
|
||||
input en_src,
|
||||
input snk_ready,
|
||||
output reg [7:0] src_data,
|
||||
output [7:0] snk_data,
|
||||
output reg [7:0] data_out,
|
||||
output reg src_valid,
|
||||
output reg_valid,
|
||||
output reg_ready
|
||||
);
|
||||
|
||||
always@(posedge clk) begin
|
||||
if (~reset_n) begin
|
||||
src_data <= 8'h0;
|
||||
src_valid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
src_valid <= 1'b0;
|
||||
if (en_src & reg_ready) begin
|
||||
src_data = src_data + 8'h1;
|
||||
src_valid <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
STREAM_REG #(.DATA_WIDTH(8)) SR0 (
|
||||
.clk(clk),
|
||||
.rst_n(reset_n),
|
||||
.ready_out(reg_ready),
|
||||
.valid_out(reg_valid),
|
||||
.data_out(snk_data),
|
||||
.ready_in(snk_ready),
|
||||
.valid_in(src_valid),
|
||||
.data_in(src_data)
|
||||
);
|
||||
|
||||
always@(posedge clk) begin
|
||||
if (~reset_n) begin
|
||||
data_out <= 8'h0;
|
||||
end
|
||||
else begin
|
||||
if (reg_valid) begin
|
||||
data_out <= snk_data;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1010
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG_TEST.vwf
Normal file
1010
Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG_TEST.vwf
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,18 @@
|
|||
ADD_RAM_OUTPUT_REGISTER=OFF
|
||||
INTENDED_DEVICE_FAMILY="MAX 10"
|
||||
LPM_NUMWORDS=256
|
||||
LPM_SHOWAHEAD=OFF
|
||||
LPM_TYPE=scfifo
|
||||
LPM_WIDTH=32
|
||||
LPM_WIDTHU=8
|
||||
OVERFLOW_CHECKING=ON
|
||||
UNDERFLOW_CHECKING=ON
|
||||
USE_EAB=ON
|
||||
DEVICE_FAMILY="MAX 10"
|
||||
clock
|
||||
data
|
||||
rdreq
|
||||
sclr
|
||||
wrreq
|
||||
q
|
||||
usedw
|
||||
56
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/F_VCM.v
Normal file
56
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/F_VCM.v
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
module F_VCM (
|
||||
input RESET_n ,
|
||||
input CLK ,
|
||||
input [ 7:0] SCAL,
|
||||
input [ 7:0] SCAL_F,
|
||||
output [10:0]STEP,
|
||||
input [9:0] STEP_UP ,
|
||||
output reg V_C ,
|
||||
output reg VCM_END ,
|
||||
output reg GO_F
|
||||
|
||||
|
||||
) ;
|
||||
reg [10:0]STEP_i;
|
||||
reg [10:0]STEP_f;
|
||||
|
||||
//parameter SCAL = 8'd10 ;
|
||||
//parameter SCAL_F = 8'd1 ;
|
||||
|
||||
//---step out
|
||||
assign STEP = ( !V_C )? STEP_i :STEP_f ;
|
||||
|
||||
//---------------------------------------initial setting
|
||||
reg [9:0] STP_I ;
|
||||
always @( negedge RESET_n or posedge CLK )
|
||||
begin
|
||||
if (!RESET_n ) begin
|
||||
V_C <=0 ;
|
||||
STEP_i <= 0;
|
||||
end
|
||||
else begin
|
||||
if (STEP_i > 11'h3f0 )
|
||||
V_C <=1 ;
|
||||
else STEP_i <= STEP_i + SCAL ; //10
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//----------------------------------------fine-adjustment
|
||||
always @( negedge V_C or posedge CLK )
|
||||
begin
|
||||
if (!V_C ) begin
|
||||
STEP_f <= STEP_UP- SCAL/2;
|
||||
VCM_END <= 0;
|
||||
GO_F <=0;
|
||||
end
|
||||
else begin
|
||||
GO_F <=1;
|
||||
if (STEP_f > STEP_UP + SCAL/2 )
|
||||
VCM_END <=1 ;
|
||||
else STEP_f <= STEP_f + SCAL_F; //1
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
// --------------------------------------------------------------------
|
||||
// Copyright (c) 2007 by Terasic Technologies Inc.
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Permission:
|
||||
//
|
||||
// Terasic grants permission to use and modify this code for use
|
||||
// in synthesis for all Terasic Development Boards and Altera Development
|
||||
// Kits made by Terasic. Other use of this code, including the selling
|
||||
// ,duplication, or modification of any portion is strictly prohibited.
|
||||
//
|
||||
// Disclaimer:
|
||||
//
|
||||
// This VHDL/Verilog or C/C++ source code is intended as a design reference
|
||||
// which illustrates how these types of functions can be implemented.
|
||||
// It is the user's responsibility to verify their design for
|
||||
// consistency and functionality through the use of formal
|
||||
// verification methods. Terasic provides no warranty regarding the use
|
||||
// or functionality of this code.
|
||||
//
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Terasic Technologies Inc
|
||||
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
|
||||
// HsinChu County, Taiwan
|
||||
// 302
|
||||
//
|
||||
// web: http://www.terasic.com/
|
||||
// email: support@terasic.com
|
||||
//
|
||||
|
||||
|
||||
module I2C_VCM_Config ( // Host Side
|
||||
iCLK,
|
||||
iRST_N,
|
||||
VCM_DATA,
|
||||
ENABLE,
|
||||
END,
|
||||
|
||||
// I2C Side
|
||||
I2C_SCLK,
|
||||
I2C_SDAT
|
||||
);
|
||||
|
||||
// Host Side
|
||||
input iCLK;
|
||||
input iRST_N;
|
||||
input [15:0] VCM_DATA;
|
||||
input ENABLE;
|
||||
output END;
|
||||
|
||||
// I2C Side
|
||||
inout I2C_SCLK;
|
||||
inout I2C_SDAT;
|
||||
|
||||
|
||||
|
||||
// Internal Registers/Wires
|
||||
reg [15:0] mI2C_CLK_DIV;
|
||||
reg [23:0] mI2C_DATA;
|
||||
reg mI2C_CTRL_CLK;
|
||||
reg mI2C_GO;
|
||||
wire mI2C_END;
|
||||
wire mI2C_ACK;
|
||||
reg [3:0] mSetup_ST;
|
||||
wire END;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Clock Setting
|
||||
parameter CLK_Freq = 50_000_000; // 50 MHz
|
||||
parameter I2C_Freq = 100_000; // 100 KHz
|
||||
|
||||
///////////////////// I2C Control Clock ////////////////////////
|
||||
always@(posedge iCLK or negedge iRST_N)
|
||||
begin
|
||||
if(!iRST_N)
|
||||
begin
|
||||
mI2C_CTRL_CLK <= 0;
|
||||
mI2C_CLK_DIV <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if( mI2C_CLK_DIV < (CLK_Freq/I2C_Freq) )
|
||||
mI2C_CLK_DIV <= mI2C_CLK_DIV+1;
|
||||
else
|
||||
begin
|
||||
mI2C_CLK_DIV <= 0;
|
||||
mI2C_CTRL_CLK <= ~mI2C_CTRL_CLK;
|
||||
end
|
||||
end
|
||||
end
|
||||
////////////////////////////////////////////////////////////////////
|
||||
I2C_VCM_Controller u0(
|
||||
.CLOCK(mI2C_CTRL_CLK), // Controller Work Clock
|
||||
.I2C_SCLK(I2C_SCLK), // I2C CLOCK
|
||||
.I2C_SDAT(I2C_SDAT), // I2C DATA
|
||||
.I2C_DATA(mI2C_DATA), // DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
|
||||
.GO(mI2C_GO), // GO transfor
|
||||
.END(mI2C_END), // END transfor
|
||||
.ACK(mI2C_ACK), // ACK
|
||||
.RESET(iRST_N)
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////
|
||||
////////////////////// Config Control ////////////////////////////
|
||||
reg f_trig;
|
||||
reg f_trig_clear;
|
||||
|
||||
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
|
||||
begin
|
||||
if(!iRST_N) f_trig <= 1'b1;
|
||||
else if(f_trig_clear) f_trig <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge mI2C_CTRL_CLK )
|
||||
begin
|
||||
case(mSetup_ST)
|
||||
0: begin
|
||||
mI2C_DATA <= {8'h18,VCM_DATA}; // 0x18 is VCM149C's I2C slave Addr
|
||||
if(ENABLE) begin
|
||||
mSetup_ST <= 1;
|
||||
mI2C_GO <= 1;
|
||||
end
|
||||
else begin
|
||||
mSetup_ST <= 0;
|
||||
mI2C_GO <= 0;
|
||||
end
|
||||
f_trig_clear <= 1'b0;
|
||||
end
|
||||
1: begin
|
||||
if(mI2C_END)
|
||||
begin
|
||||
if(!mI2C_ACK)
|
||||
mSetup_ST <= 2;
|
||||
else
|
||||
mSetup_ST <= 0;
|
||||
mI2C_GO <= 0;
|
||||
end
|
||||
f_trig_clear <= 1'b0;
|
||||
end
|
||||
2: begin
|
||||
if(f_trig) begin
|
||||
mSetup_ST <= 0;
|
||||
f_trig_clear <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
mSetup_ST <= 2;
|
||||
f_trig_clear <= 1'b0;
|
||||
end
|
||||
end
|
||||
default: mSetup_ST <= 0;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
assign END = (mSetup_ST==2);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
// --------------------------------------------------------------------
|
||||
// Copyright (c) 2005 by Terasic Technologies Inc.
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Permission:
|
||||
//
|
||||
// Terasic grants permission to use and modify this code for use
|
||||
// in synthesis for all Terasic Development Boards and Altrea Development
|
||||
// Kits made by Terasic. Other use of this code, including the selling
|
||||
// ,duplication, or modification of any portion is strictly prohibited.
|
||||
//
|
||||
// Disclaimer:
|
||||
//
|
||||
// This VHDL or Verilog source code is intended as a design reference
|
||||
// which illustrates how these types of functions can be implemented.
|
||||
// It is the user's responsibility to verify their design for
|
||||
// consistency and functionality through the use of formal
|
||||
// verification methods. Terasic provides no warranty regarding the use
|
||||
// or functionality of this code.
|
||||
//
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Terasic Technologies Inc
|
||||
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
|
||||
// HsinChu County, Taiwan
|
||||
// 302
|
||||
//
|
||||
// web: http://www.terasic.com/
|
||||
// email: support@terasic.com
|
||||
//
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Major Functions:i2c controller
|
||||
//
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Revision History :
|
||||
// --------------------------------------------------------------------
|
||||
// Ver :| Author :| Mod. Date :| Changes Made:
|
||||
// V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision
|
||||
// --------------------------------------------------------------------
|
||||
|
||||
// Modified for ADDREES + 16 bit data for VCM149C
|
||||
|
||||
module I2C_VCM_Controller (
|
||||
CLOCK,
|
||||
I2C_SCLK,//I2C CLOCK
|
||||
I2C_SDAT,//I2C DATA
|
||||
I2C_DATA,//DATA:[SLAVE_ADDR,DATA16]
|
||||
GO, //GO transfor
|
||||
END, //END transfor
|
||||
ACK, //ACK
|
||||
RESET
|
||||
);
|
||||
input CLOCK;
|
||||
input [23:0]I2C_DATA;
|
||||
input GO;
|
||||
input RESET;
|
||||
inout I2C_SDAT;
|
||||
inout I2C_SCLK;
|
||||
output END;
|
||||
output ACK;
|
||||
|
||||
|
||||
reg SDO;
|
||||
reg SCLK;
|
||||
reg END;
|
||||
reg [23:0]SD;
|
||||
reg [6:0]SD_COUNTER;
|
||||
|
||||
wire wI2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=30))? ~CLOCK :0 );
|
||||
wire I2C_SCLK=wI2C_SCLK?1'bz:0; // inout SCLK
|
||||
wire I2C_SDAT=SDO?1'bz:0 ;
|
||||
|
||||
reg ACK1,ACK2,ACK3,ACK4;
|
||||
wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
|
||||
|
||||
//--I2C COUNTER
|
||||
always @(negedge RESET or posedge CLOCK ) begin
|
||||
if (!RESET) SD_COUNTER=6'b111111;
|
||||
else begin
|
||||
if (GO==0)
|
||||
SD_COUNTER=0;
|
||||
else
|
||||
if (SD_COUNTER < 32) SD_COUNTER=SD_COUNTER+1;
|
||||
end
|
||||
end
|
||||
//----
|
||||
|
||||
always @(negedge RESET or posedge CLOCK ) begin
|
||||
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
|
||||
else
|
||||
case (SD_COUNTER)
|
||||
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
|
||||
//start
|
||||
6'd1 : begin SD=I2C_DATA;SDO=0;end
|
||||
6'd2 : SCLK=0;
|
||||
//SLAVE ADDR
|
||||
6'd3 : SDO=SD[23];
|
||||
6'd4 : SDO=SD[22];
|
||||
6'd5 : SDO=SD[21];
|
||||
6'd6 : SDO=SD[20];
|
||||
6'd7 : SDO=SD[19];
|
||||
6'd8 : SDO=SD[18];
|
||||
6'd9 : SDO=SD[17];
|
||||
6'd10 : SDO=SD[16];
|
||||
6'd11 : SDO=1'b1;//ACK
|
||||
|
||||
//MSB
|
||||
6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
|
||||
6'd13 : SDO=SD[14];
|
||||
6'd14 : SDO=SD[13];
|
||||
6'd15 : SDO=SD[12];
|
||||
6'd16 : SDO=SD[11];
|
||||
6'd17 : SDO=SD[10];
|
||||
6'd18 : SDO=SD[9];
|
||||
6'd19 : SDO=SD[8];
|
||||
6'd20 : SDO=1'b1;//ACK
|
||||
|
||||
//LSB
|
||||
6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
|
||||
6'd22 : SDO=SD[6];
|
||||
6'd23 : SDO=SD[5];
|
||||
6'd24 : SDO=SD[4];
|
||||
6'd25 : SDO=SD[3];
|
||||
6'd26 : SDO=SD[2];
|
||||
6'd27 : SDO=SD[1];
|
||||
6'd28 : SDO=SD[0];
|
||||
6'd29 : SDO=1'b1;//ACK
|
||||
|
||||
//stop
|
||||
6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK4=I2C_SDAT; end
|
||||
6'd31 : SCLK=1'b1;
|
||||
6'd32 : begin SDO=1'b1; END=1; end
|
||||
|
||||
// //DATA
|
||||
// 6'd30 : begin SDO=SD[7]; ACK3=I2C_SDAT; end
|
||||
// 6'd31 : SDO=SD[6];
|
||||
// 6'd32 : SDO=SD[5];
|
||||
// 6'd33 : SDO=SD[4];
|
||||
// 6'd34 : SDO=SD[3];
|
||||
// 6'd35 : SDO=SD[2];
|
||||
// 6'd36 : SDO=SD[1];
|
||||
// 6'd37 : SDO=SD[0];
|
||||
// 6'd38 : SDO=1'b1;//ACK
|
||||
|
||||
// //stop
|
||||
// 6'd39 : begin SDO=1'b0; SCLK=1'b0; ACK4=I2C_SDAT; end
|
||||
// 6'd40 : SCLK=1'b1;
|
||||
// 6'd41 : begin SDO=1'b1; END=1; end
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
// focus function coding by Joe
|
||||
// focus ip packaged by Dee
|
||||
|
||||
module TERASIC_AUTO_FOCUS(
|
||||
// global clock & reset
|
||||
clk,
|
||||
reset_n,
|
||||
|
||||
// mm slave
|
||||
s_chipselect,
|
||||
s_read,
|
||||
s_write,
|
||||
s_readdata,
|
||||
s_writedata,
|
||||
s_address,
|
||||
|
||||
// stream sink
|
||||
sink_data,
|
||||
sink_valid,
|
||||
sink_ready,
|
||||
sink_sop,
|
||||
sink_eop,
|
||||
|
||||
// streaming source
|
||||
source_data,
|
||||
source_valid,
|
||||
source_ready,
|
||||
source_sop,
|
||||
source_eop,
|
||||
|
||||
// conduit // i2c master
|
||||
clk50,
|
||||
vcm_i2c_scl,
|
||||
vcm_i2c_sda
|
||||
|
||||
);
|
||||
|
||||
|
||||
// global clock & reset
|
||||
input clk;
|
||||
input reset_n;
|
||||
|
||||
// mm slave
|
||||
input s_chipselect;
|
||||
input s_read;
|
||||
input s_write;
|
||||
output reg [31:0] s_readdata;
|
||||
input [31:0] s_writedata;
|
||||
input [2:0] s_address;
|
||||
|
||||
|
||||
// streaming sink
|
||||
input [23:0] sink_data;
|
||||
input sink_valid;
|
||||
output sink_ready;
|
||||
input sink_sop;
|
||||
input sink_eop;
|
||||
|
||||
// streaming source
|
||||
output [23:0] source_data;
|
||||
output source_valid;
|
||||
input source_ready;
|
||||
output source_sop;
|
||||
output source_eop;
|
||||
|
||||
// conduit export
|
||||
input clk50;
|
||||
inout vcm_i2c_scl;
|
||||
inout vcm_i2c_sda;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
parameter VIDEO_W = 800,
|
||||
VIDEO_H = 480;
|
||||
|
||||
localparam FOCUS_FULL_VIDEO_MODE = 1'b0,
|
||||
FOCUS_WINDOW_VIDEO_MODE = 1'b1;
|
||||
|
||||
reg process_start /*synthesis noprune*/;
|
||||
reg focus_mode /*synthesis noprune*/;
|
||||
|
||||
reg [11:0] focus_active_w /*synthesis noprune*/;
|
||||
reg [11:0] focus_active_h /*synthesis noprune*/;
|
||||
reg [11:0] focus_active_x_start /*synthesis noprune*/;
|
||||
reg [11:0] focus_active_y_start /*synthesis noprune*/;
|
||||
|
||||
reg [11:0] x_cnt /*synthesis noprune*/;
|
||||
reg [11:0] y_cnt /*synthesis noprune*/;
|
||||
reg [7:0] scal;
|
||||
reg [7:0] scal_f;
|
||||
reg [7:0] th;
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// coding
|
||||
|
||||
// connnect sink & source direct
|
||||
assign source_data = (vcm_en & focus_mode & focus_window_border )?{8'h7f, 8'h7f, 8'h0}:sink_data;
|
||||
assign source_valid = sink_valid;
|
||||
assign sink_ready = source_ready;
|
||||
assign source_sop = sink_sop;
|
||||
assign source_eop = sink_eop;
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////
|
||||
/// command from mm master /////
|
||||
/////////////////////////////////
|
||||
|
||||
// write
|
||||
`define REG_GO 0
|
||||
`define REG_CTRL 1
|
||||
`define REG_FOCUS_W 2
|
||||
`define REG_FOCUS_H 3
|
||||
`define REG_FOCUS_X_START 4
|
||||
`define REG_FOCUS_Y_START 5
|
||||
`define REG_SCAL 6 // scan 0 -> 1023 , step: SCAL , to find STEP_UP
|
||||
// scan STEP_UP + - SCAL/2 , step: SCAL_F
|
||||
`define REG_TH 7
|
||||
|
||||
// read
|
||||
`define REG_STATUS 0
|
||||
//`define REG_SUM 1
|
||||
|
||||
|
||||
// mm mater write
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (~reset_n)
|
||||
begin
|
||||
process_start <= 1'b0;
|
||||
focus_mode <= FOCUS_FULL_VIDEO_MODE;
|
||||
|
||||
focus_active_w <= 12'd200;
|
||||
focus_active_h <= 12'd120;
|
||||
focus_active_x_start <= 12'd300;
|
||||
focus_active_y_start <= 12'd180;
|
||||
|
||||
scal <= 8'd10;
|
||||
scal_f <= 8'd1;
|
||||
|
||||
th <= 8'd5;
|
||||
end
|
||||
else begin
|
||||
if(s_chipselect & s_write) begin
|
||||
if (s_address == `REG_GO) process_start <= s_writedata[0];
|
||||
else if (s_address == `REG_CTRL) focus_mode <= s_writedata[0];// FOCUS_WINDOW_VIDEO_MODE settings if not full-screen mode
|
||||
else if (s_address == `REG_FOCUS_W) focus_active_w <= s_writedata[11:0];
|
||||
else if (s_address == `REG_FOCUS_H) focus_active_h <= s_writedata[11:0];
|
||||
else if (s_address == `REG_FOCUS_X_START) focus_active_x_start <= s_writedata[11:0];
|
||||
else if (s_address == `REG_FOCUS_Y_START) focus_active_y_start <= s_writedata[11:0];
|
||||
else if (s_address == `REG_SCAL) begin scal <= s_writedata[15:8];
|
||||
scal_f <= s_writedata[7:0];
|
||||
end
|
||||
else if (s_address == `REG_TH) th <= s_writedata[7:0];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
// mm mater read
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
if (~reset_n)
|
||||
s_readdata <= {16'b0,1'b1,15'b0};
|
||||
else if (s_chipselect & s_read)
|
||||
begin
|
||||
if (s_address == `REG_STATUS) s_readdata <= {16'b0,status};
|
||||
// else if (s_address == `REG_SUM) s_readdata <= sum;
|
||||
end
|
||||
end
|
||||
|
||||
/////////////////////////////////
|
||||
// remember previus 'process_start' status
|
||||
reg pre_process_start;
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
if (~reset_n) pre_process_start <= 1'b1;
|
||||
else pre_process_start <= process_start;
|
||||
|
||||
|
||||
wire process_start_tiggle;
|
||||
assign process_start_tiggle = (~pre_process_start & process_start)?1'b1:1'b0;
|
||||
|
||||
|
||||
////////////////////////////////////
|
||||
////////////////////////////////////
|
||||
// process kernel
|
||||
////////////////////////////////////
|
||||
////////////////////////////////////
|
||||
|
||||
wire focus_window_area /*synthesis keep*/;
|
||||
wire focus_window_border /*synthesis keep*/;
|
||||
|
||||
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n) begin
|
||||
x_cnt <= 12'd0;
|
||||
y_cnt <= 12'd0;
|
||||
end
|
||||
else if(sink_sop) begin
|
||||
x_cnt <= 12'd0;
|
||||
y_cnt <= 12'd0;
|
||||
end
|
||||
else if(sink_valid) begin
|
||||
if(x_cnt == VIDEO_W - 1'b1) begin
|
||||
x_cnt <= 12'd0;
|
||||
y_cnt <= y_cnt + 1'b1;
|
||||
end else x_cnt <= x_cnt + 1'b1;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
assign focus_window_area = ( x_cnt >= focus_active_x_start
|
||||
&& x_cnt <= (focus_active_x_start + focus_active_w)
|
||||
&& y_cnt >= focus_active_y_start
|
||||
&& y_cnt <= (focus_active_y_start + focus_active_h)
|
||||
)?1'b1:1'b0;
|
||||
|
||||
assign focus_window_border = (( x_cnt == focus_active_x_start
|
||||
|| x_cnt == (focus_active_x_start + focus_active_w)
|
||||
|| y_cnt == focus_active_y_start
|
||||
|| y_cnt == (focus_active_y_start + focus_active_h)
|
||||
) && focus_window_area) ?1'b1:1'b0;
|
||||
|
||||
/////////////////////////////////////////////////
|
||||
// VCM enable
|
||||
reg vcm_en;
|
||||
reg [1:0] vcm_en_delay_cnt;
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n) begin
|
||||
vcm_en <= 1'b0;
|
||||
vcm_en_delay_cnt <= 2'd0;
|
||||
end
|
||||
else if(process_start_tiggle) begin
|
||||
vcm_en <= 1'b1;
|
||||
vcm_en_delay_cnt <= 2'd0;
|
||||
end
|
||||
else if(VCM_END & sink_eop ) begin
|
||||
if(vcm_en_delay_cnt == 2'd3) vcm_en <= 1'b0;// or delay x frame?
|
||||
else vcm_en_delay_cnt <= vcm_en_delay_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
//----VCM_STEP CONTROL & PIXEL HIGH_Statistics
|
||||
|
||||
VCM_CTRL_P vcm_ctrl(
|
||||
.iR (sink_data[23:16]), // RGB sequence must the same as the LCD side(final RGB sequence)
|
||||
.iG (sink_data[15: 8]),
|
||||
.iB (sink_data[ 7: 0]),
|
||||
.VS (sink_sop & sink_valid),// VS_
|
||||
|
||||
.SCAL(scal),
|
||||
.SCAL_F(scal_f),
|
||||
.TH(th),
|
||||
.ACTIV_C (focus_window_area & sink_valid) , // focus-window area
|
||||
.ACTIV_V (sink_valid) , // full-screen
|
||||
|
||||
.VIDEO_CLK ( clk ),
|
||||
.AUTO_FOC ( ~process_start_tiggle ), // focus trigger
|
||||
.SW_FUC_ALL_CEN( focus_mode) ,//
|
||||
.VCM_END ( VCM_END) ,
|
||||
.Y ( Y ),
|
||||
.S (S ),
|
||||
.END_STEP (END_STEP ),
|
||||
.VCM_DATA (VCM_DATA ),
|
||||
.SUM(sum)
|
||||
|
||||
);//
|
||||
wire [15:0] VCM_DATA ;
|
||||
wire [9:0] END_STEP ;
|
||||
wire VCM_END ;
|
||||
wire [7:0] S ;
|
||||
wire [17:0] Y ;
|
||||
//-----
|
||||
wire [15:0] status;
|
||||
wire [31:0] sum;
|
||||
assign status = { ~vcm_en,5'b0,END_STEP} ;
|
||||
|
||||
|
||||
|
||||
I2C_VCM_Config vcm_i2c(
|
||||
.iCLK(clk50),//clk_50
|
||||
.ENABLE(vcm_en), // enable
|
||||
.iRST_N(~sink_eop), // trigger
|
||||
.VCM_DATA(VCM_DATA),
|
||||
.END(),//vcm_i2c_end
|
||||
|
||||
.I2C_SCLK(vcm_i2c_scl),
|
||||
.I2C_SDAT(vcm_i2c_sda)
|
||||
);
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
# TCL File Generated by Component Editor 14.0
|
||||
# Thu Dec 31 11:58:49 CST 2015
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
#
|
||||
# TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS" v1.0
|
||||
# Dee Zeng 2015.12.31.11:58:49
|
||||
# auto focus simple fuction
|
||||
#
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 14.0
|
||||
#
|
||||
package require -exact qsys 14.0
|
||||
|
||||
|
||||
#
|
||||
# module TERASIC_AUTO_FOCUS
|
||||
#
|
||||
set_module_property DESCRIPTION "auto focus simple fuction"
|
||||
set_module_property NAME TERASIC_AUTO_FOCUS
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property GROUP "Terasic Technologies Inc"
|
||||
set_module_property AUTHOR "Dee Zeng"
|
||||
set_module_property DISPLAY_NAME TERASIC_AUTO_FOCUS
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
set_module_property REPORT_HIERARCHY false
|
||||
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
|
||||
set_fileset_property QUARTUS_SYNTH TOP_LEVEL TERASIC_AUTO_FOCUS
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file F_VCM.v VERILOG PATH F_VCM.v
|
||||
add_fileset_file I2C_VCM_Config.v VERILOG PATH I2C_VCM_Config.v
|
||||
add_fileset_file I2C_VCM_Controller.v VERILOG PATH I2C_VCM_Controller.v
|
||||
add_fileset_file TERASIC_AUTO_FOCUS.v VERILOG PATH TERASIC_AUTO_FOCUS.v TOP_LEVEL_FILE
|
||||
add_fileset_file VCM_CTRL_P.v VERILOG PATH VCM_CTRL_P.v
|
||||
|
||||
add_fileset SIM_VERILOG SIM_VERILOG "" ""
|
||||
set_fileset_property SIM_VERILOG TOP_LEVEL TERASIC_AUTO_FOCUS
|
||||
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
|
||||
add_fileset_file F_VCM.v VERILOG PATH F_VCM.v
|
||||
add_fileset_file I2C_VCM_Config.v VERILOG PATH I2C_VCM_Config.v
|
||||
add_fileset_file I2C_VCM_Controller.v VERILOG PATH I2C_VCM_Controller.v
|
||||
add_fileset_file TERASIC_AUTO_FOCUS.v VERILOG PATH TERASIC_AUTO_FOCUS.v
|
||||
add_fileset_file VCM_CTRL_P.v VERILOG PATH VCM_CTRL_P.v
|
||||
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
add_parameter VIDEO_W INTEGER 800
|
||||
set_parameter_property VIDEO_W DEFAULT_VALUE 800
|
||||
set_parameter_property VIDEO_W DISPLAY_NAME VIDEO_W
|
||||
set_parameter_property VIDEO_W TYPE INTEGER
|
||||
set_parameter_property VIDEO_W UNITS None
|
||||
set_parameter_property VIDEO_W ALLOWED_RANGES -2147483648:2147483647
|
||||
set_parameter_property VIDEO_W HDL_PARAMETER true
|
||||
add_parameter VIDEO_H INTEGER 480
|
||||
set_parameter_property VIDEO_H DEFAULT_VALUE 480
|
||||
set_parameter_property VIDEO_H DISPLAY_NAME VIDEO_H
|
||||
set_parameter_property VIDEO_H TYPE INTEGER
|
||||
set_parameter_property VIDEO_H UNITS None
|
||||
set_parameter_property VIDEO_H ALLOWED_RANGES -2147483648:2147483647
|
||||
set_parameter_property VIDEO_H HDL_PARAMETER true
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point clock
|
||||
#
|
||||
add_interface clock clock end
|
||||
set_interface_property clock clockRate 0
|
||||
set_interface_property clock ENABLED true
|
||||
set_interface_property clock EXPORT_OF ""
|
||||
set_interface_property clock PORT_NAME_MAP ""
|
||||
set_interface_property clock CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property clock SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point reset
|
||||
#
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
set_interface_property reset ENABLED true
|
||||
set_interface_property reset EXPORT_OF ""
|
||||
set_interface_property reset PORT_NAME_MAP ""
|
||||
set_interface_property reset CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property reset SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port reset reset_n reset_n Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point mm_ctrl
|
||||
#
|
||||
add_interface mm_ctrl avalon end
|
||||
set_interface_property mm_ctrl addressUnits WORDS
|
||||
set_interface_property mm_ctrl associatedClock clock
|
||||
set_interface_property mm_ctrl associatedReset reset
|
||||
set_interface_property mm_ctrl bitsPerSymbol 8
|
||||
set_interface_property mm_ctrl burstOnBurstBoundariesOnly false
|
||||
set_interface_property mm_ctrl burstcountUnits WORDS
|
||||
set_interface_property mm_ctrl explicitAddressSpan 0
|
||||
set_interface_property mm_ctrl holdTime 0
|
||||
set_interface_property mm_ctrl linewrapBursts false
|
||||
set_interface_property mm_ctrl maximumPendingReadTransactions 0
|
||||
set_interface_property mm_ctrl maximumPendingWriteTransactions 0
|
||||
set_interface_property mm_ctrl readLatency 0
|
||||
set_interface_property mm_ctrl readWaitTime 1
|
||||
set_interface_property mm_ctrl setupTime 0
|
||||
set_interface_property mm_ctrl timingUnits Cycles
|
||||
set_interface_property mm_ctrl writeWaitTime 0
|
||||
set_interface_property mm_ctrl ENABLED true
|
||||
set_interface_property mm_ctrl EXPORT_OF ""
|
||||
set_interface_property mm_ctrl PORT_NAME_MAP ""
|
||||
set_interface_property mm_ctrl CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property mm_ctrl SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port mm_ctrl s_chipselect chipselect Input 1
|
||||
add_interface_port mm_ctrl s_read read Input 1
|
||||
add_interface_port mm_ctrl s_write write Input 1
|
||||
add_interface_port mm_ctrl s_readdata readdata Output 32
|
||||
add_interface_port mm_ctrl s_writedata writedata Input 32
|
||||
add_interface_port mm_ctrl s_address address Input 3
|
||||
set_interface_assignment mm_ctrl embeddedsw.configuration.isFlash 0
|
||||
set_interface_assignment mm_ctrl embeddedsw.configuration.isMemoryDevice 0
|
||||
set_interface_assignment mm_ctrl embeddedsw.configuration.isNonVolatileStorage 0
|
||||
set_interface_assignment mm_ctrl embeddedsw.configuration.isPrintableDevice 0
|
||||
|
||||
|
||||
#
|
||||
# connection point din
|
||||
#
|
||||
add_interface din avalon_streaming end
|
||||
set_interface_property din associatedClock clock
|
||||
set_interface_property din associatedReset reset
|
||||
set_interface_property din dataBitsPerSymbol 8
|
||||
set_interface_property din errorDescriptor ""
|
||||
set_interface_property din firstSymbolInHighOrderBits true
|
||||
set_interface_property din maxChannel 0
|
||||
set_interface_property din readyLatency 1
|
||||
set_interface_property din ENABLED true
|
||||
set_interface_property din EXPORT_OF ""
|
||||
set_interface_property din PORT_NAME_MAP ""
|
||||
set_interface_property din CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property din SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port din sink_data data Input 24
|
||||
add_interface_port din sink_valid valid Input 1
|
||||
add_interface_port din sink_ready ready Output 1
|
||||
add_interface_port din sink_sop startofpacket Input 1
|
||||
add_interface_port din sink_eop endofpacket Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point dout
|
||||
#
|
||||
add_interface dout avalon_streaming start
|
||||
set_interface_property dout associatedClock clock
|
||||
set_interface_property dout associatedReset reset
|
||||
set_interface_property dout dataBitsPerSymbol 8
|
||||
set_interface_property dout errorDescriptor ""
|
||||
set_interface_property dout firstSymbolInHighOrderBits true
|
||||
set_interface_property dout maxChannel 0
|
||||
set_interface_property dout readyLatency 1
|
||||
set_interface_property dout ENABLED true
|
||||
set_interface_property dout EXPORT_OF ""
|
||||
set_interface_property dout PORT_NAME_MAP ""
|
||||
set_interface_property dout CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property dout SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port dout source_data data Output 24
|
||||
add_interface_port dout source_valid valid Output 1
|
||||
add_interface_port dout source_ready ready Input 1
|
||||
add_interface_port dout source_sop startofpacket Output 1
|
||||
add_interface_port dout source_eop endofpacket Output 1
|
||||
|
||||
|
||||
#
|
||||
# connection point Conduit
|
||||
#
|
||||
add_interface Conduit conduit end
|
||||
set_interface_property Conduit associatedClock clock
|
||||
set_interface_property Conduit associatedReset reset
|
||||
set_interface_property Conduit ENABLED true
|
||||
set_interface_property Conduit EXPORT_OF ""
|
||||
set_interface_property Conduit PORT_NAME_MAP ""
|
||||
set_interface_property Conduit CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property Conduit SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port Conduit vcm_i2c_sda vcm_i2c_sda Bidir 1
|
||||
add_interface_port Conduit clk50 clk50 Input 1
|
||||
add_interface_port Conduit vcm_i2c_scl vcm_i2c_scl Bidir 1
|
||||
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
module VCM_CTRL_P (
|
||||
input [ 7:0] iR,
|
||||
input [ 7:0] iG,
|
||||
input [ 7:0] iB,
|
||||
input VS,// VS_
|
||||
|
||||
input [ 7:0] SCAL,
|
||||
input [ 7:0] SCAL_F,
|
||||
input [ 7:0] TH,
|
||||
|
||||
input ACTIV_C ,
|
||||
input ACTIV_V ,
|
||||
|
||||
input VIDEO_CLK ,
|
||||
input AUTO_FOC ,
|
||||
input SW_FUC_ALL_CEN ,
|
||||
output VCM_END,
|
||||
output [17:0] Y ,
|
||||
output reg [7:0] SS ,
|
||||
output reg [7:0] S,
|
||||
output [9:0] END_STEP ,
|
||||
output [15:0] VCM_DATA,
|
||||
output reg[31:0] SUM
|
||||
);//
|
||||
|
||||
|
||||
// Y = R * //.299 = 256 * 0.299 = 77 // + G * // .587 = 256 * .587 = 150 //+ B * //.114 = 256 * .114 = 29
|
||||
//---RGB2Y---
|
||||
assign Y = iR * 77 + iG *150 + iB*29 ;
|
||||
//----------------------------
|
||||
|
||||
reg [7:0] rY1 , rY2;
|
||||
wire [7:0] Y1;
|
||||
|
||||
|
||||
reg [31:0] rSUM;
|
||||
reg [31:0] peakSUM;
|
||||
|
||||
|
||||
reg rVS ;
|
||||
reg rCH ;
|
||||
|
||||
//assign TH=5 ;
|
||||
assign Y1[7:0] = Y[15:8] ;
|
||||
|
||||
//--
|
||||
always @( posedge VIDEO_CLK or negedge AUTO_FOC) begin
|
||||
if ( !AUTO_FOC ) begin
|
||||
peakSUM <=0;
|
||||
end
|
||||
else begin
|
||||
|
||||
{ rY2, rY1} <= { rY1 ,Y1 } ;
|
||||
rVS <= VS ;
|
||||
S <= ( SS > TH )? 8'hff: 0 ;
|
||||
|
||||
|
||||
if ( !rVS && VS ) begin
|
||||
rGO_F <= GO_F;
|
||||
|
||||
{ SUM , rSUM } <= { rSUM,32'h0 } ;
|
||||
//if ( ( !AUTO_FOC ) || ( ~rGO_F & GO_F ) ) peakSUM <=0;
|
||||
if ( ~rGO_F & GO_F ) peakSUM <=0;
|
||||
else if (( peakSUM < SUM ) && (!VCM_END)) begin peakSUM <= SUM ; STEP_UP <= STEP; end
|
||||
end
|
||||
else if ( ( SS > TH ) && ( (SW_FUC_ALL_CEN)? ACTIV_C : ACTIV_V ) ) rSUM <= rSUM+1 ;
|
||||
|
||||
//--DIFF Y1-Y2-Y3
|
||||
if ( Y1 >rY2 ) SS<= (Y1 - rY2 ) ;
|
||||
else SS <= (rY2 - Y1 ) ;
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
//-------------------VCM STEP ---
|
||||
|
||||
reg [9:0] STEP_UP ;
|
||||
wire [9:0] STEP ;
|
||||
wire V_C ;
|
||||
|
||||
assign END_STEP = ( VCM_END )? STEP_UP[9:0] : STEP[9:0];
|
||||
assign VCM_DATA = {2'b00, END_STEP[9:0] ,4'b1111 }; //
|
||||
wire GO_F ;
|
||||
reg rGO_F ;
|
||||
F_VCM f(
|
||||
.RESET_n( AUTO_FOC ),
|
||||
.CLK ( VS ),
|
||||
.SCAL(SCAL),
|
||||
.SCAL_F(SCAL_F),
|
||||
.STEP( STEP),
|
||||
.STEP_UP ( STEP_UP) ,
|
||||
.V_C ( V_C),
|
||||
.GO_F ( GO_F) ,
|
||||
.VCM_END (VCM_END )
|
||||
) ;
|
||||
|
||||
endmodule
|
||||
|
||||
294
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer2RGB.v
Normal file
294
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer2RGB.v
Normal file
|
|
@ -0,0 +1,294 @@
|
|||
/* Bayer Pattern
|
||||
|
||||
-> G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
...............
|
||||
...............
|
||||
G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
|
||||
|
||||
// matrix
|
||||
[0] [1] [2]
|
||||
[3] [4] [5]
|
||||
[6] [7] [8]
|
||||
|
||||
|
||||
*/
|
||||
|
||||
`define GREEN_AVG_4
|
||||
|
||||
module Bayer2RGB(
|
||||
reset_n,
|
||||
|
||||
BAYER_CLK,
|
||||
BAYER_X,
|
||||
BAYER_Y,
|
||||
BAYER_DATA,
|
||||
BAYER_VALID,
|
||||
BAYER_WIDTH,
|
||||
BAYER_HEIGHT,
|
||||
|
||||
RGB_R,
|
||||
RGB_G,
|
||||
RGB_B,
|
||||
RGB_X,
|
||||
RGB_Y,
|
||||
RGB_VALID,
|
||||
RGB_FRAME_COUNT
|
||||
|
||||
);
|
||||
|
||||
|
||||
parameter VIDEO_W = 800;
|
||||
parameter VIDEO_H = 600;
|
||||
|
||||
input reset_n;
|
||||
|
||||
input BAYER_CLK;
|
||||
input [11:0] BAYER_X;
|
||||
input [11:0] BAYER_Y;
|
||||
input [11:0] BAYER_DATA;
|
||||
input BAYER_VALID;
|
||||
input [11:0] BAYER_WIDTH;
|
||||
input [11:0] BAYER_HEIGHT;
|
||||
|
||||
output reg [11:0] RGB_R;
|
||||
output reg [11:0] RGB_G;
|
||||
output reg [11:0] RGB_B;
|
||||
output reg [11:0] RGB_X;
|
||||
output reg [11:0] RGB_Y;
|
||||
output reg RGB_VALID;
|
||||
output reg [19:0] RGB_FRAME_COUNT;
|
||||
|
||||
|
||||
////////////////////////////////////
|
||||
// push into Bayer_LineBuffer
|
||||
wire [11:0] LD0, LD1, LD2;
|
||||
|
||||
|
||||
|
||||
Bayer_LineBuffer#(
|
||||
.VIDEO_W(VIDEO_W)
|
||||
) Bayer_LineBuffer_Inst(
|
||||
.aclr(~reset_n),
|
||||
.clken(BAYER_VALID),
|
||||
.clock(BAYER_CLK),
|
||||
.shiftin(BAYER_DATA),
|
||||
.shiftout(),
|
||||
.taps({LD0, LD1, LD2}) // msb is first data
|
||||
);
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////
|
||||
// RGB_X, RGB_Y
|
||||
|
||||
always @ (posedge BAYER_CLK)
|
||||
begin
|
||||
RGB_X <= BAYER_X;
|
||||
RGB_Y <= BAYER_Y;
|
||||
RGB_VALID <= BAYER_VALID;
|
||||
end
|
||||
|
||||
reg [13:0] D[8:0];
|
||||
|
||||
always @ (posedge BAYER_CLK)
|
||||
begin
|
||||
D[2] <= LD0;
|
||||
D[1] <= D[2];
|
||||
D[0] <= D[1];
|
||||
//
|
||||
D[5] <= LD1;
|
||||
D[4] <= D[5];
|
||||
D[3] <= D[4];
|
||||
//
|
||||
D[8] <= LD2;
|
||||
D[7] <= D[8];
|
||||
D[6] <= D[7];
|
||||
//
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////
|
||||
|
||||
wire [1:0] bayer_case;
|
||||
////assign bayer_case = USER_CTRL?{~BAYER_Y[0], ~BAYER_X[0]}:{BAYER_Y[0], BAYER_X[0]}; // col & row inverse
|
||||
//assign bayer_case = {BAYER_Y[0], BAYER_X[0]};
|
||||
assign bayer_case = {~BAYER_Y[0], BAYER_X[0]}; // col & row inverse
|
||||
|
||||
//assign bayer_case = {BAYER_Y[0], ~BAYER_X[0]}; // richard try
|
||||
|
||||
|
||||
wire [13:0] avg1_sum, avg2_sum;
|
||||
wire [12:0] avg3_sum, avg4_sum;
|
||||
wire [11:0] avg0, avg1, avg2, avg3, avg4;
|
||||
|
||||
|
||||
add4 add4_avg1(
|
||||
.data0x(D[1]),
|
||||
.data1x(D[3]),
|
||||
.data2x(D[5]),
|
||||
.data3x(D[7]),
|
||||
.result(avg1_sum));
|
||||
|
||||
assign avg1 = avg1_sum[13:2];// >> 2; //(D[1]+D[3]+D[5]+D[7]) >> 2;
|
||||
|
||||
|
||||
add4 add4_avg2(
|
||||
.data0x(D[0]),
|
||||
.data1x(D[2]),
|
||||
.data2x(D[6]),
|
||||
.data3x(D[8]),
|
||||
.result(avg2_sum));
|
||||
|
||||
assign avg2 = avg2_sum[13:2];// >> 2; //(D[0]+D[2]+D[6]+D[8]) >> 2;
|
||||
|
||||
add2 add2_avg3(
|
||||
.data0x(D[1]),
|
||||
.data1x(D[7]),
|
||||
.result(avg3_sum));
|
||||
|
||||
assign avg3 = avg3_sum[12:1];// >> 1; //(D[1]+D[7]) >> 1;
|
||||
|
||||
add2 add2_avg4(
|
||||
.data0x(D[3]),
|
||||
.data1x(D[5]),
|
||||
.result(avg4_sum));
|
||||
|
||||
assign avg4 = avg4_sum[12:1];// >> 1; //(D[3]+D[5]) >> 1;
|
||||
|
||||
assign avg0 = D[4];
|
||||
|
||||
|
||||
reg in_rgb_active_area;
|
||||
|
||||
always @ (posedge BAYER_CLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
in_rgb_active_area <= 1'b0;
|
||||
else if ((BAYER_X >=3) && (BAYER_Y >=5) && ((BAYER_X+3) < VIDEO_W) && ((BAYER_Y+3) < VIDEO_H))
|
||||
in_rgb_active_area <= 1'b1;
|
||||
else
|
||||
in_rgb_active_area <= 1'b0;
|
||||
end
|
||||
|
||||
reg xfer_rgb_data;
|
||||
always @ (posedge BAYER_CLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
xfer_rgb_data <= 1'b0;
|
||||
else
|
||||
xfer_rgb_data <= BAYER_VALID;
|
||||
end
|
||||
|
||||
//Interpolating the green component
|
||||
//http://www.siliconimaging.com/RGB%20Bayer.htm
|
||||
/*
|
||||
-> G1, R, G1, R, G1, R, ....
|
||||
B, G2, B, G2, B, G2, ....
|
||||
G1, R, G1, R, G1, R, ....
|
||||
B, G2, B, G2, B, G2, ....
|
||||
G1, R, G1, R, G1, R, ....
|
||||
B, G2, B, G2, B, G2, ....
|
||||
*/
|
||||
always @ (posedge BAYER_CLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
RGB_G <= 0;
|
||||
else if (xfer_rgb_data & in_rgb_active_area)
|
||||
begin
|
||||
if (bayer_case == 2'b01 || bayer_case == 2'b10)
|
||||
begin
|
||||
RGB_G <= avg1;
|
||||
end
|
||||
else
|
||||
RGB_G <= avg0;//D[12];
|
||||
end
|
||||
else
|
||||
RGB_G <= 0;
|
||||
|
||||
end
|
||||
|
||||
//Interpolating red and blue components
|
||||
//http://www.siliconimaging.com/RGB%20Bayer.htm
|
||||
/*
|
||||
-> G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
G1, R, G1, R, ....
|
||||
B, G2, B, G2, ....
|
||||
*/
|
||||
always @ (posedge BAYER_CLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
begin
|
||||
RGB_B <= 0;
|
||||
RGB_R <= 0;
|
||||
end
|
||||
else if (xfer_rgb_data & in_rgb_active_area)
|
||||
begin
|
||||
if (bayer_case == 2'b00)
|
||||
begin // case (a)
|
||||
RGB_R <= avg3;//(D[7]+D[17]) >> 1;
|
||||
RGB_B <= avg4;//(D[11]+D[13]) >> 1;
|
||||
end
|
||||
else if (bayer_case == 2'b01)
|
||||
begin // case (c)
|
||||
RGB_B <= avg0;//D[12];
|
||||
RGB_R <= avg2;//(D[6]+D[8]+D[16]+D[18]) >> 2;
|
||||
end
|
||||
else if (bayer_case == 2'b10)
|
||||
begin // case (d)
|
||||
RGB_R <= avg0;// D[12];
|
||||
RGB_B <= avg2;//(D[6]+D[8]+D[16]+D[18]) >> 2;
|
||||
end
|
||||
else if (bayer_case == 2'b11)
|
||||
begin // case (b)
|
||||
RGB_B <= avg3;//(D[7]+D[17]) >> 1;
|
||||
RGB_R <= avg4;//(D[11]+D[13]) >> 1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
RGB_B <= 0;
|
||||
RGB_R <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
wire FirstPixel, LastPixel;
|
||||
assign FirstPixel = (RGB_X == 0 && RGB_Y == 0)?1'b1:1'b0;
|
||||
assign LastPixel = (RGB_X+1 == VIDEO_W && RGB_Y+1 == VIDEO_H)?1'b1:1'b0;
|
||||
|
||||
reg FindFirstPixel;
|
||||
always @ (posedge BAYER_CLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
begin
|
||||
RGB_FRAME_COUNT <= 0;
|
||||
FindFirstPixel <= 1'b0;
|
||||
end
|
||||
else if (RGB_VALID)
|
||||
begin
|
||||
if (FirstPixel)
|
||||
FindFirstPixel <= 1'b1;
|
||||
else if (FindFirstPixel && LastPixel)
|
||||
begin
|
||||
FindFirstPixel <= 1'b0;
|
||||
RGB_FRAME_COUNT <= RGB_FRAME_COUNT + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "Shift register (RAM-based)"
|
||||
set_global_assignment -name IP_TOOL_VERSION "10.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "Bayer_LineBuffer.v"]
|
||||
112
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer_LineBuffer.v
Normal file
112
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer_LineBuffer.v
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
// megafunction wizard: %Shift register (RAM-based)%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: ALTSHIFT_TAPS
|
||||
|
||||
// ============================================================
|
||||
// File Name: Bayer_LineBuffer.v
|
||||
// Megafunction Name(s):
|
||||
// ALTSHIFT_TAPS
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2010 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module Bayer_LineBuffer #(
|
||||
parameter VIDEO_W = 800
|
||||
)(
|
||||
aclr,
|
||||
clken,
|
||||
clock,
|
||||
shiftin,
|
||||
shiftout,
|
||||
taps);
|
||||
|
||||
input aclr;
|
||||
input clken;
|
||||
input clock;
|
||||
input [11:0] shiftin;
|
||||
output [11:0] shiftout;
|
||||
output [35:0] taps;
|
||||
|
||||
wire [11:0] sub_wire0;
|
||||
wire [35:0] sub_wire1;
|
||||
wire [11:0] shiftout = sub_wire0[11:0];
|
||||
wire [35:0] taps = sub_wire1[35:0];
|
||||
|
||||
altshift_taps ALTSHIFT_TAPS_component (
|
||||
.aclr (aclr),
|
||||
.clock (clock),
|
||||
.clken (clken),
|
||||
.shiftin (shiftin),
|
||||
.shiftout (sub_wire0),
|
||||
.taps (sub_wire1));
|
||||
defparam
|
||||
ALTSHIFT_TAPS_component.intended_device_family = "Cyclone IV E",
|
||||
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
|
||||
ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
|
||||
ALTSHIFT_TAPS_component.number_of_taps = 3,
|
||||
ALTSHIFT_TAPS_component.power_up_state = "CLEARED",
|
||||
// ALTSHIFT_TAPS_component.tap_distance = 800,
|
||||
ALTSHIFT_TAPS_component.tap_distance = VIDEO_W, // ##Lou mod
|
||||
ALTSHIFT_TAPS_component.width = 12;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
|
||||
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "3"
|
||||
// Retrieval info: CONSTANT: POWER_UP_STATE STRING "CLEARED"
|
||||
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "800"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
|
||||
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
|
||||
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
|
||||
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
|
||||
// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL "shiftin[11..0]"
|
||||
// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
|
||||
// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL "shiftout[11..0]"
|
||||
// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
|
||||
// Retrieval info: USED_PORT: taps 0 0 36 0 OUTPUT NODEFVAL "taps[35..0]"
|
||||
// Retrieval info: CONNECT: taps 0 0 36 0 @taps 0 0 36 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL Bayer_LineBuffer.v TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL Bayer_LineBuffer.qip TRUE FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL Bayer_LineBuffer.bsf FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL Bayer_LineBuffer_inst.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL Bayer_LineBuffer_bb.v FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL Bayer_LineBuffer.inc FALSE TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL Bayer_LineBuffer.cmp FALSE TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
121
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_Bayer.v
Normal file
121
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_Bayer.v
Normal file
|
|
@ -0,0 +1,121 @@
|
|||
module CAMERA_Bayer(
|
||||
reset_n,
|
||||
|
||||
CAMERA_D,
|
||||
CAMERA_FVAL,
|
||||
CAMERA_LVAL,
|
||||
CAMERA_PIXCLK,
|
||||
|
||||
BAYER_X,
|
||||
BAYER_Y,
|
||||
BAYER_DATA,
|
||||
BAYER_VALID,
|
||||
BAYER_WIDTH,
|
||||
BAYER_HEIGH
|
||||
);
|
||||
|
||||
input reset_n;
|
||||
|
||||
input [11:0] CAMERA_D;
|
||||
input CAMERA_FVAL;
|
||||
input CAMERA_LVAL;
|
||||
input CAMERA_PIXCLK;
|
||||
|
||||
output reg [11:0] BAYER_X;
|
||||
output reg [11:0] BAYER_Y;
|
||||
output reg [11:0] BAYER_DATA;
|
||||
output reg BAYER_VALID;
|
||||
output reg [11:0] BAYER_WIDTH;
|
||||
output reg [11:0] BAYER_HEIGH;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
reg pre_CAMERA_FVAL;
|
||||
reg pre_CAMERA_LVAL;
|
||||
|
||||
always @ (negedge CAMERA_PIXCLK)
|
||||
begin
|
||||
pre_CAMERA_FVAL <= CAMERA_FVAL;
|
||||
pre_CAMERA_LVAL <= CAMERA_LVAL;
|
||||
end
|
||||
|
||||
//////////////////////
|
||||
// Y, heigh count
|
||||
reg [11:0] y_cnt;
|
||||
always @ (posedge CAMERA_PIXCLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
begin
|
||||
BAYER_HEIGH <= 0;
|
||||
y_cnt <= 0;
|
||||
end
|
||||
else if (pre_CAMERA_FVAL & ~CAMERA_FVAL)
|
||||
begin
|
||||
y_cnt <= 0;
|
||||
if (y_cnt > BAYER_HEIGH)
|
||||
BAYER_HEIGH <= y_cnt;
|
||||
end
|
||||
else if (pre_CAMERA_LVAL && ~CAMERA_LVAL)
|
||||
y_cnt <= y_cnt + 1;
|
||||
|
||||
end
|
||||
|
||||
always @ (posedge CAMERA_PIXCLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
BAYER_Y <= 0;
|
||||
else
|
||||
BAYER_Y <= y_cnt;
|
||||
end
|
||||
|
||||
//////////////////////
|
||||
// X, width count
|
||||
reg [11:0] x_cnt;
|
||||
always @ (posedge CAMERA_PIXCLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
begin
|
||||
BAYER_WIDTH <= 0;
|
||||
x_cnt <= 0;
|
||||
end
|
||||
else if (pre_CAMERA_LVAL & ~CAMERA_LVAL)
|
||||
begin
|
||||
x_cnt <= 0;
|
||||
if (x_cnt > BAYER_WIDTH)
|
||||
BAYER_WIDTH <= x_cnt;
|
||||
end
|
||||
else if (CAMERA_FVAL & CAMERA_LVAL)
|
||||
x_cnt <= x_cnt + 1;
|
||||
end
|
||||
|
||||
always @ (posedge CAMERA_PIXCLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
BAYER_X <= 0;
|
||||
else
|
||||
BAYER_X <= x_cnt;
|
||||
end
|
||||
|
||||
// data valid
|
||||
always @ (posedge CAMERA_PIXCLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
BAYER_VALID <= 1'b0;
|
||||
else
|
||||
BAYER_VALID <= (CAMERA_FVAL & CAMERA_LVAL)?1'b1:1'b0;
|
||||
|
||||
end
|
||||
|
||||
// data
|
||||
always @ (posedge CAMERA_PIXCLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
BAYER_DATA <= 12'h000;
|
||||
else
|
||||
BAYER_DATA <= CAMERA_D;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
95
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_RGB.v
Normal file
95
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_RGB.v
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
module CAMERA_RGB(
|
||||
reset_n,
|
||||
|
||||
// Bayer Input
|
||||
CAMERA_D,
|
||||
CAMERA_FVAL,
|
||||
CAMERA_LVAL,
|
||||
CAMERA_PIXCLK,
|
||||
|
||||
// RGB Output
|
||||
RGB_R,
|
||||
RGB_G,
|
||||
RGB_B,
|
||||
RGB_X,
|
||||
RGB_Y,
|
||||
RGB_VALID
|
||||
|
||||
|
||||
);
|
||||
|
||||
|
||||
input reset_n;
|
||||
|
||||
input [11:0] CAMERA_D;
|
||||
input CAMERA_FVAL;
|
||||
input CAMERA_LVAL;
|
||||
input CAMERA_PIXCLK;
|
||||
|
||||
output [11:0] RGB_R;
|
||||
output [11:0] RGB_G;
|
||||
output [11:0] RGB_B;
|
||||
output [11:0] RGB_X;
|
||||
output [11:0] RGB_Y;
|
||||
output RGB_VALID;
|
||||
|
||||
////////////////////////////////////////////////
|
||||
|
||||
/* ##lou mod
|
||||
parameter VIDEO_W = 800;
|
||||
parameter VIDEO_H = 600;
|
||||
*/
|
||||
|
||||
parameter VIDEO_W = 1280;
|
||||
parameter VIDEO_H = 720;
|
||||
|
||||
////////////////////////////////////
|
||||
wire [11:0] BAYER_X;
|
||||
wire [11:0] BAYER_Y;
|
||||
wire [11:0] BAYER_DATA;
|
||||
wire BAYER_VALID;
|
||||
|
||||
CAMERA_Bayer CAMERA_Bayer_inst(
|
||||
.reset_n(reset_n),
|
||||
|
||||
.CAMERA_D(CAMERA_D),
|
||||
.CAMERA_FVAL(CAMERA_FVAL),
|
||||
.CAMERA_LVAL(CAMERA_LVAL),
|
||||
.CAMERA_PIXCLK(CAMERA_PIXCLK),
|
||||
|
||||
.BAYER_X(BAYER_X),
|
||||
.BAYER_Y(BAYER_Y),
|
||||
.BAYER_DATA(BAYER_DATA),
|
||||
.BAYER_VALID(BAYER_VALID),
|
||||
.BAYER_WIDTH(),
|
||||
.BAYER_HEIGH()
|
||||
);
|
||||
|
||||
|
||||
|
||||
Bayer2RGB Bayer2RGB_inst(
|
||||
.reset_n(reset_n),
|
||||
|
||||
.BAYER_CLK(CAMERA_PIXCLK),
|
||||
.BAYER_X(BAYER_X),
|
||||
.BAYER_Y(BAYER_Y),
|
||||
.BAYER_DATA(BAYER_DATA),
|
||||
.BAYER_VALID(BAYER_VALID),
|
||||
.BAYER_WIDTH(),
|
||||
.BAYER_HEIGH(),
|
||||
|
||||
.RGB_R(RGB_R),
|
||||
.RGB_G(RGB_G),
|
||||
.RGB_B(RGB_B),
|
||||
.RGB_X(RGB_X),
|
||||
.RGB_Y(RGB_Y),
|
||||
.RGB_VALID(RGB_VALID)
|
||||
|
||||
);
|
||||
|
||||
defparam Bayer2RGB_inst.VIDEO_W = VIDEO_W;
|
||||
defparam Bayer2RGB_inst.VIDEO_H = VIDEO_H;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
198
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v
Normal file
198
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
// Packet: follow video packet of "Avalon-ST Video Protocol" defined VIP spec.
|
||||
|
||||
|
||||
|
||||
module TERASIC_CAMERA(
|
||||
clk,
|
||||
reset_n,
|
||||
|
||||
// streaming source interface
|
||||
st_data,
|
||||
st_valid,
|
||||
st_sop,
|
||||
st_eop,
|
||||
st_ready,
|
||||
|
||||
|
||||
|
||||
// export
|
||||
CAMERA_D,
|
||||
CAMERA_FVAL,
|
||||
CAMERA_LVAL,
|
||||
CAMERA_PIXCLK
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
input clk;
|
||||
input reset_n;
|
||||
|
||||
|
||||
output [23:0] st_data;
|
||||
output st_valid;
|
||||
output st_sop;
|
||||
output st_eop;
|
||||
input st_ready;
|
||||
|
||||
|
||||
|
||||
input [11:0] CAMERA_D;
|
||||
input CAMERA_FVAL;
|
||||
input CAMERA_LVAL;
|
||||
input CAMERA_PIXCLK;
|
||||
|
||||
////////////////////////////////////////////////
|
||||
/* ##lou mod
|
||||
parameter VIDEO_W = 800;
|
||||
parameter VIDEO_H = 600;
|
||||
*/
|
||||
|
||||
parameter VIDEO_W = 1280;
|
||||
parameter VIDEO_H = 720;
|
||||
`define VIDEO_PIX_NUM (VIDEO_W * VIDEO_H)
|
||||
|
||||
////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
|
||||
wire [11:0] RGB_R,RGB_G, RGB_B;
|
||||
wire [11:0] RGB_X,RGB_Y;
|
||||
wire RGB_VALID;
|
||||
|
||||
CAMERA_RGB CAMERA_RGB_inst(
|
||||
.reset_n(reset_n),
|
||||
|
||||
// Bayer Input
|
||||
.CAMERA_D(CAMERA_D),
|
||||
.CAMERA_FVAL(CAMERA_FVAL),
|
||||
.CAMERA_LVAL(CAMERA_LVAL),
|
||||
.CAMERA_PIXCLK(CAMERA_PIXCLK),
|
||||
|
||||
// RGB Output
|
||||
.RGB_R(RGB_R),
|
||||
.RGB_G(RGB_G),
|
||||
.RGB_B(RGB_B),
|
||||
.RGB_X(RGB_X),
|
||||
.RGB_Y(RGB_Y),
|
||||
.RGB_VALID(RGB_VALID)
|
||||
|
||||
);
|
||||
|
||||
defparam CAMERA_RGB_inst.VIDEO_W = VIDEO_W;
|
||||
defparam CAMERA_RGB_inst.VIDEO_H = VIDEO_H;
|
||||
|
||||
|
||||
|
||||
/////////////////////////////
|
||||
// write rgb to fifo
|
||||
|
||||
reg [25:0] fifo_w_data; // 1-bit sop + 1-bit eop + 24-bits data
|
||||
wire fifo_w_full;
|
||||
wire sop;
|
||||
wire eop;
|
||||
wire in_active_area;
|
||||
|
||||
assign sop = (RGB_X == 0 && RGB_Y == 0)?1'b1:1'b0;
|
||||
assign eop = (((RGB_X+1) == VIDEO_W) && ((RGB_Y+1) == VIDEO_H))?1'b1:1'b0;
|
||||
|
||||
assign in_active_area = ((RGB_X < VIDEO_W) && (RGB_Y < VIDEO_H))?1'b1:1'b0;
|
||||
|
||||
reg fifo_w_write;
|
||||
always @ (posedge CAMERA_PIXCLK or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
begin
|
||||
fifo_w_write <= 1'b0;
|
||||
//push_fail <= 1'b0;
|
||||
end
|
||||
else if (RGB_VALID & in_active_area)
|
||||
begin
|
||||
if (!fifo_w_full)
|
||||
begin
|
||||
fifo_w_data <= {sop,eop, RGB_B[11:4], RGB_G[11:4], RGB_R[11:4]};
|
||||
fifo_w_write <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
fifo_w_write <= 1'b0;
|
||||
// push_fail <= 1'b1; // fifo full !!!!!
|
||||
end
|
||||
end
|
||||
else
|
||||
fifo_w_write <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
|
||||
/////////////////////////////
|
||||
// read from fifo
|
||||
wire fifo_r_empty;
|
||||
wire [25:0] fifo_r_q;
|
||||
wire fifo_r_rdreq_ack;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/////////////////////////////
|
||||
// FIFO
|
||||
rgb_fifo rgb_fifo_inst(
|
||||
// write
|
||||
.data(fifo_w_data),
|
||||
.wrclk(~CAMERA_PIXCLK),
|
||||
.wrreq(fifo_w_write),
|
||||
.wrfull(fifo_w_full),
|
||||
|
||||
// read
|
||||
.rdclk(clk),
|
||||
.rdreq(fifo_r_rdreq_ack),
|
||||
.q(fifo_r_q),
|
||||
.rdempty(fifo_r_empty),
|
||||
//
|
||||
.aclr(~reset_n)
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
///////////////////////////////
|
||||
wire frame_start;
|
||||
assign frame_start = fifo_r_q[25] & ~fifo_r_empty;
|
||||
|
||||
reg first_pix;
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
first_pix <= 1'b0;
|
||||
else if (send_packet_id)
|
||||
first_pix <= 1'b1;
|
||||
else
|
||||
first_pix <= 1'b0;
|
||||
end
|
||||
|
||||
wire send_packet_id;
|
||||
assign send_packet_id = frame_start & ~first_pix;
|
||||
|
||||
/////////////////////////////
|
||||
// flag for ready_latency=1
|
||||
reg pre_ready;
|
||||
always @ (posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (~reset_n)
|
||||
pre_ready <= 0;
|
||||
else
|
||||
pre_ready <= st_ready;
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////
|
||||
assign {st_sop, st_eop, st_data} = (send_packet_id)?{1'b1,1'b0, 24'h000000}:{1'b0, fifo_r_q[24:0]};
|
||||
assign st_valid = ~fifo_r_empty & pre_ready;
|
||||
assign fifo_r_rdreq_ack = st_valid & (~send_packet_id);
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
# TCL File Generated by Component Editor 10.1
|
||||
# Sun Jan 23 01:18:19 CST 2011
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
# +-----------------------------------
|
||||
# |
|
||||
# | TERASIC_CAMERA "TERASIC_CAMERA" v1.0
|
||||
# | null 2011.01.23.01:18:19
|
||||
# |
|
||||
# |
|
||||
# | D:/svn/DE2_115_WDR_CAMERA/ip/TERASIC_CAMERA/TERASIC_CAMERA.v
|
||||
# |
|
||||
# | ./TERASIC_CAMERA.v syn, sim
|
||||
# | ./CAMERA_RGB.v syn, sim
|
||||
# | ./CAMERA_Bayer.v syn, sim
|
||||
# | ./Bayer2RGB.v syn, sim
|
||||
# | ./Bayer_LineBuffer.v syn, sim
|
||||
# | ./rgb_fifo.v syn, sim
|
||||
# | ./add2.v syn, sim
|
||||
# | ./add4.v syn, sim
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | request TCL package from ACDS 10.1
|
||||
# |
|
||||
package require -exact sopc 10.1
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | module TERASIC_CAMERA
|
||||
# |
|
||||
set_module_property NAME TERASIC_CAMERA
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property GROUP "Terasic Technologies Inc"
|
||||
set_module_property DISPLAY_NAME TERASIC_CAMERA
|
||||
set_module_property TOP_LEVEL_HDL_FILE TERASIC_CAMERA.v
|
||||
set_module_property TOP_LEVEL_HDL_MODULE TERASIC_CAMERA
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property ANALYZE_HDL TRUE
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | files
|
||||
# |
|
||||
add_file TERASIC_CAMERA.v {SYNTHESIS SIMULATION}
|
||||
add_file CAMERA_RGB.v {SYNTHESIS SIMULATION}
|
||||
add_file CAMERA_Bayer.v {SYNTHESIS SIMULATION}
|
||||
add_file Bayer2RGB.v {SYNTHESIS SIMULATION}
|
||||
add_file Bayer_LineBuffer.v {SYNTHESIS SIMULATION}
|
||||
add_file rgb_fifo.v {SYNTHESIS SIMULATION}
|
||||
add_file add2.v {SYNTHESIS SIMULATION}
|
||||
add_file add4.v {SYNTHESIS SIMULATION}
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | parameters
|
||||
# |
|
||||
add_parameter VIDEO_W INTEGER 800
|
||||
set_parameter_property VIDEO_W DEFAULT_VALUE 800
|
||||
set_parameter_property VIDEO_W DISPLAY_NAME VIDEO_W
|
||||
set_parameter_property VIDEO_W TYPE INTEGER
|
||||
set_parameter_property VIDEO_W UNITS None
|
||||
set_parameter_property VIDEO_W ALLOWED_RANGES -2147483648:2147483647
|
||||
set_parameter_property VIDEO_W AFFECTS_GENERATION false
|
||||
set_parameter_property VIDEO_W HDL_PARAMETER true
|
||||
add_parameter VIDEO_H INTEGER 600
|
||||
set_parameter_property VIDEO_H DEFAULT_VALUE 600
|
||||
set_parameter_property VIDEO_H DISPLAY_NAME VIDEO_H
|
||||
set_parameter_property VIDEO_H TYPE INTEGER
|
||||
set_parameter_property VIDEO_H UNITS None
|
||||
set_parameter_property VIDEO_H ALLOWED_RANGES -2147483648:2147483647
|
||||
set_parameter_property VIDEO_H AFFECTS_GENERATION false
|
||||
set_parameter_property VIDEO_H HDL_PARAMETER true
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | display items
|
||||
# |
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | connection point clock_reset
|
||||
# |
|
||||
add_interface clock_reset clock end
|
||||
set_interface_property clock_reset clockRate 0
|
||||
|
||||
set_interface_property clock_reset ENABLED true
|
||||
|
||||
add_interface_port clock_reset clk clk Input 1
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | connection point clock_reset_reset
|
||||
# |
|
||||
add_interface clock_reset_reset reset end
|
||||
set_interface_property clock_reset_reset associatedClock clock_reset
|
||||
set_interface_property clock_reset_reset synchronousEdges DEASSERT
|
||||
|
||||
set_interface_property clock_reset_reset ENABLED true
|
||||
|
||||
add_interface_port clock_reset_reset reset_n reset_n Input 1
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | connection point conduit_end
|
||||
# |
|
||||
add_interface conduit_end conduit end
|
||||
|
||||
set_interface_property conduit_end ENABLED true
|
||||
|
||||
add_interface_port conduit_end CAMERA_D export Input 12
|
||||
add_interface_port conduit_end CAMERA_FVAL export Input 1
|
||||
add_interface_port conduit_end CAMERA_LVAL export Input 1
|
||||
add_interface_port conduit_end CAMERA_PIXCLK export Input 1
|
||||
# |
|
||||
# +-----------------------------------
|
||||
|
||||
# +-----------------------------------
|
||||
# | connection point avalon_streaming_source
|
||||
# |
|
||||
add_interface avalon_streaming_source avalon_streaming start
|
||||
set_interface_property avalon_streaming_source associatedClock clock_reset
|
||||
set_interface_property avalon_streaming_source associatedReset clock_reset_reset
|
||||
set_interface_property avalon_streaming_source dataBitsPerSymbol 8
|
||||
set_interface_property avalon_streaming_source errorDescriptor ""
|
||||
set_interface_property avalon_streaming_source maxChannel 0
|
||||
set_interface_property avalon_streaming_source readyLatency 1
|
||||
|
||||
set_interface_property avalon_streaming_source ENABLED true
|
||||
|
||||
add_interface_port avalon_streaming_source st_data data Output 24
|
||||
add_interface_port avalon_streaming_source st_sop startofpacket Output 1
|
||||
add_interface_port avalon_streaming_source st_eop endofpacket Output 1
|
||||
add_interface_port avalon_streaming_source st_ready ready Input 1
|
||||
add_interface_port avalon_streaming_source st_valid valid Output 1
|
||||
# |
|
||||
# +-----------------------------------
|
||||
4
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2.qip
Normal file
4
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2.qip
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "PARALLEL_ADD"
|
||||
set_global_assignment -name IP_TOOL_VERSION "10.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "add2.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "add2_bb.v"]
|
||||
103
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2.v
Normal file
103
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2.v
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
// megafunction wizard: %PARALLEL_ADD%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: parallel_add
|
||||
|
||||
// ============================================================
|
||||
// File Name: add2.v
|
||||
// Megafunction Name(s):
|
||||
// parallel_add
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2010 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module add2 (
|
||||
data0x,
|
||||
data1x,
|
||||
result);
|
||||
|
||||
input [11:0] data0x;
|
||||
input [11:0] data1x;
|
||||
output [12:0] result;
|
||||
|
||||
wire [12:0] sub_wire0;
|
||||
wire [11:0] sub_wire3 = data1x[11:0];
|
||||
wire [12:0] result = sub_wire0[12:0];
|
||||
wire [11:0] sub_wire1 = data0x[11:0];
|
||||
wire [23:0] sub_wire2 = {sub_wire3, sub_wire1};
|
||||
|
||||
parallel_add parallel_add_component (
|
||||
.data (sub_wire2),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
parallel_add_component.msw_subtract = "NO",
|
||||
parallel_add_component.pipeline = 0,
|
||||
parallel_add_component.representation = "UNSIGNED",
|
||||
parallel_add_component.result_alignment = "LSB",
|
||||
parallel_add_component.shift = 0,
|
||||
parallel_add_component.size = 2,
|
||||
parallel_add_component.width = 12,
|
||||
parallel_add_component.widthr = 13;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
|
||||
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: REPRESENTATION STRING "UNSIGNED"
|
||||
// Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
|
||||
// Retrieval info: CONSTANT: SHIFT NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: SIZE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: WIDTHR NUMERIC "13"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 12 0 INPUT NODEFVAL "data0x[11..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 12 0 INPUT NODEFVAL "data1x[11..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 13 0 OUTPUT NODEFVAL "result[12..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 12 0 data0x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 12 data1x 0 0 12 0
|
||||
// Retrieval info: CONNECT: result 0 0 13 0 @result 0 0 13 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
71
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2_bb.v
Normal file
71
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2_bb.v
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
// megafunction wizard: %PARALLEL_ADD%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: parallel_add
|
||||
|
||||
// ============================================================
|
||||
// File Name: add2.v
|
||||
// Megafunction Name(s):
|
||||
// parallel_add
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2010 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
module add2 (
|
||||
data0x,
|
||||
data1x,
|
||||
result);
|
||||
|
||||
input [11:0] data0x;
|
||||
input [11:0] data1x;
|
||||
output [12:0] result;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
|
||||
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: REPRESENTATION STRING "UNSIGNED"
|
||||
// Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
|
||||
// Retrieval info: CONSTANT: SHIFT NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: SIZE NUMERIC "2"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: WIDTHR NUMERIC "13"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 12 0 INPUT NODEFVAL "data0x[11..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 12 0 INPUT NODEFVAL "data1x[11..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 13 0 OUTPUT NODEFVAL "result[12..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 12 0 data0x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 12 data1x 0 0 12 0
|
||||
// Retrieval info: CONNECT: result 0 0 13 0 @result 0 0 13 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add2_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
4
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4.qip
Normal file
4
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4.qip
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "PARALLEL_ADD"
|
||||
set_global_assignment -name IP_TOOL_VERSION "10.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "add4.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "add4_bb.v"]
|
||||
113
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4.v
Normal file
113
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4.v
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
// megafunction wizard: %PARALLEL_ADD%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: parallel_add
|
||||
|
||||
// ============================================================
|
||||
// File Name: add4.v
|
||||
// Megafunction Name(s):
|
||||
// parallel_add
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2010 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module add4 (
|
||||
data0x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
result);
|
||||
|
||||
input [11:0] data0x;
|
||||
input [11:0] data1x;
|
||||
input [11:0] data2x;
|
||||
input [11:0] data3x;
|
||||
output [13:0] result;
|
||||
|
||||
wire [13:0] sub_wire0;
|
||||
wire [11:0] sub_wire5 = data3x[11:0];
|
||||
wire [11:0] sub_wire4 = data2x[11:0];
|
||||
wire [11:0] sub_wire3 = data1x[11:0];
|
||||
wire [13:0] result = sub_wire0[13:0];
|
||||
wire [11:0] sub_wire1 = data0x[11:0];
|
||||
wire [47:0] sub_wire2 = {sub_wire5, sub_wire4, sub_wire3, sub_wire1};
|
||||
|
||||
parallel_add parallel_add_component (
|
||||
.data (sub_wire2),
|
||||
.result (sub_wire0)
|
||||
// synopsys translate_off
|
||||
,
|
||||
.aclr (),
|
||||
.clken (),
|
||||
.clock ()
|
||||
// synopsys translate_on
|
||||
);
|
||||
defparam
|
||||
parallel_add_component.msw_subtract = "NO",
|
||||
parallel_add_component.pipeline = 0,
|
||||
parallel_add_component.representation = "UNSIGNED",
|
||||
parallel_add_component.result_alignment = "LSB",
|
||||
parallel_add_component.shift = 0,
|
||||
parallel_add_component.size = 4,
|
||||
parallel_add_component.width = 12,
|
||||
parallel_add_component.widthr = 14;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
|
||||
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: REPRESENTATION STRING "UNSIGNED"
|
||||
// Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
|
||||
// Retrieval info: CONSTANT: SHIFT NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: SIZE NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: WIDTHR NUMERIC "14"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 12 0 INPUT NODEFVAL "data0x[11..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 12 0 INPUT NODEFVAL "data1x[11..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 12 0 INPUT NODEFVAL "data2x[11..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 12 0 INPUT NODEFVAL "data3x[11..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 14 0 OUTPUT NODEFVAL "result[13..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 12 0 data0x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 12 data1x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 24 data2x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 36 data3x 0 0 12 0
|
||||
// Retrieval info: CONNECT: result 0 0 14 0 @result 0 0 14 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
79
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4_bb.v
Normal file
79
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4_bb.v
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
// megafunction wizard: %PARALLEL_ADD%VBB%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: parallel_add
|
||||
|
||||
// ============================================================
|
||||
// File Name: add4.v
|
||||
// Megafunction Name(s):
|
||||
// parallel_add
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
//Copyright (C) 1991-2010 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
module add4 (
|
||||
data0x,
|
||||
data1x,
|
||||
data2x,
|
||||
data3x,
|
||||
result);
|
||||
|
||||
input [11:0] data0x;
|
||||
input [11:0] data1x;
|
||||
input [11:0] data2x;
|
||||
input [11:0] data3x;
|
||||
output [13:0] result;
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: MSW_SUBTRACT STRING "NO"
|
||||
// Retrieval info: CONSTANT: PIPELINE NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: REPRESENTATION STRING "UNSIGNED"
|
||||
// Retrieval info: CONSTANT: RESULT_ALIGNMENT STRING "LSB"
|
||||
// Retrieval info: CONSTANT: SHIFT NUMERIC "0"
|
||||
// Retrieval info: CONSTANT: SIZE NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: WIDTHR NUMERIC "14"
|
||||
// Retrieval info: USED_PORT: data0x 0 0 12 0 INPUT NODEFVAL "data0x[11..0]"
|
||||
// Retrieval info: USED_PORT: data1x 0 0 12 0 INPUT NODEFVAL "data1x[11..0]"
|
||||
// Retrieval info: USED_PORT: data2x 0 0 12 0 INPUT NODEFVAL "data2x[11..0]"
|
||||
// Retrieval info: USED_PORT: data3x 0 0 12 0 INPUT NODEFVAL "data3x[11..0]"
|
||||
// Retrieval info: USED_PORT: result 0 0 14 0 OUTPUT NODEFVAL "result[13..0]"
|
||||
// Retrieval info: CONNECT: @data 0 0 12 0 data0x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 12 data1x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 24 data2x 0 0 12 0
|
||||
// Retrieval info: CONNECT: @data 0 0 12 36 data3x 0 0 12 0
|
||||
// Retrieval info: CONNECT: result 0 0 14 0 @result 0 0 14 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL add4_bb.v TRUE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
INTENDED_DEVICE_FAMILY="Cyclone IV E"
|
||||
LPM_HINT=RAM_BLOCK_TYPE=M9K
|
||||
LPM_TYPE=altshift_taps
|
||||
NUMBER_OF_TAPS=3
|
||||
TAP_DISTANCE=800
|
||||
WIDTH=12
|
||||
DEVICE_FAMILY="Cyclone IV E"
|
||||
aclr
|
||||
clken
|
||||
clock
|
||||
shiftin
|
||||
shiftout
|
||||
taps
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
set_global_assignment -name IP_TOOL_NAME "FIFO"
|
||||
set_global_assignment -name IP_TOOL_VERSION "10.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rgb_fifo.v"]
|
||||
178
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo.v
Normal file
178
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo.v
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
// megafunction wizard: %FIFO%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: dcfifo
|
||||
|
||||
// ============================================================
|
||||
// File Name: rgb_fifo.v
|
||||
// Megafunction Name(s):
|
||||
// dcfifo
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
//
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 10.1 Build 153 11/29/2010 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2010 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module rgb_fifo (
|
||||
aclr,
|
||||
data,
|
||||
rdclk,
|
||||
rdreq,
|
||||
wrclk,
|
||||
wrreq,
|
||||
q,
|
||||
rdempty,
|
||||
wrfull);
|
||||
|
||||
input aclr;
|
||||
input [25:0] data;
|
||||
input rdclk;
|
||||
input rdreq;
|
||||
input wrclk;
|
||||
input wrreq;
|
||||
output [25:0] q;
|
||||
output rdempty;
|
||||
output wrfull;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 aclr;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire sub_wire0;
|
||||
wire [25:0] sub_wire1;
|
||||
wire sub_wire2;
|
||||
wire wrfull = sub_wire0;
|
||||
wire [25:0] q = sub_wire1[25:0];
|
||||
wire rdempty = sub_wire2;
|
||||
|
||||
dcfifo dcfifo_component (
|
||||
.rdclk (rdclk),
|
||||
.wrclk (wrclk),
|
||||
.wrreq (wrreq),
|
||||
.aclr (aclr),
|
||||
.data (data),
|
||||
.rdreq (rdreq),
|
||||
.wrfull (sub_wire0),
|
||||
.q (sub_wire1),
|
||||
.rdempty (sub_wire2),
|
||||
.rdfull (),
|
||||
.rdusedw (),
|
||||
.wrempty (),
|
||||
.wrusedw ());
|
||||
defparam
|
||||
dcfifo_component.intended_device_family = "Cyclone IV E",
|
||||
dcfifo_component.lpm_numwords = 4096,
|
||||
dcfifo_component.lpm_showahead = "ON",
|
||||
dcfifo_component.lpm_type = "dcfifo",
|
||||
dcfifo_component.lpm_width = 26,
|
||||
dcfifo_component.lpm_widthu = 12,
|
||||
dcfifo_component.overflow_checking = "ON",
|
||||
dcfifo_component.rdsync_delaypipe = 5,
|
||||
dcfifo_component.underflow_checking = "ON",
|
||||
dcfifo_component.use_eab = "ON",
|
||||
dcfifo_component.write_aclr_synch = "OFF",
|
||||
dcfifo_component.wrsync_delaypipe = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
|
||||
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Clock NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
|
||||
// Retrieval info: PRIVATE: Empty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Full NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: Width NUMERIC "26"
|
||||
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: output_width NUMERIC "26"
|
||||
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
|
||||
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
|
||||
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "26"
|
||||
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
|
||||
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
|
||||
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
|
||||
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
|
||||
// Retrieval info: USED_PORT: data 0 0 26 0 INPUT NODEFVAL "data[25..0]"
|
||||
// Retrieval info: USED_PORT: q 0 0 26 0 OUTPUT NODEFVAL "q[25..0]"
|
||||
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
|
||||
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
|
||||
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
|
||||
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
|
||||
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
|
||||
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
|
||||
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
|
||||
// Retrieval info: CONNECT: @data 0 0 26 0 data 0 0 26 0
|
||||
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
|
||||
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
|
||||
// Retrieval info: CONNECT: q 0 0 26 0 @q 0 0 26 0
|
||||
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
|
||||
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_bb.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_waveforms.html TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL rgb_fifo_wave*.jpg FALSE
|
||||
BIN
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo_wave0.jpg
Normal file
BIN
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo_wave0.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 106 KiB |
BIN
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo_wave1.jpg
Normal file
BIN
Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo_wave1.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 94 KiB |
|
|
@ -0,0 +1,16 @@
|
|||
<html>
|
||||
<head>
|
||||
<title>Sample Waveforms for "rgb_fifo.v" </title>
|
||||
</head>
|
||||
<body>
|
||||
<h2><CENTER>Sample behavioral waveforms for design file "rgb_fifo.v" </CENTER></h2>
|
||||
<P>The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "rgb_fifo.v". The design "rgb_fifo.v" has a depth of 4096 words of 26 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge. </P>
|
||||
<CENTER><img src=rgb_fifo_wave0.jpg> </CENTER>
|
||||
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read and write operation. </CENTER></P>
|
||||
<P><FONT size=3>The above waveform shows the behavior of the design under normal read and write conditions with aclr . </P>
|
||||
<CENTER><img src=rgb_fifo_wave1.jpg> </CENTER>
|
||||
<P><CENTER><FONT size=2>Fig. 2 : Wave showing FIFO full operation. </CENTER></P>
|
||||
<P><FONT size=3>The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back. </P>
|
||||
<P></P>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/* these test were created to show how to use the opencores I2C along with a driver found in
|
||||
* the I2C_opencores component to talk to various components.
|
||||
* This test example uses a littel daughter board from microtronix
|
||||
* it has a I2c to parallel chip (PCA9554A) a EEPORM and real time clock.
|
||||
* I chose not to impliment the real time clock.
|
||||
* But you can see how the calls work
|
||||
* There are only 4 functions associalted with the I2C driver
|
||||
* I2C start - send start bit and address of the chip
|
||||
* I2C_read - read data
|
||||
* I2C_write. - write data
|
||||
* how and when each of these get used is based on the device you
|
||||
* are talking to.
|
||||
* See the driver code for details of each function.
|
||||
* */
|
||||
|
||||
#include <stdio.h>
|
||||
#include "system.h"
|
||||
#include "i2c_opencores.h"
|
||||
int main()
|
||||
{
|
||||
int data;
|
||||
int i;
|
||||
// testing the PCA9554A paralle interface
|
||||
// this writes a 5 to the leds and read the position of the dip switches.
|
||||
printf(" tesing the PCA9554A interface the\n the LEDS should be at a 5 \n");
|
||||
// address 0x38
|
||||
// set the fequesncy that you want to run at
|
||||
// most devices work at 100Khz some faster
|
||||
I2C_init(I2CA_BASE,ALT_CPU_FREQ,100000);
|
||||
I2C_init(I2CA_BASE,ALT_CPU_FREQ,100000);
|
||||
// for the parallel io only the first 4 are output s
|
||||
|
||||
// the PCA9554A uses a command word right after the chip address word ( the start work)
|
||||
I2C_start(I2CA_BASE,0x38,0);// chip address in write mode
|
||||
I2C_write(I2CA_BASE,3,0); // write to register 3 command
|
||||
I2C_write(I2CA_BASE,0xf0,1); // set the bottom 4 bits to outputs for the LEDs set the stop
|
||||
|
||||
// now right to the leds
|
||||
I2C_start(I2CA_BASE,0x38,0); // address the chip in write mode
|
||||
I2C_write(I2CA_BASE,1,0); // set command to the pca9554 to be output register
|
||||
I2C_write(I2CA_BASE,5,1); // write the data to the output register and set the stop
|
||||
|
||||
//now read the dip switches
|
||||
// first set the command to 0
|
||||
I2C_start(I2CA_BASE,0x38,0); //address the chip in write mode
|
||||
data = I2C_write(I2CA_BASE,0,0); // set command to read input register.
|
||||
I2C_start(I2CA_BASE,0x38,1); //send start again but this time in read mode
|
||||
data = I2C_read(I2CA_BASE,1); // read the input register and send stop
|
||||
data = 0xff & (data >>4);
|
||||
printf("dip switch 0x%x\n",data);
|
||||
|
||||
printf("\nNow writing and reading from the EEPROM\n");
|
||||
//address 0x50-57
|
||||
I2C_start(I2CA_BASE,0x50,0); // chip address in write mode
|
||||
I2C_write(I2CA_BASE,0,0); // write to starting address of 0
|
||||
// now write the data
|
||||
for (i=0;i<7;i++) // can only write 8 bites at a time
|
||||
{
|
||||
I2C_write(I2CA_BASE,i,0); // writ the data
|
||||
}
|
||||
I2C_write(I2CA_BASE,i,1); // write last one with last flag
|
||||
|
||||
while ( I2C_start(I2CA_BASE,0x50,0)); // make sure the write is done be fore continuing.
|
||||
// can ony burst 8 at a time.
|
||||
|
||||
I2C_write(I2CA_BASE,8,0); // write to starting address of 8
|
||||
// now write the data
|
||||
for (i=0;i<7;i++) // write the next 8 bytes
|
||||
{
|
||||
I2C_write(I2CA_BASE,i+8,0); //
|
||||
}
|
||||
I2C_write(I2CA_BASE,i+8,1); // write last one with last flag
|
||||
|
||||
while ( I2C_start(I2CA_BASE,0x50,0)); // make sure the write is done be fore continuing.
|
||||
|
||||
//now read the values
|
||||
// first set the command to 0
|
||||
I2C_start(I2CA_BASE,0x50,0); //set chip address and set to write/
|
||||
I2C_write(I2CA_BASE,0,0); // set address to 0.
|
||||
I2C_start(I2CA_BASE,0x50,1); //set chip address in read mode
|
||||
for (i=0;i<15;i++)
|
||||
{
|
||||
data = I2C_read(I2CA_BASE,0); // memory array
|
||||
printf("\tdata = 0x%x\n",data);
|
||||
}
|
||||
|
||||
data = I2C_read(I2CA_BASE,1); // last memory read
|
||||
printf("\tdata = 0x%x\n",data);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
printf("Hello from Nios II!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
BIN
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/Docs/i2c_specs.pdf
Normal file
BIN
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/Docs/i2c_specs.pdf
Normal file
Binary file not shown.
|
|
@ -0,0 +1,31 @@
|
|||
#ifndef __I2C_OPENCORES_H__
|
||||
#define __I2C_OPENCORES_H__
|
||||
|
||||
|
||||
#include "alt_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
|
||||
|
||||
void I2C_init(alt_u32 base,alt_u32 clk,alt_u32 speed);
|
||||
int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read);
|
||||
alt_u32 I2C_read(alt_u32 base,alt_u32 last);
|
||||
alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last);
|
||||
#define I2C_OK (0)
|
||||
#define I2C_ACK (0)
|
||||
#define I2C_NOACK (1)
|
||||
#define I2C_ABITRATION_LOST (2)
|
||||
|
||||
#define I2C_OPENCORES_INSTANCE(name, dev) extern int alt_no_storage
|
||||
#define I2C_OPENCORES_INIT(name, dev) while (0)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __I2C_OPENCORES_H__ */
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
# *******************************************************************************
|
||||
# * *
|
||||
# * License Agreement *
|
||||
# * *
|
||||
# * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
|
||||
# * All rights reserved. *
|
||||
# * *
|
||||
# * Permission is hereby granted, free of charge, to any person obtaining a *
|
||||
# * copy of this software and associated documentation files (the "Software"), *
|
||||
# * to deal in the Software without restriction, including without limitation *
|
||||
# * the rights to use, copy, modify, merge, publish, distribute, sublicense, *
|
||||
# * and/or sell copies of the Software, and to permit persons to whom the *
|
||||
# * Software is furnished to do so, subject to the following conditions: *
|
||||
# * *
|
||||
# * The above copyright notice and this permission notice shall be included in *
|
||||
# * all copies or substantial portions of the Software. *
|
||||
# * *
|
||||
# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
|
||||
# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
|
||||
# * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
|
||||
# * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
|
||||
# * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
|
||||
# * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
|
||||
# * DEALINGS IN THE SOFTWARE. *
|
||||
# * *
|
||||
# * This agreement shall be governed in all respects by the laws of the State *
|
||||
# * of California and by the laws of the United States of America. *
|
||||
# * *
|
||||
# * Altera does not recommend, suggest or require that this reference design *
|
||||
# * file be used in conjunction or combination with any other product. *
|
||||
# *******************************************************************************
|
||||
|
||||
# List all source files supplied by this component.
|
||||
|
||||
C_LIB_SRCS += i2c_opencores.c
|
||||
|
||||
ASM_LIB_SRCS +=
|
||||
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
|
||||
#include "alt_types.h"
|
||||
#include "i2c_opencores_regs.h"
|
||||
#include "i2c_opencores.h"
|
||||
|
||||
// #define I2C_DEBUG
|
||||
//int I2C_init(alt_u32 base,alt_u32 clk, alt_u32 speed)
|
||||
//int I2C_start(alt_u32 base, alt_u32 add, alt_u32 write);
|
||||
//alt_u32 I2C_read(alt_u32 base);
|
||||
//int I2C_write(alt_u32 base, alt_u8 data);
|
||||
//int I2C_stop(alt_u32 base);
|
||||
|
||||
/* these functions are polled only. */
|
||||
/* all functions wait until the I2C is done before exiting */
|
||||
|
||||
|
||||
/****************************************************************
|
||||
int I2C_init
|
||||
This function inititlizes the prescalor for the scl
|
||||
and then enables the core. This must be run before
|
||||
any other i2c code is executed
|
||||
inputs
|
||||
base = the base address of the component
|
||||
clk = freuqency of the clock driving this component ( in Hz)
|
||||
speed = SCL speed ie 100K, 400K ... (in Hz)
|
||||
15-OCT-07 initial release
|
||||
*****************************************************************/
|
||||
void I2C_init(alt_u32 base,alt_u32 clk,alt_u32 speed)
|
||||
{
|
||||
alt_u32 prescale = (clk/( 5 * speed))-1;
|
||||
#ifdef I2C_DEBUG
|
||||
printf(" Initializing I2C at 0x%x, \n\twith clock speed 0x%x \n\tand SCL speed 0x%x \n\tand prescale 0x%x\n",base,clk,speed,prescale);
|
||||
#endif
|
||||
IOWR_I2C_OPENCORES_CTR(base, 0x00); /* turn off the core*/
|
||||
|
||||
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_IACK_MSK); /* clearn any pening IRQ*/
|
||||
|
||||
IOWR_I2C_OPENCORES_PRERLO(base, (0xff & prescale)); /* load low presacle bit*/
|
||||
|
||||
IOWR_I2C_OPENCORES_PRERHI(base, (0xff & (prescale>>8))); /* load upper prescale bit */
|
||||
|
||||
IOWR_I2C_OPENCORES_CTR(base, I2C_OPENCORES_CTR_EN_MSK); /* turn on the core*/
|
||||
|
||||
}
|
||||
|
||||
/****************************************************************
|
||||
int I2C_start
|
||||
Sets the start bit and then sends the first byte which
|
||||
is the address of the device + the write bit.
|
||||
inputs
|
||||
base = the base address of the component
|
||||
add = address of I2C device
|
||||
read = 1== read 0== write
|
||||
return value
|
||||
0 if address is acknowledged
|
||||
1 if address was not acknowledged
|
||||
15-OCT-07 initial release
|
||||
*****************************************************************/
|
||||
int I2C_start(alt_u32 base, alt_u32 add, alt_u32 read)
|
||||
{
|
||||
#ifdef I2C_DEBUG
|
||||
printf(" Start I2C at 0x%x, \n\twith address 0x%x \n\tand read 0x%x \n\tand prescale 0x%x\n",base,add,read);
|
||||
#endif
|
||||
|
||||
/* transmit the address shifted by one and the read/write bit*/
|
||||
IOWR_I2C_OPENCORES_TXR(base, ((add<<1) + (0x1 & read)));
|
||||
|
||||
/* set start and write bits which will start the transaction*/
|
||||
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_STA_MSK | I2C_OPENCORES_CR_WR_MSK );
|
||||
|
||||
/* wait for the trnasaction to be over.*/
|
||||
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
|
||||
|
||||
/* now check to see if the address was acknowledged */
|
||||
if(IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_RXNACK_MSK)
|
||||
{
|
||||
#ifdef I2C_DEBUG
|
||||
printf("\tNOACK\n");
|
||||
#endif
|
||||
return (I2C_NOACK);
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef I2C_DEBUG
|
||||
printf("\tACK\n");
|
||||
#endif
|
||||
return (I2C_ACK);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************
|
||||
int I2C_read
|
||||
assumes that any addressing and start
|
||||
has already been done.
|
||||
reads one byte of data from the slave. on the last read
|
||||
we don't acknowldge and set the stop bit.
|
||||
inputs
|
||||
base = the base address of the component
|
||||
last = on the last read there must not be a ack
|
||||
|
||||
return value
|
||||
byte read back.
|
||||
15-OCT-07 initial release
|
||||
*****************************************************************/
|
||||
alt_u32 I2C_read(alt_u32 base,alt_u32 last)
|
||||
{
|
||||
#ifdef I2C_DEBUG
|
||||
printf(" Read I2C at 0x%x, \n\twith last0x%x\n",base,last);
|
||||
#endif
|
||||
if( last)
|
||||
{
|
||||
/* start a read and no ack and stop bit*/
|
||||
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_RD_MSK |
|
||||
I2C_OPENCORES_CR_NACK_MSK | I2C_OPENCORES_CR_STO_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* start read*/
|
||||
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_RD_MSK );
|
||||
}
|
||||
/* wait for the trnasaction to be over.*/
|
||||
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
|
||||
|
||||
/* now read the data */
|
||||
return (IORD_I2C_OPENCORES_RXR(base));
|
||||
|
||||
}
|
||||
|
||||
/****************************************************************
|
||||
int I2C_write
|
||||
assumes that any addressing and start
|
||||
has already been done.
|
||||
writes one byte of data from the slave.
|
||||
If last is set the stop bit set.
|
||||
inputs
|
||||
base = the base address of the component
|
||||
data = byte to write
|
||||
last = on the last read there must not be a ack
|
||||
|
||||
return value
|
||||
0 if address is acknowledged
|
||||
1 if address was not acknowledged
|
||||
15-OCT-07 initial release
|
||||
*****************************************************************/
|
||||
alt_u32 I2C_write(alt_u32 base,alt_u8 data, alt_u32 last)
|
||||
{
|
||||
#ifdef I2C_DEBUG
|
||||
printf(" Read I2C at 0x%x, \n\twith data 0x%x,\n\twith last0x%x\n",base,data,last);
|
||||
#endif
|
||||
/* transmit the data*/
|
||||
IOWR_I2C_OPENCORES_TXR(base, data);
|
||||
|
||||
if( last)
|
||||
{
|
||||
/* start a read and no ack and stop bit*/
|
||||
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_WR_MSK |
|
||||
I2C_OPENCORES_CR_STO_MSK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* start read*/
|
||||
IOWR_I2C_OPENCORES_CR(base, I2C_OPENCORES_CR_WR_MSK );
|
||||
}
|
||||
/* wait for the trnasaction to be over.*/
|
||||
while( IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_TIP_MSK);
|
||||
|
||||
/* now check to see if the address was acknowledged */
|
||||
if(IORD_I2C_OPENCORES_SR(base) & I2C_OPENCORES_SR_RXNACK_MSK)
|
||||
{
|
||||
#ifdef I2C_DEBUG
|
||||
printf("\tNOACK\n");
|
||||
#endif
|
||||
return (I2C_NOACK);
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef I2C_DEBUG
|
||||
printf("\tACK\n");
|
||||
#endif
|
||||
return (I2C_ACK);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,540 @@
|
|||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// Author: Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// www.asics.ws ////
|
||||
//// ////
|
||||
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2001 Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer.////
|
||||
//// ////
|
||||
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
||||
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
||||
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
||||
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
||||
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
||||
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
||||
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
||||
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
||||
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
||||
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
||||
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
||||
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
||||
//// POSSIBILITY OF SUCH DAMAGE. ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
// CVS Log
|
||||
//
|
||||
// $Id: i2c_master_bit_ctrl.v,v 1.11 2004/05/07 11:02:26 rherveille Exp $
|
||||
//
|
||||
// $Date: 2004/05/07 11:02:26 $
|
||||
// $Revision: 1.11 $
|
||||
// $Author: rherveille $
|
||||
// $Locker: $
|
||||
// $State: Exp $
|
||||
//
|
||||
// Change History:
|
||||
// $Log: i2c_master_bit_ctrl.v,v $
|
||||
// Revision 1.11 2004/05/07 11:02:26 rherveille
|
||||
// Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
|
||||
//
|
||||
// Revision 1.10 2003/08/09 07:01:33 rherveille
|
||||
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
|
||||
// Fixed a potential bug in the byte controller's host-acknowledge generation.
|
||||
//
|
||||
// Revision 1.9 2003/03/10 14:26:37 rherveille
|
||||
// Fixed cmd_ack generation item (no bug).
|
||||
//
|
||||
// Revision 1.8 2003/02/05 00:06:10 rherveille
|
||||
// Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
|
||||
//
|
||||
// Revision 1.7 2002/12/26 16:05:12 rherveille
|
||||
// Small code simplifications
|
||||
//
|
||||
// Revision 1.6 2002/12/26 15:02:32 rherveille
|
||||
// Core is now a Multimaster I2C controller
|
||||
//
|
||||
// Revision 1.5 2002/11/30 22:24:40 rherveille
|
||||
// Cleaned up code
|
||||
//
|
||||
// Revision 1.4 2002/10/30 18:10:07 rherveille
|
||||
// Fixed some reported minor start/stop generation timing issuess.
|
||||
//
|
||||
// Revision 1.3 2002/06/15 07:37:03 rherveille
|
||||
// Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
|
||||
//
|
||||
// Revision 1.2 2001/11/05 11:59:25 rherveille
|
||||
// Fixed wb_ack_o generation bug.
|
||||
// Fixed bug in the byte_controller statemachine.
|
||||
// Added headers.
|
||||
//
|
||||
|
||||
//
|
||||
/////////////////////////////////////
|
||||
// Bit controller section
|
||||
/////////////////////////////////////
|
||||
//
|
||||
// Translate simple commands into SCL/SDA transitions
|
||||
// Each command has 5 states, A/B/C/D/idle
|
||||
//
|
||||
// start: SCL ~~~~~~~~~~\____
|
||||
// SDA ~~~~~~~~\______
|
||||
// x | A | B | C | D | i
|
||||
//
|
||||
// repstart SCL ____/~~~~\___
|
||||
// SDA __/~~~\______
|
||||
// x | A | B | C | D | i
|
||||
//
|
||||
// stop SCL ____/~~~~~~~~
|
||||
// SDA ==\____/~~~~~
|
||||
// x | A | B | C | D | i
|
||||
//
|
||||
//- write SCL ____/~~~~\____
|
||||
// SDA ==X=========X=
|
||||
// x | A | B | C | D | i
|
||||
//
|
||||
//- read SCL ____/~~~~\____
|
||||
// SDA XXXX=====XXXX
|
||||
// x | A | B | C | D | i
|
||||
//
|
||||
|
||||
// Timing: Normal mode Fast mode
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
// Fscl 100KHz 400KHz
|
||||
// Th_scl 4.0us 0.6us High period of SCL
|
||||
// Tl_scl 4.7us 1.3us Low period of SCL
|
||||
// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
|
||||
// Tsu:sto 4.0us 0.6us setup time for a stop conditon
|
||||
// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
|
||||
//
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
|
||||
`include "i2c_master_defines.v"
|
||||
|
||||
module i2c_master_bit_ctrl(
|
||||
clk, rst, nReset,
|
||||
clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
|
||||
scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
|
||||
);
|
||||
|
||||
//
|
||||
// inputs & outputs
|
||||
//
|
||||
input clk;
|
||||
input rst;
|
||||
input nReset;
|
||||
input ena; // core enable signal
|
||||
|
||||
input [15:0] clk_cnt; // clock prescale value
|
||||
|
||||
input [3:0] cmd;
|
||||
output cmd_ack; // command complete acknowledge
|
||||
reg cmd_ack;
|
||||
output busy; // i2c bus busy
|
||||
reg busy;
|
||||
output al; // i2c bus arbitration lost
|
||||
reg al;
|
||||
|
||||
input din;
|
||||
output dout;
|
||||
reg dout;
|
||||
|
||||
// I2C lines
|
||||
input scl_i; // i2c clock line input
|
||||
output scl_o; // i2c clock line output
|
||||
output scl_oen; // i2c clock line output enable (active low)
|
||||
reg scl_oen;
|
||||
input sda_i; // i2c data line input
|
||||
output sda_o; // i2c data line output
|
||||
output sda_oen; // i2c data line output enable (active low)
|
||||
reg sda_oen;
|
||||
|
||||
|
||||
//
|
||||
// variable declarations
|
||||
//
|
||||
|
||||
reg sSCL, sSDA; // synchronized SCL and SDA inputs
|
||||
reg dscl_oen; // delayed scl_oen
|
||||
reg sda_chk; // check SDA output (Multi-master arbitration)
|
||||
reg clk_en; // clock generation signals
|
||||
wire slave_wait;
|
||||
// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
|
||||
reg [15:0] cnt; // clock divider counter (synthesis)
|
||||
|
||||
// state machine variable
|
||||
reg [16:0] c_state;
|
||||
|
||||
//
|
||||
// module body
|
||||
//
|
||||
|
||||
// whenever the slave is not ready it can delay the cycle by pulling SCL low
|
||||
// delay scl_oen
|
||||
always @(posedge clk)
|
||||
dscl_oen <= #1 scl_oen;
|
||||
|
||||
assign slave_wait = dscl_oen && !sSCL;
|
||||
|
||||
|
||||
// generate clk enable signal
|
||||
always @(posedge clk or negedge nReset)
|
||||
if(~nReset)
|
||||
begin
|
||||
cnt <= #1 16'h0;
|
||||
clk_en <= #1 1'b1;
|
||||
end
|
||||
else if (rst)
|
||||
begin
|
||||
cnt <= #1 16'h0;
|
||||
clk_en <= #1 1'b1;
|
||||
end
|
||||
else if ( ~|cnt || ~ena)
|
||||
if (~slave_wait)
|
||||
begin
|
||||
cnt <= #1 clk_cnt;
|
||||
clk_en <= #1 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cnt <= #1 cnt;
|
||||
clk_en <= #1 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cnt <= #1 cnt - 16'h1;
|
||||
clk_en <= #1 1'b0;
|
||||
end
|
||||
|
||||
|
||||
// generate bus status controller
|
||||
reg dSCL, dSDA;
|
||||
reg sta_condition;
|
||||
reg sto_condition;
|
||||
|
||||
// synchronize SCL and SDA inputs
|
||||
// reduce metastability risc
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (~nReset)
|
||||
begin
|
||||
sSCL <= #1 1'b1;
|
||||
sSDA <= #1 1'b1;
|
||||
|
||||
dSCL <= #1 1'b1;
|
||||
dSDA <= #1 1'b1;
|
||||
end
|
||||
else if (rst)
|
||||
begin
|
||||
sSCL <= #1 1'b1;
|
||||
sSDA <= #1 1'b1;
|
||||
|
||||
dSCL <= #1 1'b1;
|
||||
dSDA <= #1 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
sSCL <= #1 scl_i;
|
||||
sSDA <= #1 sda_i;
|
||||
|
||||
dSCL <= #1 sSCL;
|
||||
dSDA <= #1 sSDA;
|
||||
end
|
||||
|
||||
// detect start condition => detect falling edge on SDA while SCL is high
|
||||
// detect stop condition => detect rising edge on SDA while SCL is high
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (~nReset)
|
||||
begin
|
||||
sta_condition <= #1 1'b0;
|
||||
sto_condition <= #1 1'b0;
|
||||
end
|
||||
else if (rst)
|
||||
begin
|
||||
sta_condition <= #1 1'b0;
|
||||
sto_condition <= #1 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
sta_condition <= #1 ~sSDA & dSDA & sSCL;
|
||||
sto_condition <= #1 sSDA & ~dSDA & sSCL;
|
||||
end
|
||||
|
||||
// generate i2c bus busy signal
|
||||
always @(posedge clk or negedge nReset)
|
||||
if(!nReset)
|
||||
busy <= #1 1'b0;
|
||||
else if (rst)
|
||||
busy <= #1 1'b0;
|
||||
else
|
||||
busy <= #1 (sta_condition | busy) & ~sto_condition;
|
||||
|
||||
// generate arbitration lost signal
|
||||
// aribitration lost when:
|
||||
// 1) master drives SDA high, but the i2c bus is low
|
||||
// 2) stop detected while not requested
|
||||
reg cmd_stop;
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (~nReset)
|
||||
cmd_stop <= #1 1'b0;
|
||||
else if (rst)
|
||||
cmd_stop <= #1 1'b0;
|
||||
else if (clk_en)
|
||||
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
|
||||
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (~nReset)
|
||||
al <= #1 1'b0;
|
||||
else if (rst)
|
||||
al <= #1 1'b0;
|
||||
else
|
||||
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
|
||||
|
||||
|
||||
// generate dout signal (store SDA on rising edge of SCL)
|
||||
always @(posedge clk)
|
||||
if(sSCL & ~dSCL)
|
||||
dout <= #1 sSDA;
|
||||
|
||||
// generate statemachine
|
||||
|
||||
// nxt_state decoder
|
||||
parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
|
||||
parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
|
||||
parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
|
||||
parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
|
||||
parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
|
||||
parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
|
||||
parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000;
|
||||
parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000;
|
||||
parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000;
|
||||
parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000;
|
||||
parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000;
|
||||
parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000;
|
||||
parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000;
|
||||
parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000;
|
||||
parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
|
||||
parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
|
||||
parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
|
||||
parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
|
||||
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (!nReset)
|
||||
begin
|
||||
c_state <= #1 idle;
|
||||
cmd_ack <= #1 1'b0;
|
||||
scl_oen <= #1 1'b1;
|
||||
sda_oen <= #1 1'b1;
|
||||
sda_chk <= #1 1'b0;
|
||||
end
|
||||
else if (rst | al)
|
||||
begin
|
||||
c_state <= #1 idle;
|
||||
cmd_ack <= #1 1'b0;
|
||||
scl_oen <= #1 1'b1;
|
||||
sda_oen <= #1 1'b1;
|
||||
sda_chk <= #1 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
|
||||
|
||||
if (clk_en)
|
||||
case (c_state)
|
||||
// idle state
|
||||
idle:
|
||||
begin
|
||||
case (cmd)
|
||||
`I2C_CMD_START:
|
||||
c_state <= #1 start_a;
|
||||
|
||||
`I2C_CMD_STOP:
|
||||
c_state <= #1 stop_a;
|
||||
|
||||
`I2C_CMD_WRITE:
|
||||
c_state <= #1 wr_a;
|
||||
|
||||
`I2C_CMD_READ:
|
||||
c_state <= #1 rd_a;
|
||||
|
||||
default:
|
||||
c_state <= #1 idle;
|
||||
endcase
|
||||
|
||||
scl_oen <= #1 scl_oen; // keep SCL in same state
|
||||
sda_oen <= #1 sda_oen; // keep SDA in same state
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
// start
|
||||
start_a:
|
||||
begin
|
||||
c_state <= #1 start_b;
|
||||
scl_oen <= #1 scl_oen; // keep SCL in same state
|
||||
sda_oen <= #1 1'b1; // set SDA high
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
start_b:
|
||||
begin
|
||||
c_state <= #1 start_c;
|
||||
scl_oen <= #1 1'b1; // set SCL high
|
||||
sda_oen <= #1 1'b1; // keep SDA high
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
start_c:
|
||||
begin
|
||||
c_state <= #1 start_d;
|
||||
scl_oen <= #1 1'b1; // keep SCL high
|
||||
sda_oen <= #1 1'b0; // set SDA low
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
start_d:
|
||||
begin
|
||||
c_state <= #1 start_e;
|
||||
scl_oen <= #1 1'b1; // keep SCL high
|
||||
sda_oen <= #1 1'b0; // keep SDA low
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
start_e:
|
||||
begin
|
||||
c_state <= #1 idle;
|
||||
cmd_ack <= #1 1'b1;
|
||||
scl_oen <= #1 1'b0; // set SCL low
|
||||
sda_oen <= #1 1'b0; // keep SDA low
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
// stop
|
||||
stop_a:
|
||||
begin
|
||||
c_state <= #1 stop_b;
|
||||
scl_oen <= #1 1'b0; // keep SCL low
|
||||
sda_oen <= #1 1'b0; // set SDA low
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
stop_b:
|
||||
begin
|
||||
c_state <= #1 stop_c;
|
||||
scl_oen <= #1 1'b1; // set SCL high
|
||||
sda_oen <= #1 1'b0; // keep SDA low
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
stop_c:
|
||||
begin
|
||||
c_state <= #1 stop_d;
|
||||
scl_oen <= #1 1'b1; // keep SCL high
|
||||
sda_oen <= #1 1'b0; // keep SDA low
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
stop_d:
|
||||
begin
|
||||
c_state <= #1 idle;
|
||||
cmd_ack <= #1 1'b1;
|
||||
scl_oen <= #1 1'b1; // keep SCL high
|
||||
sda_oen <= #1 1'b1; // set SDA high
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
// read
|
||||
rd_a:
|
||||
begin
|
||||
c_state <= #1 rd_b;
|
||||
scl_oen <= #1 1'b0; // keep SCL low
|
||||
sda_oen <= #1 1'b1; // tri-state SDA
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
rd_b:
|
||||
begin
|
||||
c_state <= #1 rd_c;
|
||||
scl_oen <= #1 1'b1; // set SCL high
|
||||
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
rd_c:
|
||||
begin
|
||||
c_state <= #1 rd_d;
|
||||
scl_oen <= #1 1'b1; // keep SCL high
|
||||
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
rd_d:
|
||||
begin
|
||||
c_state <= #1 idle;
|
||||
cmd_ack <= #1 1'b1;
|
||||
scl_oen <= #1 1'b0; // set SCL low
|
||||
sda_oen <= #1 1'b1; // keep SDA tri-stated
|
||||
sda_chk <= #1 1'b0; // don't check SDA output
|
||||
end
|
||||
|
||||
// write
|
||||
wr_a:
|
||||
begin
|
||||
c_state <= #1 wr_b;
|
||||
scl_oen <= #1 1'b0; // keep SCL low
|
||||
sda_oen <= #1 din; // set SDA
|
||||
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
||||
end
|
||||
|
||||
wr_b:
|
||||
begin
|
||||
c_state <= #1 wr_c;
|
||||
scl_oen <= #1 1'b1; // set SCL high
|
||||
sda_oen <= #1 din; // keep SDA
|
||||
sda_chk <= #1 1'b1; // check SDA output
|
||||
end
|
||||
|
||||
wr_c:
|
||||
begin
|
||||
c_state <= #1 wr_d;
|
||||
scl_oen <= #1 1'b1; // keep SCL high
|
||||
sda_oen <= #1 din;
|
||||
sda_chk <= #1 1'b1; // check SDA output
|
||||
end
|
||||
|
||||
wr_d:
|
||||
begin
|
||||
c_state <= #1 idle;
|
||||
cmd_ack <= #1 1'b1;
|
||||
scl_oen <= #1 1'b0; // set SCL low
|
||||
sda_oen <= #1 din;
|
||||
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
|
||||
end
|
||||
|
||||
default:
|
||||
c_state <= #1 idle;
|
||||
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
// assign scl and sda output (always gnd)
|
||||
wire scl_o/* synthesis keep */;
|
||||
wire sda_o/* synthesis keep */;
|
||||
assign scl_o = 1'b0;
|
||||
assign sda_o = 1'b0;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,344 @@
|
|||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// WISHBONE rev.B2 compliant I2C Master byte-controller ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// Author: Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// www.asics.ws ////
|
||||
//// ////
|
||||
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2001 Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer.////
|
||||
//// ////
|
||||
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
||||
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
||||
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
||||
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
||||
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
||||
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
||||
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
||||
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
||||
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
||||
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
||||
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
||||
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
||||
//// POSSIBILITY OF SUCH DAMAGE. ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
// CVS Log
|
||||
//
|
||||
// $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
|
||||
//
|
||||
// $Date: 2004/02/18 11:40:46 $
|
||||
// $Revision: 1.7 $
|
||||
// $Author: rherveille $
|
||||
// $Locker: $
|
||||
// $State: Exp $
|
||||
//
|
||||
// Change History:
|
||||
// $Log: i2c_master_byte_ctrl.v,v $
|
||||
// Revision 1.7 2004/02/18 11:40:46 rherveille
|
||||
// Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
|
||||
//
|
||||
// Revision 1.6 2003/08/09 07:01:33 rherveille
|
||||
// Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
|
||||
// Fixed a potential bug in the byte controller's host-acknowledge generation.
|
||||
//
|
||||
// Revision 1.5 2002/12/26 15:02:32 rherveille
|
||||
// Core is now a Multimaster I2C controller
|
||||
//
|
||||
// Revision 1.4 2002/11/30 22:24:40 rherveille
|
||||
// Cleaned up code
|
||||
//
|
||||
// Revision 1.3 2001/11/05 11:59:25 rherveille
|
||||
// Fixed wb_ack_o generation bug.
|
||||
// Fixed bug in the byte_controller statemachine.
|
||||
// Added headers.
|
||||
//
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
|
||||
`include "i2c_master_defines.v"
|
||||
|
||||
module i2c_master_byte_ctrl (
|
||||
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
|
||||
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
|
||||
|
||||
//
|
||||
// inputs & outputs
|
||||
//
|
||||
input clk; // master clock
|
||||
input rst; // synchronous active high reset
|
||||
input nReset; // asynchronous active low reset
|
||||
input ena; // core enable signal
|
||||
|
||||
input [15:0] clk_cnt; // 4x SCL
|
||||
|
||||
// control inputs
|
||||
input start;
|
||||
input stop;
|
||||
input read;
|
||||
input write;
|
||||
input ack_in;
|
||||
input [7:0] din;
|
||||
|
||||
// status outputs
|
||||
output cmd_ack;
|
||||
reg cmd_ack;
|
||||
output ack_out;
|
||||
reg ack_out;
|
||||
output i2c_busy;
|
||||
output i2c_al;
|
||||
output [7:0] dout;
|
||||
|
||||
// I2C signals
|
||||
input scl_i;
|
||||
output scl_o;
|
||||
output scl_oen;
|
||||
input sda_i;
|
||||
output sda_o;
|
||||
output sda_oen;
|
||||
|
||||
|
||||
//
|
||||
// Variable declarations
|
||||
//
|
||||
|
||||
// statemachine
|
||||
parameter [4:0] ST_IDLE = 5'b0_0000;
|
||||
parameter [4:0] ST_START = 5'b0_0001;
|
||||
parameter [4:0] ST_READ = 5'b0_0010;
|
||||
parameter [4:0] ST_WRITE = 5'b0_0100;
|
||||
parameter [4:0] ST_ACK = 5'b0_1000;
|
||||
parameter [4:0] ST_STOP = 5'b1_0000;
|
||||
|
||||
// signals for bit_controller
|
||||
reg [3:0] core_cmd;
|
||||
reg core_txd;
|
||||
wire core_ack, core_rxd;
|
||||
|
||||
// signals for shift register
|
||||
reg [7:0] sr; //8bit shift register
|
||||
reg shift, ld;
|
||||
|
||||
// signals for state machine
|
||||
wire go;
|
||||
reg [2:0] dcnt;
|
||||
wire cnt_done;
|
||||
|
||||
//
|
||||
// Module body
|
||||
//
|
||||
|
||||
// hookup bit_controller
|
||||
i2c_master_bit_ctrl bit_controller (
|
||||
.clk ( clk ),
|
||||
.rst ( rst ),
|
||||
.nReset ( nReset ),
|
||||
.ena ( ena ),
|
||||
.clk_cnt ( clk_cnt ),
|
||||
.cmd ( core_cmd ),
|
||||
.cmd_ack ( core_ack ),
|
||||
.busy ( i2c_busy ),
|
||||
.al ( i2c_al ),
|
||||
.din ( core_txd ),
|
||||
.dout ( core_rxd ),
|
||||
.scl_i ( scl_i ),
|
||||
.scl_o ( scl_o ),
|
||||
.scl_oen ( scl_oen ),
|
||||
.sda_i ( sda_i ),
|
||||
.sda_o ( sda_o ),
|
||||
.sda_oen ( sda_oen )
|
||||
);
|
||||
|
||||
// generate go-signal
|
||||
assign go = (read | write | stop) & ~cmd_ack;
|
||||
|
||||
// assign dout output to shift-register
|
||||
assign dout = sr;
|
||||
|
||||
// generate shift register
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (!nReset)
|
||||
sr <= #1 8'h0;
|
||||
else if (rst)
|
||||
sr <= #1 8'h0;
|
||||
else if (ld)
|
||||
sr <= #1 din;
|
||||
else if (shift)
|
||||
sr <= #1 {sr[6:0], core_rxd};
|
||||
|
||||
// generate counter
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (!nReset)
|
||||
dcnt <= #1 3'h0;
|
||||
else if (rst)
|
||||
dcnt <= #1 3'h0;
|
||||
else if (ld)
|
||||
dcnt <= #1 3'h7;
|
||||
else if (shift)
|
||||
dcnt <= #1 dcnt - 3'h1;
|
||||
|
||||
assign cnt_done = ~(|dcnt);
|
||||
|
||||
//
|
||||
// state machine
|
||||
//
|
||||
reg [4:0] c_state; // synopsis enum_state
|
||||
|
||||
always @(posedge clk or negedge nReset)
|
||||
if (!nReset)
|
||||
begin
|
||||
core_cmd <= #1 `I2C_CMD_NOP;
|
||||
core_txd <= #1 1'b0;
|
||||
shift <= #1 1'b0;
|
||||
ld <= #1 1'b0;
|
||||
cmd_ack <= #1 1'b0;
|
||||
c_state <= #1 ST_IDLE;
|
||||
ack_out <= #1 1'b0;
|
||||
end
|
||||
else if (rst | i2c_al)
|
||||
begin
|
||||
core_cmd <= #1 `I2C_CMD_NOP;
|
||||
core_txd <= #1 1'b0;
|
||||
shift <= #1 1'b0;
|
||||
ld <= #1 1'b0;
|
||||
cmd_ack <= #1 1'b0;
|
||||
c_state <= #1 ST_IDLE;
|
||||
ack_out <= #1 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// initially reset all signals
|
||||
core_txd <= #1 sr[7];
|
||||
shift <= #1 1'b0;
|
||||
ld <= #1 1'b0;
|
||||
cmd_ack <= #1 1'b0;
|
||||
|
||||
case (c_state) // synopsys full_case parallel_case
|
||||
ST_IDLE:
|
||||
if (go)
|
||||
begin
|
||||
if (start)
|
||||
begin
|
||||
c_state <= #1 ST_START;
|
||||
core_cmd <= #1 `I2C_CMD_START;
|
||||
end
|
||||
else if (read)
|
||||
begin
|
||||
c_state <= #1 ST_READ;
|
||||
core_cmd <= #1 `I2C_CMD_READ;
|
||||
end
|
||||
else if (write)
|
||||
begin
|
||||
c_state <= #1 ST_WRITE;
|
||||
core_cmd <= #1 `I2C_CMD_WRITE;
|
||||
end
|
||||
else // stop
|
||||
begin
|
||||
c_state <= #1 ST_STOP;
|
||||
core_cmd <= #1 `I2C_CMD_STOP;
|
||||
end
|
||||
|
||||
ld <= #1 1'b1;
|
||||
end
|
||||
|
||||
ST_START:
|
||||
if (core_ack)
|
||||
begin
|
||||
if (read)
|
||||
begin
|
||||
c_state <= #1 ST_READ;
|
||||
core_cmd <= #1 `I2C_CMD_READ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
c_state <= #1 ST_WRITE;
|
||||
core_cmd <= #1 `I2C_CMD_WRITE;
|
||||
end
|
||||
|
||||
ld <= #1 1'b1;
|
||||
end
|
||||
|
||||
ST_WRITE:
|
||||
if (core_ack)
|
||||
if (cnt_done)
|
||||
begin
|
||||
c_state <= #1 ST_ACK;
|
||||
core_cmd <= #1 `I2C_CMD_READ;
|
||||
end
|
||||
else
|
||||
begin
|
||||
c_state <= #1 ST_WRITE; // stay in same state
|
||||
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
|
||||
shift <= #1 1'b1;
|
||||
end
|
||||
|
||||
ST_READ:
|
||||
if (core_ack)
|
||||
begin
|
||||
if (cnt_done)
|
||||
begin
|
||||
c_state <= #1 ST_ACK;
|
||||
core_cmd <= #1 `I2C_CMD_WRITE;
|
||||
end
|
||||
else
|
||||
begin
|
||||
c_state <= #1 ST_READ; // stay in same state
|
||||
core_cmd <= #1 `I2C_CMD_READ; // read next bit
|
||||
end
|
||||
|
||||
shift <= #1 1'b1;
|
||||
core_txd <= #1 ack_in;
|
||||
end
|
||||
|
||||
ST_ACK:
|
||||
if (core_ack)
|
||||
begin
|
||||
if (stop)
|
||||
begin
|
||||
c_state <= #1 ST_STOP;
|
||||
core_cmd <= #1 `I2C_CMD_STOP;
|
||||
end
|
||||
else
|
||||
begin
|
||||
c_state <= #1 ST_IDLE;
|
||||
core_cmd <= #1 `I2C_CMD_NOP;
|
||||
|
||||
// generate command acknowledge signal
|
||||
cmd_ack <= #1 1'b1;
|
||||
end
|
||||
|
||||
// assign ack_out output to bit_controller_rxd (contains last received bit)
|
||||
ack_out <= #1 core_rxd;
|
||||
|
||||
core_txd <= #1 1'b1;
|
||||
end
|
||||
else
|
||||
core_txd <= #1 ack_in;
|
||||
|
||||
ST_STOP:
|
||||
if (core_ack)
|
||||
begin
|
||||
c_state <= #1 ST_IDLE;
|
||||
core_cmd <= #1 `I2C_CMD_NOP;
|
||||
|
||||
// generate command acknowledge signal
|
||||
cmd_ack <= #1 1'b1;
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// WISHBONE rev.B2 compliant I2C Master controller defines ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// Author: Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// www.asics.ws ////
|
||||
//// ////
|
||||
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2001 Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer.////
|
||||
//// ////
|
||||
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
||||
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
||||
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
||||
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
||||
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
||||
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
||||
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
||||
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
||||
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
||||
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
||||
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
||||
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
||||
//// POSSIBILITY OF SUCH DAMAGE. ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
// CVS Log
|
||||
//
|
||||
// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $
|
||||
//
|
||||
// $Date: 2001/11/05 11:59:25 $
|
||||
// $Revision: 1.3 $
|
||||
// $Author: rherveille $
|
||||
// $Locker: $
|
||||
// $State: Exp $
|
||||
//
|
||||
// Change History:
|
||||
// $Log: i2c_master_defines.v,v $
|
||||
// Revision 1.3 2001/11/05 11:59:25 rherveille
|
||||
// Fixed wb_ack_o generation bug.
|
||||
// Fixed bug in the byte_controller statemachine.
|
||||
// Added headers.
|
||||
//
|
||||
|
||||
|
||||
// I2C registers wishbone addresses
|
||||
|
||||
// bitcontroller states
|
||||
`define I2C_CMD_NOP 4'b0000
|
||||
`define I2C_CMD_START 4'b0001
|
||||
`define I2C_CMD_STOP 4'b0010
|
||||
`define I2C_CMD_WRITE 4'b0100
|
||||
`define I2C_CMD_READ 4'b1000
|
||||
296
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/i2c_master_top.v
Normal file
296
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/i2c_master_top.v
Normal file
|
|
@ -0,0 +1,296 @@
|
|||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
|
||||
//// ////
|
||||
//// ////
|
||||
//// Author: Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// www.asics.ws ////
|
||||
//// ////
|
||||
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
//// ////
|
||||
//// Copyright (C) 2001 Richard Herveille ////
|
||||
//// richard@asics.ws ////
|
||||
//// ////
|
||||
//// This source file may be used and distributed without ////
|
||||
//// restriction provided that this copyright statement is not ////
|
||||
//// removed from the file and that any derivative work contains ////
|
||||
//// the original copyright notice and the associated disclaimer.////
|
||||
//// ////
|
||||
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
|
||||
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
|
||||
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
|
||||
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
|
||||
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
|
||||
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
|
||||
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
|
||||
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
|
||||
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
|
||||
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
|
||||
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
|
||||
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
|
||||
//// POSSIBILITY OF SUCH DAMAGE. ////
|
||||
//// ////
|
||||
/////////////////////////////////////////////////////////////////////
|
||||
|
||||
// CVS Log
|
||||
//
|
||||
// $Id: i2c_master_top.v,v 1.10 2003/09/01 10:34:38 rherveille Exp $
|
||||
//
|
||||
// $Date: 2003/09/01 10:34:38 $
|
||||
// $Revision: 1.10 $
|
||||
// $Author: rherveille $
|
||||
// $Locker: $
|
||||
// $State: Exp $
|
||||
//
|
||||
// Change History:
|
||||
// $Log: i2c_master_top.v,v $
|
||||
// Revision 1.10 2003/09/01 10:34:38 rherveille
|
||||
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
|
||||
//
|
||||
// Revision 1.9 2003/01/09 16:44:45 rherveille
|
||||
// Fixed a bug in the Command Register declaration.
|
||||
//
|
||||
// Revision 1.8 2002/12/26 16:05:12 rherveille
|
||||
// Small code simplifications
|
||||
//
|
||||
// Revision 1.7 2002/12/26 15:02:32 rherveille
|
||||
// Core is now a Multimaster I2C controller
|
||||
//
|
||||
// Revision 1.6 2002/11/30 22:24:40 rherveille
|
||||
// Cleaned up code
|
||||
//
|
||||
// Revision 1.5 2001/11/10 10:52:55 rherveille
|
||||
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
|
||||
//
|
||||
|
||||
// synopsys translate_off
|
||||
`include "timescale.v"
|
||||
// synopsys translate_on
|
||||
|
||||
`include "i2c_master_defines.v"
|
||||
|
||||
module i2c_master_top(
|
||||
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
|
||||
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
|
||||
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
|
||||
|
||||
// parameters
|
||||
parameter ARST_LVL = 1'b0; // asynchronous reset level
|
||||
|
||||
//
|
||||
// inputs & outputs
|
||||
//
|
||||
|
||||
// wishbone signals
|
||||
input wb_clk_i; // master clock input
|
||||
input wb_rst_i; // synchronous active high reset
|
||||
input arst_i; // asynchronous reset
|
||||
input [2:0] wb_adr_i; // lower address bits
|
||||
input [7:0] wb_dat_i; // databus input
|
||||
output [7:0] wb_dat_o; // databus output
|
||||
input wb_we_i; // write enable input
|
||||
input wb_stb_i; // stobe/core select signal
|
||||
input wb_cyc_i; // valid bus cycle input
|
||||
output wb_ack_o; // bus cycle acknowledge output
|
||||
output wb_inta_o; // interrupt request signal output
|
||||
|
||||
reg [7:0] wb_dat_o;
|
||||
reg wb_ack_o;
|
||||
reg wb_inta_o;
|
||||
|
||||
// I2C signals
|
||||
// i2c clock line
|
||||
input scl_pad_i; // SCL-line input
|
||||
output scl_pad_o; // SCL-line output (always 1'b0)
|
||||
output scl_padoen_o; // SCL-line output enable (active low)
|
||||
|
||||
// i2c data line
|
||||
input sda_pad_i; // SDA-line input
|
||||
output sda_pad_o; // SDA-line output (always 1'b0)
|
||||
output sda_padoen_o; // SDA-line output enable (active low)
|
||||
|
||||
|
||||
//
|
||||
// variable declarations
|
||||
//
|
||||
|
||||
// registers
|
||||
reg [15:0] prer; // clock prescale register
|
||||
reg [ 7:0] ctr; // control register
|
||||
reg [ 7:0] txr; // transmit register
|
||||
wire [ 7:0] rxr; // receive register
|
||||
reg [ 7:0] cr; // command register
|
||||
wire [ 7:0] sr; // status register
|
||||
|
||||
// done signal: command completed, clear command register
|
||||
wire done;
|
||||
|
||||
// core enable signal
|
||||
wire core_en;
|
||||
wire ien;
|
||||
|
||||
// status register signals
|
||||
wire irxack;
|
||||
reg rxack; // received aknowledge from slave
|
||||
reg tip; // transfer in progress
|
||||
reg irq_flag; // interrupt pending flag
|
||||
wire i2c_busy; // bus busy (start signal detected)
|
||||
wire i2c_al; // i2c bus arbitration lost
|
||||
reg al; // status register arbitration lost bit
|
||||
|
||||
//
|
||||
// module body
|
||||
//
|
||||
|
||||
// generate internal reset
|
||||
wire rst_i = arst_i ^ ARST_LVL;
|
||||
|
||||
// generate wishbone signals
|
||||
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
|
||||
|
||||
// generate acknowledge output signal
|
||||
always @(posedge wb_clk_i)
|
||||
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
|
||||
|
||||
// assign DAT_O
|
||||
always @(posedge wb_clk_i)
|
||||
begin
|
||||
case (wb_adr_i) // synopsis full_case parallel_case
|
||||
3'b000: wb_dat_o <= #1 prer[ 7:0];
|
||||
3'b001: wb_dat_o <= #1 prer[15:8];
|
||||
3'b010: wb_dat_o <= #1 ctr;
|
||||
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
|
||||
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
|
||||
3'b101: wb_dat_o <= #1 txr;
|
||||
3'b110: wb_dat_o <= #1 cr;
|
||||
3'b111: wb_dat_o <= #1 0; // reserved
|
||||
endcase
|
||||
end
|
||||
|
||||
// generate registers
|
||||
always @(posedge wb_clk_i or negedge rst_i)
|
||||
if (!rst_i)
|
||||
begin
|
||||
prer <= #1 16'hffff;
|
||||
ctr <= #1 8'h0;
|
||||
txr <= #1 8'h0;
|
||||
end
|
||||
else if (wb_rst_i)
|
||||
begin
|
||||
prer <= #1 16'hffff;
|
||||
ctr <= #1 8'h0;
|
||||
txr <= #1 8'h0;
|
||||
end
|
||||
else
|
||||
if (wb_wacc)
|
||||
case (wb_adr_i) // synopsis full_case parallel_case
|
||||
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
|
||||
3'b001 : prer [15:8] <= #1 wb_dat_i;
|
||||
3'b010 : ctr <= #1 wb_dat_i;
|
||||
3'b011 : txr <= #1 wb_dat_i;
|
||||
endcase
|
||||
|
||||
// generate command register (special case)
|
||||
always @(posedge wb_clk_i or negedge rst_i)
|
||||
if (~rst_i)
|
||||
cr <= #1 8'h0;
|
||||
else if (wb_rst_i)
|
||||
cr <= #1 8'h0;
|
||||
else if (wb_wacc)
|
||||
begin
|
||||
if (core_en & (wb_adr_i == 3'b100) )
|
||||
cr <= #1 wb_dat_i;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (done | i2c_al)
|
||||
cr[7:4] <= #1 4'h0; // clear command bits when done
|
||||
// or when aribitration lost
|
||||
cr[2:1] <= #1 2'b0; // reserved bits
|
||||
cr[0] <= #1 1'b0; // clear IRQ_ACK bit
|
||||
end
|
||||
|
||||
|
||||
// decode command register
|
||||
wire sta = cr[7];
|
||||
wire sto = cr[6];
|
||||
wire rd = cr[5];
|
||||
wire wr = cr[4];
|
||||
wire ack = cr[3];
|
||||
wire iack = cr[0];
|
||||
|
||||
// decode control register
|
||||
assign core_en = ctr[7];
|
||||
assign ien = ctr[6];
|
||||
|
||||
// hookup byte controller block
|
||||
i2c_master_byte_ctrl byte_controller (
|
||||
.clk ( wb_clk_i ),
|
||||
.rst ( wb_rst_i ),
|
||||
.nReset ( rst_i ),
|
||||
.ena ( core_en ),
|
||||
.clk_cnt ( prer ),
|
||||
.start ( sta ),
|
||||
.stop ( sto ),
|
||||
.read ( rd ),
|
||||
.write ( wr ),
|
||||
.ack_in ( ack ),
|
||||
.din ( txr ),
|
||||
.cmd_ack ( done ),
|
||||
.ack_out ( irxack ),
|
||||
.dout ( rxr ),
|
||||
.i2c_busy ( i2c_busy ),
|
||||
.i2c_al ( i2c_al ),
|
||||
.scl_i ( scl_pad_i ),
|
||||
.scl_o ( scl_pad_o ),
|
||||
.scl_oen ( scl_padoen_o ),
|
||||
.sda_i ( sda_pad_i ),
|
||||
.sda_o ( sda_pad_o ),
|
||||
.sda_oen ( sda_padoen_o )
|
||||
);
|
||||
|
||||
// status register block + interrupt request signal
|
||||
always @(posedge wb_clk_i or negedge rst_i)
|
||||
if (!rst_i)
|
||||
begin
|
||||
al <= #1 1'b0;
|
||||
rxack <= #1 1'b0;
|
||||
tip <= #1 1'b0;
|
||||
irq_flag <= #1 1'b0;
|
||||
end
|
||||
else if (wb_rst_i)
|
||||
begin
|
||||
al <= #1 1'b0;
|
||||
rxack <= #1 1'b0;
|
||||
tip <= #1 1'b0;
|
||||
irq_flag <= #1 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
al <= #1 i2c_al | (al & ~sta);
|
||||
rxack <= #1 irxack;
|
||||
tip <= #1 (rd | wr);
|
||||
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
|
||||
end
|
||||
|
||||
// generate interrupt request signals
|
||||
always @(posedge wb_clk_i or negedge rst_i)
|
||||
if (!rst_i)
|
||||
wb_inta_o <= #1 1'b0;
|
||||
else if (wb_rst_i)
|
||||
wb_inta_o <= #1 1'b0;
|
||||
else
|
||||
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
|
||||
|
||||
// assign status register bits
|
||||
assign sr[7] = rxack;
|
||||
assign sr[6] = i2c_busy;
|
||||
assign sr[5] = al;
|
||||
assign sr[4:2] = 3'h0; // reserved
|
||||
assign sr[1] = tip;
|
||||
assign sr[0] = irq_flag;
|
||||
|
||||
endmodule
|
||||
72
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/i2c_opencores.v
Normal file
72
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/i2c_opencores.v
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
//
|
||||
// fixed for 9.1 jan 21 2010 cruben
|
||||
//
|
||||
//`include "timescale.v"
|
||||
//`include "i2c_master_defines.v"
|
||||
|
||||
module i2c_opencores
|
||||
(
|
||||
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
|
||||
wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
|
||||
scl_pad_io, sda_pad_io
|
||||
);
|
||||
|
||||
|
||||
// Common bus signals
|
||||
input wb_clk_i; // WISHBONE clock
|
||||
input wb_rst_i; // WISHBONE reset
|
||||
|
||||
// Slave signals
|
||||
input [2:0] wb_adr_i; // WISHBONE address input
|
||||
input [7:0] wb_dat_i; // WISHBONE data input
|
||||
output [7:0] wb_dat_o; // WISHBONE data output
|
||||
input wb_we_i; // WISHBONE write enable input
|
||||
input wb_stb_i; // WISHBONE strobe input
|
||||
//input wb_cyc_i; // WISHBONE cycle input
|
||||
output wb_ack_o; // WISHBONE acknowledge output
|
||||
output wb_inta_o; // WISHBONE interrupt output
|
||||
|
||||
// I2C signals
|
||||
inout scl_pad_io; // I2C clock io
|
||||
inout sda_pad_io; // I2C data io
|
||||
|
||||
wire wb_cyc_i; // WISHBONE cycle input
|
||||
// Wire tri-state scl/sda
|
||||
wire scl_pad_i;
|
||||
wire scl_pad_o;
|
||||
wire scl_pad_io;
|
||||
wire scl_padoen_o;
|
||||
|
||||
assign wb_cyc_i = wb_stb_i;
|
||||
assign scl_pad_i = scl_pad_io;
|
||||
assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
|
||||
|
||||
wire sda_pad_i;
|
||||
wire sda_pad_o;
|
||||
wire sda_pad_io;
|
||||
wire sda_padoen_o;
|
||||
|
||||
assign sda_pad_i = sda_pad_io;
|
||||
assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
|
||||
|
||||
// Avalon doesn't have an asynchronous reset
|
||||
// set it to be inactive and just use synchronous reset
|
||||
// reset level is a parameter, 0 is the default (active-low reset)
|
||||
wire arst_i;
|
||||
|
||||
assign arst_i = 1'b1;
|
||||
|
||||
// Connect the top level I2C core
|
||||
i2c_master_top i2c_master_top_inst
|
||||
(
|
||||
.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
|
||||
|
||||
.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
|
||||
.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
|
||||
.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
|
||||
|
||||
.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
|
||||
.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
# TCL File Generated by Component Editor 12.0
|
||||
# Mon Jul 16 09:24:51 CDT 2012
|
||||
# DO NOT MODIFY
|
||||
|
||||
|
||||
#
|
||||
# i2c_opencores "I2C Master (opencores.org)" v12.0
|
||||
# 2012.07.16.09:24:51
|
||||
# I2C Master Peripheral from opencores.org
|
||||
#
|
||||
|
||||
#
|
||||
# request TCL package from ACDS 12.0
|
||||
#
|
||||
package require -exact qsys 12.0
|
||||
|
||||
|
||||
#
|
||||
# module i2c_opencores
|
||||
#
|
||||
set_module_property DESCRIPTION "I2C Master Peripheral from opencores.org"
|
||||
set_module_property NAME i2c_opencores
|
||||
set_module_property VERSION 12.0
|
||||
set_module_property INTERNAL false
|
||||
set_module_property OPAQUE_ADDRESS_MAP true
|
||||
set_module_property GROUP "Interface Protocols/Serial"
|
||||
set_module_property AUTHOR ""
|
||||
set_module_property DISPLAY_NAME "I2C Master (opencores.org)"
|
||||
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
|
||||
set_module_property EDITABLE true
|
||||
set_module_property ANALYZE_HDL AUTO
|
||||
set_module_property REPORT_TO_TALKBACK false
|
||||
set_module_property ALLOW_GREYBOX_GENERATION false
|
||||
|
||||
|
||||
#
|
||||
# file sets
|
||||
#
|
||||
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
|
||||
set_fileset_property quartus_synth TOP_LEVEL i2c_opencores
|
||||
set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
add_fileset_file i2c_opencores.v VERILOG PATH i2c_opencores.v
|
||||
add_fileset_file i2c_master_top.v VERILOG PATH i2c_master_top.v
|
||||
add_fileset_file i2c_master_defines.v VERILOG PATH i2c_master_defines.v
|
||||
add_fileset_file i2c_master_byte_ctrl.v VERILOG PATH i2c_master_byte_ctrl.v
|
||||
add_fileset_file i2c_master_bit_ctrl.v VERILOG PATH i2c_master_bit_ctrl.v
|
||||
|
||||
add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
|
||||
set_fileset_property sim_verilog TOP_LEVEL i2c_opencores
|
||||
set_fileset_property sim_verilog ENABLE_RELATIVE_INCLUDE_PATHS false
|
||||
add_fileset_file i2c_opencores.v VERILOG PATH i2c_opencores.v
|
||||
add_fileset_file i2c_master_top.v VERILOG PATH i2c_master_top.v
|
||||
add_fileset_file i2c_master_defines.v VERILOG PATH i2c_master_defines.v
|
||||
add_fileset_file i2c_master_byte_ctrl.v VERILOG PATH i2c_master_byte_ctrl.v
|
||||
add_fileset_file i2c_master_bit_ctrl.v VERILOG PATH i2c_master_bit_ctrl.v
|
||||
add_fileset_file timescale.v VERILOG PATH timescale.v
|
||||
|
||||
|
||||
#
|
||||
# parameters
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# display items
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# connection point clock
|
||||
#
|
||||
add_interface clock clock end
|
||||
set_interface_property clock clockRate 0
|
||||
set_interface_property clock ENABLED true
|
||||
|
||||
add_interface_port clock wb_clk_i clk Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point clock_reset
|
||||
#
|
||||
add_interface clock_reset reset end
|
||||
set_interface_property clock_reset associatedClock clock
|
||||
set_interface_property clock_reset synchronousEdges DEASSERT
|
||||
set_interface_property clock_reset ENABLED true
|
||||
|
||||
add_interface_port clock_reset wb_rst_i reset Input 1
|
||||
|
||||
|
||||
#
|
||||
# connection point export
|
||||
#
|
||||
add_interface export conduit end
|
||||
set_interface_property export associatedClock ""
|
||||
set_interface_property export associatedReset ""
|
||||
set_interface_property export ENABLED true
|
||||
|
||||
add_interface_port export scl_pad_io export Bidir 1
|
||||
add_interface_port export sda_pad_io export Bidir 1
|
||||
|
||||
|
||||
#
|
||||
# connection point avalon_slave_0
|
||||
#
|
||||
add_interface avalon_slave_0 avalon end
|
||||
set_interface_property avalon_slave_0 addressAlignment NATIVE
|
||||
set_interface_property avalon_slave_0 addressUnits WORDS
|
||||
set_interface_property avalon_slave_0 associatedClock clock
|
||||
set_interface_property avalon_slave_0 associatedReset clock_reset
|
||||
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
|
||||
set_interface_property avalon_slave_0 explicitAddressSpan 0
|
||||
set_interface_property avalon_slave_0 holdTime 0
|
||||
set_interface_property avalon_slave_0 isMemoryDevice false
|
||||
set_interface_property avalon_slave_0 isNonVolatileStorage false
|
||||
set_interface_property avalon_slave_0 linewrapBursts false
|
||||
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
|
||||
set_interface_property avalon_slave_0 printableDevice false
|
||||
set_interface_property avalon_slave_0 readLatency 0
|
||||
set_interface_property avalon_slave_0 readWaitTime 1
|
||||
set_interface_property avalon_slave_0 setupTime 0
|
||||
set_interface_property avalon_slave_0 timingUnits Cycles
|
||||
set_interface_property avalon_slave_0 writeWaitTime 0
|
||||
set_interface_property avalon_slave_0 ENABLED true
|
||||
|
||||
add_interface_port avalon_slave_0 wb_adr_i address Input 3
|
||||
add_interface_port avalon_slave_0 wb_dat_i writedata Input 8
|
||||
add_interface_port avalon_slave_0 wb_dat_o readdata Output 8
|
||||
add_interface_port avalon_slave_0 wb_we_i write Input 1
|
||||
add_interface_port avalon_slave_0 wb_stb_i chipselect Input 1
|
||||
add_interface_port avalon_slave_0 wb_ack_o waitrequest_n Output 1
|
||||
|
||||
|
||||
#
|
||||
# connection point interrupt_sender
|
||||
#
|
||||
add_interface interrupt_sender interrupt end
|
||||
set_interface_property interrupt_sender associatedAddressablePoint avalon_slave_0
|
||||
set_interface_property interrupt_sender associatedClock clock
|
||||
set_interface_property interrupt_sender associatedReset clock_reset
|
||||
set_interface_property interrupt_sender ENABLED true
|
||||
|
||||
add_interface_port interrupt_sender wb_inta_o irq Output 1
|
||||
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
#
|
||||
# opencores_i2c_sw.tcl
|
||||
#
|
||||
|
||||
# Create a new driver
|
||||
create_driver opencores_i2c_driver
|
||||
|
||||
# Associate it with some hardware known as "opencores_i2c"
|
||||
set_sw_property hw_class_name opencores_i2c
|
||||
|
||||
# The version of this driver
|
||||
set_sw_property version 11.0
|
||||
|
||||
# This driver may be incompatible with versions of hardware less
|
||||
# than specified below. Updates to hardware and device drivers
|
||||
# rendering the driver incompatible with older versions of
|
||||
# hardware are noted with this property assignment.
|
||||
#
|
||||
# Multiple-Version compatibility was introduced in version 7.1;
|
||||
# prior versions are therefore excluded.
|
||||
set_sw_property min_compatible_hw_version 7.1
|
||||
|
||||
# Initialize the driver in alt_sys_init()
|
||||
set_sw_property auto_initialize true
|
||||
|
||||
# Location in generated BSP that above sources will be copied into
|
||||
set_sw_property bsp_subdirectory drivers
|
||||
|
||||
|
||||
# Interrupt properties:
|
||||
# This peripheral has an IRQ output but the driver doesn't currently
|
||||
# have any interrupt service routine. To ensure that the BSP tools
|
||||
# do not otherwise limit the BSP functionality for users of the
|
||||
# Nios II enhanced interrupt port, these settings advertise
|
||||
# compliance with both legacy and enhanced interrupt APIs, and to state
|
||||
# that any driver ISR supports preemption. If an interrupt handler
|
||||
# is added to this driver, these must be re-examined for validity.
|
||||
set_sw_property isr_preemption_supported true
|
||||
set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api"
|
||||
|
||||
#
|
||||
# Source file listings...
|
||||
#
|
||||
|
||||
# C/C++ source files
|
||||
add_sw_property c_source HAL/src/opencores_i2c.c
|
||||
|
||||
# Include files
|
||||
add_sw_property include_source HAL/inc/opencores_i2c.h
|
||||
add_sw_property include_source inc/opencores_i2c_regs.h
|
||||
|
||||
# This driver supports HAL & UCOSII BSP (OS) types
|
||||
add_sw_property supported_bsp_type HAL
|
||||
add_sw_property supported_bsp_type UCOSII
|
||||
|
||||
# End of file
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
|
||||
|
||||
#ifndef __I2C_OPENCORES_REGS_H__
|
||||
#define __I2C_OPENCORES_REGS_H__
|
||||
|
||||
#include <io.h>
|
||||
/* prescal clock/(5*desired_SCL) */
|
||||
/* all registers are 8 bits wide but on 32 bit address boundaries.*/
|
||||
/* reg definitions take from i2c_specs.pdf in the docs folder */
|
||||
|
||||
#define IOADDR_I2C_OPENCORES_PRERLO(base) __IO_CALC_ADDRESS_NATIVE(base, 0)
|
||||
#define IORD_I2C_OPENCORES_PRERLO(base) IORD(base, 0)
|
||||
#define IOWR_I2C_OPENCORES_PRERLO(base, data) IOWR(base, 0, data)
|
||||
|
||||
|
||||
#define IOADDR_I2C_OPENCORES_PRERHI(base) __IO_CALC_ADDRESS_NATIVE(base, 0)
|
||||
#define IORD_I2C_OPENCORES_PRERHI(base) IORD(base, 1)
|
||||
#define IOWR_I2C_OPENCORES_PRERHI(base, data) IOWR(base, 1, data)
|
||||
|
||||
|
||||
#define IOADDR_I2C_OPENCORES_CTR(base) __IO_CALC_ADDRESS_NATIVE(base, 2)
|
||||
#define IORD_I2C_OPENCORES_CTR(base) IORD(base, 2)
|
||||
#define IOWR_I2C_OPENCORES_CTR(base, data) IOWR(base, 2, data)
|
||||
/* bit definitions*/
|
||||
#define I2C_OPENCORES_CTR_EN_MSK (0x80)
|
||||
#define I2C_OPENCORES_CTR_EN_OFST (7)
|
||||
#define I2C_OPENCORES_CTR_IEN_MSK (0x40)
|
||||
#define I2C_OPENCORES_CTR_IEN_OFST (6)
|
||||
|
||||
|
||||
#define IOADDR_I2C_OPENCORES_TXR(base) __IO_CALC_ADDRESS_NATIVE(base, 3)
|
||||
#define IOWR_I2C_OPENCORES_TXR(base, data) IOWR(base, 3, data)
|
||||
/* bit definitions*/
|
||||
#define I2C_OPENCORES_TXR_RD_MSK (0x1)
|
||||
#define I2C_OPENCORES_TXR_RD_OFST (0)
|
||||
#define I2C_OPENCORES_TXR_WR_MSK (0x0)
|
||||
#define I2C_OPENCORES_TXR_WR_OFST (0)
|
||||
|
||||
|
||||
#define IOADDR_I2C_OPENCORES_RXR(base) __IO_CALC_ADDRESS_NATIVE(base, 3)
|
||||
#define IORD_I2C_OPENCORES_RXR(base) IORD(base, 3)
|
||||
|
||||
|
||||
#define IOADDR_I2C_OPENCORES_CR(base) __IO_CALC_ADDRESS_NATIVE(base, 4)
|
||||
#define IOWR_I2C_OPENCORES_CR(base, data) IOWR(base, 4, data)
|
||||
/* bit definitions*/
|
||||
#define I2C_OPENCORES_CR_STA_MSK (0x80)
|
||||
#define I2C_OPENCORES_CR_STA_OFST (7)
|
||||
#define I2C_OPENCORES_CR_STO_MSK (0x40)
|
||||
#define I2C_OPENCORES_CR_STO_OFST (6)
|
||||
#define I2C_OPENCORES_CR_RD_MSK (0x20)
|
||||
#define I2C_OPENCORES_CR_RD_OFST (5)
|
||||
#define I2C_OPENCORES_CR_WR_MSK (0x10)
|
||||
#define I2C_OPENCORES_CR_WR_OFST (4)
|
||||
#define I2C_OPENCORES_CR_NACK_MSK (0x8)
|
||||
#define I2C_OPENCORES_CR_NACK_OFST (3)
|
||||
#define I2C_OPENCORES_CR_IACK_MSK (0x1)
|
||||
#define I2C_OPENCORES_CR_IACK_OFST (0)
|
||||
|
||||
|
||||
#define IOADDR_I2C_OPENCORES_SR(base) __IO_CALC_ADDRESS_NATIVE(base, 4)
|
||||
#define IORD_I2C_OPENCORES_SR(base) IORD(base, 4)
|
||||
/* bit definitions*/
|
||||
#define I2C_OPENCORES_SR_RXNACK_MSK (0x80)
|
||||
#define I2C_OPENCORES_SR_RXNACK_OFST (7)
|
||||
#define I2C_OPENCORES_SR_BUSY_MSK (0x40)
|
||||
#define I2C_OPENCORES_SR_BUSY_OFST (6)
|
||||
#define I2C_OPENCORES_SR_AL_MSK (0x20)
|
||||
#define I2C_OPENCORES_SR_AL_OFST (5)
|
||||
#define I2C_OPENCORES_SR_TIP_MSK (0x2)
|
||||
#define I2C_OPENCORES_SR_TIP_OFST (1)
|
||||
#define I2C_OPENCORES_SR_IF_MSK (0x1)
|
||||
#define I2C_OPENCORES_SR_IF_OFST (0)
|
||||
|
||||
#endif /* __I2C_OPENCORES_REGS_H__ */
|
||||
388
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/test.v
Normal file
388
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/test.v
Normal file
|
|
@ -0,0 +1,388 @@
|
|||
`timescale 1ns / 1ps
|
||||
|
||||
module i2c_drive(
|
||||
clk,rst_n,
|
||||
sw1,sw2,
|
||||
scl,sda,
|
||||
dis_data
|
||||
);
|
||||
|
||||
input clk; // 50MHz
|
||||
input rst_n; //复位信号，低有效
|
||||
input sw1,sw2; //按键1、2,(1按下执行写入操作，2按下执行读操作)
|
||||
output scl; // 24C02的时钟端口
|
||||
inout sda; // 24C02的数据端口
|
||||
output [7:0] dis_data; //输出指定单元的数据
|
||||
|
||||
//--------------------------------------------
|
||||
//按键检测
|
||||
reg sw1_r,sw2_r; //键值锁存寄存器，每20ms检测一次键值
|
||||
reg[19:0] cnt_20ms; //20ms计数寄存器
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(!rst_n)
|
||||
cnt_20ms <= 20'd0;
|
||||
else
|
||||
cnt_20ms <= cnt_20ms+1'b1; //不断计数
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(!rst_n)
|
||||
begin
|
||||
sw1_r <= 1'b1; //键值寄存器复位，没有键盘按下时键值都为1
|
||||
sw2_r <= 1'b1;
|
||||
end
|
||||
else if(cnt_20ms == 20'hfffff)
|
||||
begin
|
||||
sw1_r <= sw1; //按键1值锁存
|
||||
sw2_r <= sw2; //按键2值锁存
|
||||
end
|
||||
|
||||
//---------------------------------------------
|
||||
//分频部分
|
||||
reg[2:0] cnt; // cnt=0:scl上升沿，cnt=1:scl高电平中间，cnt=2:scl下降沿，cnt=3:scl低电平中间
|
||||
reg[8:0] cnt_delay; //500循环计数，产生iic所需要的时钟
|
||||
reg scl_r; //时钟脉冲寄存器
|
||||
reg scl_en;
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(!rst_n)
|
||||
cnt_delay <= 9'd0;
|
||||
else if(cnt_delay == 9'd499)
|
||||
cnt_delay <= 9'd0; //计数到10us为scl的周期，即100KHz
|
||||
else
|
||||
cnt_delay <= cnt_delay+1'b1; //时钟计数
|
||||
|
||||
always @ (posedge clk or negedge rst_n) begin
|
||||
if(!rst_n)
|
||||
cnt <= 3'd5;
|
||||
else
|
||||
begin
|
||||
case (cnt_delay)
|
||||
9'd124: cnt <= 3'd1; //cnt=1:scl高电平中间,用于数据采样
|
||||
9'd249: cnt <= 3'd2; //cnt=2:scl下降沿
|
||||
9'd374: cnt <= 3'd3; //cnt=3:scl低电平中间,用于数据变化
|
||||
9'd499: cnt <= 3'd0; //cnt=0:scl上升沿
|
||||
default: cnt <= 3'd5;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
`define SCL_POS (cnt==3'd0) //cnt=0:scl上升沿
|
||||
`define SCL_HIG (cnt==3'd1) //cnt=1:scl高电平中间,用于数据采样
|
||||
`define SCL_NEG (cnt==3'd2) //cnt=2:scl下降沿
|
||||
`define SCL_LOW (cnt==3'd3) //cnt=3:scl低电平中间,用于数据变化
|
||||
|
||||
|
||||
always @ (posedge clk or negedge rst_n)
|
||||
if(!rst_n)
|
||||
scl_r <= 1'b0;
|
||||
else if(cnt==3'd0)
|
||||
scl_r <= 1'b1; //scl信号上升沿
|
||||
else if(cnt==3'd2)
|
||||
scl_r <= 1'b0; //scl信号下降沿
|
||||
|
||||
assign scl = scl_en?scl_r:1'bz; //产生iic所需要的时钟
|
||||
//---------------------------------------------
|
||||
|
||||
//需要写入24C02的地址和数据
|
||||
`define DEVICE_READ 8'b0111_0001 //被寻址器件地址（读操作）
|
||||
`define DEVICE_WRITE 8'b0111_0000 //被寻址器件地址（写操作）
|
||||
|
||||
//`define WRITE_DATA 8'b0000_0111 //写入EEPROM的数据
|
||||
`define BYTE_ADDR 8'b0000_0010 //写入/读出EEPROM的地址寄存器
|
||||
|
||||
reg[7:0] db_r; //在IIC上传送的数据寄存器
|
||||
reg[7:0] read_data; //读出EEPROM的数据寄存器
|
||||
|
||||
//---------------------------------------------
|
||||
//读、写时序
|
||||
parameter IDLE = 4'd0;
|
||||
parameter START1 = 4'd1;
|
||||
parameter ADD1 = 4'd2;
|
||||
parameter ACK1 = 4'd3;
|
||||
parameter ADD2 = 4'd4;
|
||||
parameter ACK2 = 4'd5;
|
||||
parameter START2 = 4'd6;
|
||||
parameter ADD3 = 4'd7;
|
||||
parameter ACK3 = 4'd8;
|
||||
parameter DATA = 4'd9;
|
||||
parameter ACK4 = 4'd10;
|
||||
parameter STOP1 = 4'd11;
|
||||
parameter STOP2 = 4'd12;
|
||||
|
||||
|
||||
reg[3:0] cstate; //状态寄存器
|
||||
reg sda_r; //输出数据寄存器
|
||||
reg sda_link; //输出数据sda信号inout方向控制位
|
||||
reg[3:0] num; //
|
||||
|
||||
|
||||
always @ (posedge clk or negedge rst_n) begin
|
||||
if(!rst_n)
|
||||
begin
|
||||
cstate <= IDLE;
|
||||
sda_r <= 1'b1;
|
||||
sda_link <= 1'b0;
|
||||
num <= 4'd0;
|
||||
read_data <= 8'b0000_0000;
|
||||
scl_en<=0;
|
||||
end
|
||||
else
|
||||
case (cstate)
|
||||
IDLE:
|
||||
begin
|
||||
sda_link <= 1'b1; //数据线sda为input
|
||||
sda_r <= 1'b1;
|
||||
scl_en<=0;
|
||||
if(!sw1_r || !sw2_r)
|
||||
begin //SW1,SW2键有一个被按下
|
||||
db_r <= `DEVICE_WRITE; //送器件地址（写操作）
|
||||
cstate <= START1;
|
||||
scl_en<=1;
|
||||
end
|
||||
else
|
||||
cstate <= IDLE; //没有任何键被按下
|
||||
end
|
||||
START1:
|
||||
begin
|
||||
if(`SCL_HIG)
|
||||
begin //scl为高电平期间
|
||||
sda_link <= 1'b1; //数据线sda为output
|
||||
sda_r <= 1'b0; //拉低数据线sda，产生起始位信号
|
||||
cstate <= ADD1;
|
||||
num <= 4'd0; //num计数清零
|
||||
end
|
||||
else
|
||||
cstate <= START1; //等待scl高电平中间位置到来
|
||||
end
|
||||
ADD1:
|
||||
begin
|
||||
if(`SCL_LOW)
|
||||
begin
|
||||
if(num == 4'd8)
|
||||
begin
|
||||
num <= 4'd0; //num计数清零
|
||||
sda_r <= 1'b1;
|
||||
sda_link <= 1'b0; //sda置为高阻态(input)
|
||||
cstate <= ACK1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cstate <= ADD1;
|
||||
num <= num+1'b1;
|
||||
case (num)
|
||||
4'd0: sda_r <= db_r[7];
|
||||
4'd1: sda_r <= db_r[6];
|
||||
4'd2: sda_r <= db_r[5];
|
||||
4'd3: sda_r <= db_r[4];
|
||||
4'd4: sda_r <= db_r[3];
|
||||
4'd5: sda_r <= db_r[2];
|
||||
4'd6: sda_r <= db_r[1];
|
||||
4'd7: sda_r <= db_r[0];
|
||||
default: ;
|
||||
endcase
|
||||
// sda_r <= db_r[4'd7-num]; //送器件地址，从高位开始
|
||||
end
|
||||
end
|
||||
// else if(`SCL_POS) db_r <= {db_r[6:0],1'b0}; //器件地址左移1bit
|
||||
else
|
||||
cstate <= ADD1;
|
||||
end
|
||||
ACK1:
|
||||
begin
|
||||
if(/*!sda*/`SCL_NEG)
|
||||
begin //注：24C01/02/04/08/16器件可以不考虑应答位
|
||||
cstate <= ADD2; //从机响应信号
|
||||
db_r <= `BYTE_ADDR; // 1地址
|
||||
end
|
||||
else
|
||||
cstate <= ACK1; //等待从机响应
|
||||
end
|
||||
ADD2:
|
||||
begin
|
||||
if(`SCL_LOW)
|
||||
begin
|
||||
if(num==4'd8)
|
||||
begin
|
||||
num <= 4'd0; //num计数清零
|
||||
sda_r <= 1'b1;
|
||||
sda_link <= 1'b0; //sda置为高阻态(input)
|
||||
cstate <= ACK2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
sda_link <= 1'b1; //sda作为output
|
||||
num <= num+1'b1;
|
||||
case (num)
|
||||
4'd0: sda_r <= db_r[7];
|
||||
4'd1: sda_r <= db_r[6];
|
||||
4'd2: sda_r <= db_r[5];
|
||||
4'd3: sda_r <= db_r[4];
|
||||
4'd4: sda_r <= db_r[3];
|
||||
4'd5: sda_r <= db_r[2];
|
||||
4'd6: sda_r <= db_r[1];
|
||||
4'd7: sda_r <= db_r[0];
|
||||
default: ;
|
||||
endcase
|
||||
// sda_r <= db_r[4'd7-num]; //送EEPROM地址（高bit开始）
|
||||
cstate <= ADD2;
|
||||
end
|
||||
end
|
||||
// else if(`SCL_POS) db_r <= {db_r[6:0],1'b0}; //器件地址左移1bit
|
||||
else
|
||||
cstate <= ADD2;
|
||||
end
|
||||
ACK2: begin
|
||||
if(/*!sda*/`SCL_NEG) begin //从机响应信号
|
||||
if(!sw1_r) begin
|
||||
cstate <= DATA; //写操作
|
||||
db_r <= `WRITE_DATA; //写入的数据
|
||||
end
|
||||
else if(!sw2_r) begin
|
||||
db_r <= `DEVICE_READ; //送器件地址（读操作），特定地址读需要执行该步骤以下操作
|
||||
cstate <= START2; //读操作
|
||||
end
|
||||
end
|
||||
else cstate <= ACK2; //等待从机响应
|
||||
end
|
||||
START2: begin //读操作起始位
|
||||
if(`SCL_LOW) begin
|
||||
sda_link <= 1'b1; //sda作为output
|
||||
sda_r <= 1'b1; //拉高数据线sda
|
||||
cstate <= START2;
|
||||
end
|
||||
else if(`SCL_HIG) begin //scl为高电平中间
|
||||
sda_r <= 1'b0; //拉低数据线sda，产生起始位信号
|
||||
cstate <= ADD3;
|
||||
end
|
||||
else cstate <= START2;
|
||||
end
|
||||
ADD3: begin //送读操作地址
|
||||
if(`SCL_LOW) begin
|
||||
if(num==4'd8) begin
|
||||
num <= 4'd0; //num计数清零
|
||||
sda_r <= 1'b1;
|
||||
sda_link <= 1'b0; //sda置为高阻态(input)
|
||||
cstate <= ACK3;
|
||||
end
|
||||
else begin
|
||||
num <= num+1'b1;
|
||||
case (num)
|
||||
4'd0: sda_r <= db_r[7];
|
||||
4'd1: sda_r <= db_r[6];
|
||||
4'd2: sda_r <= db_r[5];
|
||||
4'd3: sda_r <= db_r[4];
|
||||
4'd4: sda_r <= db_r[3];
|
||||
4'd5: sda_r <= db_r[2];
|
||||
4'd6: sda_r <= db_r[1];
|
||||
4'd7: sda_r <= db_r[0];
|
||||
default: ;
|
||||
endcase
|
||||
// sda_r <= db_r[4'd7-num]; //送EEPROM地址（高bit开始）
|
||||
cstate <= ADD3;
|
||||
end
|
||||
end
|
||||
// else if(`SCL_POS) db_r <= {db_r[6:0],1'b0}; //器件地址左移1bit
|
||||
else cstate <= ADD3;
|
||||
end
|
||||
ACK3: begin
|
||||
if(/*!sda*/`SCL_NEG) begin
|
||||
cstate <= DATA; //从机响应信号
|
||||
sda_link <= 1'b0;
|
||||
end
|
||||
else cstate <= ACK3; //等待从机响应
|
||||
end
|
||||
DATA: begin
|
||||
if(!sw2_r) begin //读操作
|
||||
if(num<=4'd7) begin
|
||||
cstate <= DATA;
|
||||
if(`SCL_HIG) begin
|
||||
num <= num+1'b1;
|
||||
case (num)
|
||||
4'd0: read_data[7] <= sda;
|
||||
4'd1: read_data[6] <= sda;
|
||||
4'd2: read_data[5] <= sda;
|
||||
4'd3: read_data[4] <= sda;
|
||||
4'd4: read_data[3] <= sda;
|
||||
4'd5: read_data[2] <= sda;
|
||||
4'd6: read_data[1] <= sda;
|
||||
4'd7: read_data[0] <= sda;
|
||||
default: ;
|
||||
endcase
|
||||
// read_data[4'd7-num] <= sda; //读数据（高bit开始）
|
||||
end
|
||||
// else if(`SCL_NEG) read_data <= {read_data[6:0],read_data[7]}; //数据循环右移
|
||||
end
|
||||
else if((`SCL_LOW) && (num==4'd8)) begin
|
||||
num <= 4'd0; //num计数清零
|
||||
cstate <= ACK4;
|
||||
end
|
||||
else cstate <= DATA;
|
||||
end
|
||||
else if(!sw1_r) begin //写操作
|
||||
sda_link <= 1'b1;
|
||||
if(num<=4'd7) begin
|
||||
cstate <= DATA;
|
||||
if(`SCL_LOW) begin
|
||||
sda_link <= 1'b1; //数据线sda作为output
|
||||
num <= num+1'b1;
|
||||
case (num)
|
||||
4'd0: sda_r <= db_r[7];
|
||||
4'd1: sda_r <= db_r[6];
|
||||
4'd2: sda_r <= db_r[5];
|
||||
4'd3: sda_r <= db_r[4];
|
||||
4'd4: sda_r <= db_r[3];
|
||||
4'd5: sda_r <= db_r[2];
|
||||
4'd6: sda_r <= db_r[1];
|
||||
4'd7: sda_r <= db_r[0];
|
||||
default: ;
|
||||
endcase
|
||||
// sda_r <= db_r[4'd7-num]; //写入数据（高bit开始）
|
||||
end
|
||||
// else if(`SCL_POS) db_r <= {db_r[6:0],1'b0}; //写入数据左移1bit
|
||||
end
|
||||
else if((`SCL_LOW) && (num==4'd8)) begin
|
||||
num <= 4'd0;
|
||||
sda_r <= 1'b1;
|
||||
sda_link <= 1'b0; //sda置为高阻态
|
||||
cstate <= ACK4;
|
||||
end
|
||||
else cstate <= DATA;
|
||||
end
|
||||
end
|
||||
ACK4: begin
|
||||
if(/*!sda*/`SCL_NEG) begin
|
||||
// sda_r <= 1'b1;
|
||||
cstate <= STOP1;
|
||||
end
|
||||
else cstate <= ACK4;
|
||||
end
|
||||
STOP1: begin
|
||||
if(`SCL_LOW) begin
|
||||
sda_link <= 1'b1;
|
||||
sda_r <= 1'b0;
|
||||
cstate <= STOP1;
|
||||
end
|
||||
else if(`SCL_HIG) begin
|
||||
sda_r <= 1'b1; //scl为高时，sda产生上升沿（结束信号）
|
||||
cstate <= STOP2;
|
||||
end
|
||||
else cstate <= STOP1;
|
||||
end
|
||||
STOP2: begin
|
||||
if(`SCL_LOW) sda_r <= 1'b1;
|
||||
else if(cnt_20ms==20'hffff0) cstate <= IDLE;
|
||||
else cstate <= STOP2;
|
||||
end
|
||||
default: cstate <= IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign sda = sda_link ? sda_r:1'bz;
|
||||
assign dis_data = read_data;
|
||||
|
||||
//---------------------------------------------
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
2
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/timescale.v
Normal file
2
Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/timescale.v
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
`timescale 1ns / 10ps
|
||||
|
||||
BIN
Vision/DE10_LITE_D8M_VIP_16/readme.pdf
Normal file
BIN
Vision/DE10_LITE_D8M_VIP_16/readme.pdf
Normal file
Binary file not shown.
|
|
@ -0,0 +1,83 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050">
|
||||
<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" moduleId="org.eclipse.cdt.core.settings"/>
|
||||
</buildSystem>
|
||||
<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050">
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
|
||||
<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050." name="/" resourcePath="">
|
||||
<toolChain id="altera.nios2.mingw.gcc4.360127606" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
|
||||
<targetPlatform id="altera.nios2.mingw.gcc4.1269419812" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
|
||||
<builder buildPath="${workspace_loc://D8M_Camera_Test}" id="altera.tool.gnu.builder.mingw.49071199" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
|
||||
<tool id="altera.tool.gnu.c.compiler.mingw.1481046436" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.586658978" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="altera.tool.gnu.cpp.compiler.mingw.1510030252" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.373987131" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="altera.tool.gnu.archiver.mingw.1404974041" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
|
||||
<tool id="altera.tool.gnu.c.linker.mingw.134928044" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
|
||||
<tool id="altera.tool.gnu.assembler.mingw.775279607" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.258488279" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="D8M_Camera_Test.null.1062948969" name="D8M_Camera_Test"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050.;altera.tool.gnu.cpp.compiler.mingw.1510030252;cdt.managedbuild.tool.gnu.cpp.compiler.input.373987131">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050.;altera.tool.gnu.c.compiler.mingw.1481046436;cdt.managedbuild.tool.gnu.c.compiler.input.586658978">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
|
||||
<buildTargets>
|
||||
<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
|
||||
<buildCommand>make</buildCommand>
|
||||
<buildArguments/>
|
||||
<buildTarget>mem_init_install</buildTarget>
|
||||
<stopOnError>true</stopOnError>
|
||||
<useDefaultCommand>false</useDefaultCommand>
|
||||
<runAllBuilders>false</runAllBuilders>
|
||||
</target>
|
||||
<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
|
||||
<buildCommand>make</buildCommand>
|
||||
<buildArguments/>
|
||||
<buildTarget>mem_init_generate</buildTarget>
|
||||
<stopOnError>true</stopOnError>
|
||||
<useDefaultCommand>false</useDefaultCommand>
|
||||
<runAllBuilders>false</runAllBuilders>
|
||||
</target>
|
||||
<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
|
||||
<buildCommand>make</buildCommand>
|
||||
<buildArguments/>
|
||||
<buildTarget>help</buildTarget>
|
||||
<stopOnError>true</stopOnError>
|
||||
<useDefaultCommand>false</useDefaultCommand>
|
||||
<runAllBuilders>false</runAllBuilders>
|
||||
</target>
|
||||
</buildTargets>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>D8M_Camera_Test</name>
|
||||
<comment></comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>com.altera.sbtgui.project.makefileBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>com.altera.sbtgui.project.makefileBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
|
||||
<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
|
||||
<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.743549050" name="Nios II">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-1853935238722855090" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
||||
Binary file not shown.
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Load diff
732
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/I2C_core.c
Normal file
732
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/I2C_core.c
Normal file
|
|
@ -0,0 +1,732 @@
|
|||
// --------------------------------------------------------------------
|
||||
// Copyright (c) 2007 by Terasic Technologies Inc.
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Permission:
|
||||
//
|
||||
// Terasic grants permission to use and modify this code for use
|
||||
// in synthesis for all Terasic Development Boards and Altera Development
|
||||
// Kits made by Terasic. Other use of this code, including the selling
|
||||
// ,duplication, or modification of any portion is strictly prohibited.
|
||||
//
|
||||
// Disclaimer:
|
||||
//
|
||||
// This VHDL/Verilog or C/C++ source code is intended as a design reference
|
||||
// which illustrates how these types of functions can be implemented.
|
||||
// It is the user's responsibility to verify their design for
|
||||
// consistency and functionality through the use of formal
|
||||
// verification methods. Terasic provides no warranty regarding the use
|
||||
// or functionality of this code.
|
||||
//
|
||||
// --------------------------------------------------------------------
|
||||
//
|
||||
// Terasic Technologies Inc
|
||||
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
|
||||
// HsinChu County, Taiwan
|
||||
// 302
|
||||
//
|
||||
// web: http://www.terasic.com/
|
||||
// email: support@terasic.com
|
||||
//
|
||||
// --------------------------------------------------------------------
|
||||
#include "terasic_includes.h"
|
||||
#include "I2C_core.h"
|
||||
#include "io.h"
|
||||
// Note. Remember to reset device befroe acceess I2C interface
|
||||
#ifdef DEBUG_I2C
|
||||
#define I2C_DEBUG(x) DEBUG(x)
|
||||
#else
|
||||
#define I2C_DEBUG(x)
|
||||
#endif
|
||||
|
||||
#define SLEEP_TIME 250 //us
|
||||
#define ACK_SLEEP_TIME 250 //us
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
|
||||
bool Write32_Data(alt_32 base_address, alt_32 offset_address, alt_32 Data){
|
||||
bool bPass;
|
||||
IOWR(base_address, offset_address,Data);
|
||||
bPass=TRUE;
|
||||
return bPass;
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool Read32_Data(alt_32 base_address, alt_32 offset_address, alt_32 *pData32){
|
||||
bool bPass;
|
||||
*pData32 =IORD(base_address ,offset_address );
|
||||
bPass=TRUE;
|
||||
return bPass;
|
||||
}
|
||||
|
||||
bool oc_i2c_init(alt_32 i2c_base){
|
||||
bool bSuccess;
|
||||
const alt_32 ref_clk = 50*1000*1000; // 50MHz
|
||||
const alt_32 i2c_clk = 400*1000; // 400KHz
|
||||
|
||||
bSuccess = oc_i2c_init_ex(i2c_base, ref_clk, i2c_clk);
|
||||
|
||||
return bSuccess;
|
||||
}
|
||||
|
||||
bool oc_i2c_init_ex(alt_32 i2c_base, alt_32 ref_clk, alt_32 i2c_clk)
|
||||
{
|
||||
bool bSuccess=TRUE;
|
||||
alt_32 read_data;
|
||||
alt_32 prescale;
|
||||
alt_u8 prescale_high;
|
||||
alt_u8 prescale_low;
|
||||
const alt_u8 ControlValue = 0x80;
|
||||
|
||||
// I2c sysclock =50M hz
|
||||
// i2c scl max 400k
|
||||
//scl =sysclock/(prescale*5)
|
||||
prescale = (ref_clk/(5*i2c_clk))-1;
|
||||
prescale_low = prescale & 0xFF;
|
||||
prescale_high = (prescale >> 8) & 0xFF;
|
||||
|
||||
IOWR(i2c_base, 0, prescale_low);//write low byte of prescale (reg 0)
|
||||
IOWR(i2c_base, 1, prescale_high);//write high byte of prescale (reg 1)
|
||||
|
||||
//enable the I2C core, but disable the IRQ
|
||||
IOWR( i2c_base, 2, ControlValue);
|
||||
|
||||
|
||||
// check prescale low byte
|
||||
if (bSuccess){
|
||||
read_data =IORD(i2c_base, 0);
|
||||
if( (read_data & 0x00ff) != prescale_low ){
|
||||
bSuccess = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
// check prescale high byte
|
||||
if (bSuccess){
|
||||
read_data =IORD(i2c_base, 1);
|
||||
if( (read_data & 0x00ff) != prescale_high ){
|
||||
bSuccess = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
// check control
|
||||
if (bSuccess){
|
||||
read_data =IORD(i2c_base, 2);
|
||||
if( (read_data & 0x00ff) != ControlValue ){
|
||||
bSuccess = FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
if (bSuccess){
|
||||
// printf("\nI2C core is enabled! \r\n");
|
||||
}
|
||||
else
|
||||
printf("\nI2C core is not enabled successfully! \r\n");
|
||||
|
||||
return bSuccess;
|
||||
|
||||
}
|
||||
|
||||
bool oc_i2c_uninit(alt_32 i2c_base)
|
||||
{
|
||||
bool bSuccess=TRUE;
|
||||
alt_32 read_data;
|
||||
const alt_u8 ControlValue = 0x00;
|
||||
|
||||
IOWR( i2c_base, 2, ControlValue);
|
||||
read_data =IORD(i2c_base, 2);
|
||||
if( (read_data & 0x00ff) != ControlValue ){
|
||||
bSuccess = FALSE;
|
||||
}
|
||||
|
||||
if (bSuccess){
|
||||
// printf("\I2C core is disabled! \r\n");
|
||||
}
|
||||
else
|
||||
printf("\I2C core is failed to disable! \r\n");
|
||||
|
||||
return bSuccess;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
bool ACK_single_check(alt_32 i2c_base)
|
||||
{
|
||||
bool bSuccess=TRUE;
|
||||
alt_32 read_data;
|
||||
|
||||
usleep(ACK_SLEEP_TIME);
|
||||
read_data =IORD(i2c_base, 4);
|
||||
if(read_data & 0x02)
|
||||
bSuccess = FALSE;
|
||||
if (bSuccess){
|
||||
usleep(ACK_SLEEP_TIME);
|
||||
read_data =IORD(i2c_base, 4);
|
||||
if(read_data & 0x80)
|
||||
bSuccess = FALSE;
|
||||
}
|
||||
return bSuccess;
|
||||
}
|
||||
|
||||
|
||||
bool ACK_check(alt_32 i2c_base){
|
||||
bool bSuccess = FALSE;
|
||||
int i=0;
|
||||
|
||||
while(!bSuccess && i++ < 10){
|
||||
bSuccess = ACK_single_check(i2c_base);
|
||||
}
|
||||
|
||||
return bSuccess;
|
||||
}
|
||||
|
||||
bool OC_I2C_Write(alt_32 i2c_base,alt_u8 device_address,alt_u8 sub_address, alt_u8 *pData, int nWriteLength)
|
||||
{
|
||||
//DWORD reg_data = 0x0;
|
||||
int i;
|
||||
|
||||
//set the tx reg audio chip dev address with write bit
|
||||
if (!Write32_Data( i2c_base, 3,device_address)){
|
||||
printf("OC_I2C_Write error[0]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x90)){
|
||||
printf("OC_I2C_Write error[1]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2C_Write error[2]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n receive ACK-device address! \n");
|
||||
|
||||
//set the txr reg data with reg address + 1 data MSB
|
||||
if (!Write32_Data( i2c_base, 3,sub_address)){
|
||||
printf("OC_I2C_Write error[3]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
//set WR bits(bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10)){
|
||||
printf("OC_I2C_Write error[4]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2C_Write error[5]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n receive ACK-reg address! \n");
|
||||
|
||||
#if 1
|
||||
for( i=nWriteLength-1;i>=0;i--){
|
||||
//set the txr reg data with the data
|
||||
if (!Write32_Data( i2c_base, 3,*(pData+i))){
|
||||
printf("OC_I2C_Write error[6]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
//set STO and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10)){
|
||||
printf("OC_I2C_Write error[7]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2C_Write error[8]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
//set the txr reg data with the data
|
||||
if (!Write32_Data( i2c_base, 3,data&0xff))
|
||||
return false;
|
||||
|
||||
//set STO and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return false;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base))
|
||||
return false;
|
||||
#endif
|
||||
|
||||
if (!Write32_Data( i2c_base, 4,0x40)){
|
||||
printf("OC_I2C_Write error[9]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
//Sleep(10);
|
||||
//OS_msleep(1);
|
||||
usleep(SLEEP_TIME);
|
||||
|
||||
// printf("\n receive ACK-data! \n");
|
||||
|
||||
return TRUE;
|
||||
|
||||
}
|
||||
|
||||
|
||||
bool ACK_judge_for_read(alt_32 i2c_base)
|
||||
{
|
||||
bool bSuccess;
|
||||
alt_32 this_data;
|
||||
|
||||
// OS_msleep( SLEEP_TIME );
|
||||
usleep(ACK_SLEEP_TIME);
|
||||
// while(this_data & 0x02)
|
||||
// {
|
||||
// this_data = Read32_Data ( hPCIe, i2c_base, 4);
|
||||
// }
|
||||
bSuccess = Read32_Data ( i2c_base, 4, &this_data);
|
||||
if (bSuccess){
|
||||
if(this_data & 0x02)
|
||||
bSuccess = FALSE;
|
||||
}
|
||||
//wait the rx ACK signal 0-valid
|
||||
|
||||
return bSuccess;
|
||||
|
||||
}
|
||||
|
||||
bool OC_I2C_Read(alt_32 i2c_base,alt_u8 device_address,alt_u8 sub_address, alt_u8 *pData8, int nReadLength){
|
||||
|
||||
//DWORD reg_data = 0x0;
|
||||
//BYTE data = 0x0;
|
||||
alt_32 Data32;
|
||||
int i;
|
||||
|
||||
//set the tx reg audio chip dev address with write bit
|
||||
IOWR( i2c_base, 3,device_address);
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
IOWR( i2c_base, 4,0x90);
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if (!ACK_check( i2c_base)){
|
||||
printf("OC_I2C_Read error[2]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
IOWR(i2c_base, 3,sub_address);
|
||||
|
||||
//set WR bits(bit4)
|
||||
IOWR( i2c_base, 4,0x10);
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if (!ACK_check( i2c_base)){
|
||||
printf("OC_I2C_Read error[5]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n read receive ACK-reg address! \n");
|
||||
|
||||
//read
|
||||
//set the tx reg audio chip dev address with read bit 1
|
||||
|
||||
IOWR(i2c_base, 3,device_address|0x01);
|
||||
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
IOWR( i2c_base, 4,0x90);
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if (!ACK_check( i2c_base)){
|
||||
printf("OC_I2C_Read error[8]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
for(i=0;i<nReadLength;i++){
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
//set the RD and ACK bit(bit5 and bit3)
|
||||
IOWR( i2c_base, 4,((i+1) == nReadLength)?0x28:0x20);
|
||||
|
||||
if (!ACK_judge_for_read( i2c_base)){
|
||||
printf("OC_I2C_Read error[10]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
|
||||
Data32=IORD( i2c_base, 3);
|
||||
*(pData8+i) = Data32 & 0xff;
|
||||
}
|
||||
|
||||
IOWR( i2c_base, 4,0x40);
|
||||
|
||||
// Sleep(10);
|
||||
//OS_msleep(1);
|
||||
usleep(SLEEP_TIME);
|
||||
// printf(" Read [%02X] = %02Xh\r\n", sub_address, data);
|
||||
|
||||
|
||||
return TRUE;
|
||||
|
||||
}
|
||||
|
||||
|
||||
bool OC_I2C_Read_Continue(alt_32 i2c_base,alt_u8 device_address, alt_u8 *pData8, int nReadLength){
|
||||
int i;
|
||||
alt_u32 Data32;
|
||||
|
||||
IOWR(i2c_base, 3,device_address|0x01);
|
||||
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
IOWR( i2c_base, 4,0x90);
|
||||
//usleep(5*1000);
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if (!ACK_check( i2c_base)){
|
||||
printf("OC_I2C_Read error[8]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
for(i=0;i<nReadLength;i++){
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
//set the RD and ACK bit(bit5 and bit3)
|
||||
IOWR( i2c_base, 4,((i+1) == nReadLength)?0x28:0x20);
|
||||
|
||||
if (!ACK_judge_for_read( i2c_base)){
|
||||
printf("OC_I2C_Read error[10]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
|
||||
Data32=IORD( i2c_base, 3);
|
||||
*(pData8+i) = Data32 & 0xff;
|
||||
}
|
||||
|
||||
IOWR( i2c_base, 4,0x40);
|
||||
|
||||
// Sleep(10);
|
||||
//OS_msleep(1);
|
||||
usleep(SLEEP_TIME);
|
||||
// printf(" Read [%02X] = %02Xh\r\n", sub_address, data);
|
||||
|
||||
|
||||
return TRUE;
|
||||
|
||||
}
|
||||
|
||||
|
||||
// size > 2Kb
|
||||
bool OC_I2CL_Write(alt_32 i2c_base,alt_u8 device_address,alt_u16 sub_address,alt_u8 *pData, int nWriteLength)
|
||||
{
|
||||
//DWORD reg_data = 0x0;
|
||||
alt_u8 AddrHigh, AddrLow;
|
||||
//int count= 0;
|
||||
|
||||
AddrHigh = (sub_address >> 8) & 0xFF;
|
||||
AddrLow = sub_address & 0xFF;
|
||||
|
||||
int i;
|
||||
|
||||
//set the tx reg audio chip dev address with write bit
|
||||
if (!Write32_Data( i2c_base, 3,device_address))
|
||||
return FALSE;
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x90))//0x90
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Write error[0]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n receive ACK-device address! \n");
|
||||
|
||||
//set the txr reg data with reg address + 1 data MSB
|
||||
// reg_data = (sub_address << 1) & 0xFE;
|
||||
//reg_data |= ((data >> 8) & 0x01);
|
||||
if (!Write32_Data( i2c_base, 3,AddrHigh))//reg_data&0xff);
|
||||
return FALSE;
|
||||
|
||||
//set WR bits(bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Write error[1]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n receive ACK-reg high address! \n");
|
||||
|
||||
//set the txr reg data with reg address + 1 data MSB
|
||||
if (!Write32_Data( i2c_base, 3,AddrLow))//reg_data&0xff);
|
||||
return FALSE;
|
||||
|
||||
//set WR bits(bit4)
|
||||
Write32_Data( i2c_base, 4,0x10);
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Write error[2]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n receive ACK-reg low address! \n");
|
||||
|
||||
#if 1
|
||||
for( i=nWriteLength-1;i>=0;i--){
|
||||
//set the txr reg data with the other data 8 bit LSB
|
||||
if (!Write32_Data( i2c_base, 3,*(pData+i)))
|
||||
return FALSE;
|
||||
|
||||
//set STO and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Write error[3]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
#else
|
||||
//set the txr reg data with the other data 8 bit LSB
|
||||
if (!Write32_Data( i2c_base, 3,data&0xff))
|
||||
return false;
|
||||
|
||||
//set STO and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base))
|
||||
return FALSE;
|
||||
|
||||
#endif
|
||||
if (!Write32_Data( i2c_base, 4,0x40))
|
||||
return FALSE;
|
||||
|
||||
//OS_msleep(1);
|
||||
usleep(SLEEP_TIME);
|
||||
// printf("\n receive ACK-data! \n");
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
bool OC_I2CL_Read(alt_32 i2c_base,alt_u8 device_address,int sub_address, alt_u8 *pData8){
|
||||
|
||||
//DWORD reg_data = 0x0;
|
||||
alt_32 Data32;// = 0x0;
|
||||
|
||||
alt_u8 AddrHigh, AddrLow;
|
||||
|
||||
AddrHigh = (sub_address >> 8) & 0xFF;
|
||||
AddrLow = sub_address & 0xFF;
|
||||
|
||||
|
||||
//set the tx reg audio chip dev address with write bit
|
||||
if (!Write32_Data( i2c_base, 3,device_address))
|
||||
return FALSE;
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x90))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base))
|
||||
return FALSE;
|
||||
// printf("\n receive ACK-device address! \n");
|
||||
|
||||
|
||||
//set the txr reg data with reg address + 0
|
||||
|
||||
if (!Write32_Data( i2c_base, 3,AddrHigh))//reg_data&0xff);
|
||||
return FALSE;
|
||||
|
||||
//set WR bits(bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base))
|
||||
return FALSE;
|
||||
// printf("\n read receive ACK-reg High address! \n");
|
||||
|
||||
//set the txr reg data with reg address + 0
|
||||
if (!Write32_Data( i2c_base, 3,AddrLow)) //;//reg_data&0xff);
|
||||
return FALSE;
|
||||
|
||||
//set WR bits(bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base))
|
||||
return FALSE;
|
||||
|
||||
// printf("\n read receive ACK-reg Low address! \n");
|
||||
|
||||
//read
|
||||
//set the tx reg audio chip dev address with read bit 1
|
||||
if (!Write32_Data( i2c_base, 3,device_address|0x01))
|
||||
return FALSE;
|
||||
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x90))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base))
|
||||
return FALSE;
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
|
||||
//read the rxr data
|
||||
|
||||
|
||||
//set the RD and ACK bit(bit5 and bit3)
|
||||
if (!Write32_Data( i2c_base, 4,0x28))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_judge_for_read( i2c_base))
|
||||
return FALSE;
|
||||
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
if (!Read32_Data ( i2c_base, 3, &Data32))
|
||||
return FALSE;
|
||||
|
||||
*pData8 = Data32 & 0xff;
|
||||
|
||||
|
||||
if (!Write32_Data( i2c_base, 4,0x40))
|
||||
return FALSE;
|
||||
|
||||
//OS_msleep(1);
|
||||
usleep(SLEEP_TIME);
|
||||
|
||||
return TRUE;
|
||||
|
||||
} */
|
||||
|
||||
bool OC_I2CL_Read(alt_32 i2c_base,alt_u8 device_address, alt_u16 sub_address, alt_u8 *pData8, int nReadLength){
|
||||
|
||||
//DWORD reg_data = 0x0;
|
||||
alt_32 Data32;// = 0x0;
|
||||
int i;
|
||||
|
||||
alt_u8 AddrHigh, AddrLow;
|
||||
alt_u8 DataHigh, DataLow;
|
||||
|
||||
AddrHigh = (sub_address >> 8) & 0xFF;
|
||||
AddrLow = sub_address & 0xFF;
|
||||
|
||||
|
||||
//set the tx reg audio chip dev address with write bit
|
||||
if (!Write32_Data( i2c_base, 3,device_address))
|
||||
return FALSE;
|
||||
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x90))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Read error[0]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n receive ACK-device address! \n");
|
||||
|
||||
|
||||
//set the txr reg data with reg address + 0
|
||||
|
||||
if (!Write32_Data( i2c_base, 3,AddrHigh))//reg_data&0xff);
|
||||
return FALSE;
|
||||
|
||||
//set WR bits(bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Read error[1]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n read receive ACK-reg High address! \n");
|
||||
|
||||
//set the txr reg data with reg address + 0
|
||||
if (!Write32_Data( i2c_base, 3,AddrLow)) //;//reg_data&0xff);
|
||||
return FALSE;
|
||||
//set WR bits(bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x10))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Read error[2]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
// printf("\n read receive ACK-reg Low address! \n");
|
||||
|
||||
//read
|
||||
//set the tx reg audio chip dev address with read bit 1
|
||||
if (!Write32_Data( i2c_base, 3,device_address|0x01))
|
||||
return FALSE;
|
||||
|
||||
//set STA and WR bits(bit7 and bit4)
|
||||
if (!Write32_Data( i2c_base, 4,0x90))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_check( i2c_base)){
|
||||
printf("OC_I2CL_Read error[3]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
|
||||
//read the rxr data
|
||||
|
||||
#if 1
|
||||
for(i=0;i<nReadLength;i++){
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
//set the RD and ACK bit(bit5 and bit3)
|
||||
IOWR( i2c_base, 4,((i+1) == nReadLength)?0x28:0x20);
|
||||
|
||||
if (!ACK_judge_for_read( i2c_base)){
|
||||
printf("OC_I2CL_Read error[4]\r\n");
|
||||
return FALSE;
|
||||
}
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
|
||||
Data32=IORD( i2c_base, 3);
|
||||
*(pData8+i) = Data32 & 0xff;
|
||||
}
|
||||
#else
|
||||
//set the RD and ACK bit(bit5 and bit3)
|
||||
if (!Write32_Data( i2c_base, 4,0x28))
|
||||
return FALSE;
|
||||
|
||||
//wait TIP bit go to 0 to end Tx
|
||||
if(!ACK_judge_for_read( i2c_base))
|
||||
return FALSE;
|
||||
|
||||
// printf("\n read receive ACK-device address(read)! \n");
|
||||
if (!Read32_Data ( i2c_base, 3, &Data32))
|
||||
return FALSE;
|
||||
|
||||
DataHigh = Data32 & 0xff;
|
||||
|
||||
if (!Read32_Data ( i2c_base, 3, &Data32))
|
||||
return FALSE;
|
||||
|
||||
DataLow = Data32 & 0xff;
|
||||
|
||||
pData16 = (DataHigh << 8) | DataLow;
|
||||
#endif
|
||||
|
||||
if (!Write32_Data( i2c_base, 4,0x40))
|
||||
return FALSE;
|
||||
|
||||
//OS_msleep(1);
|
||||
usleep(SLEEP_TIME);
|
||||
|
||||
return TRUE;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* I2C_ocre.h
|
||||
*
|
||||
* Created on: 2014-6-3
|
||||
* Author: niubility
|
||||
*/
|
||||
|
||||
#ifndef I2C_OCRE_H_
|
||||
#define I2C_OCRE_H_
|
||||
#include "alt_types.h" // alt_u32
|
||||
#include "terasic_includes.h"
|
||||
|
||||
#define DEBUG_I2C
|
||||
|
||||
bool oc_i2c_init(alt_32 i2c_base);
|
||||
bool oc_i2c_init_ex(alt_32 i2c_base, alt_32 ref_clk, alt_32 i2c_clk);
|
||||
bool oc_i2c_uninit(alt_32 i2c_base);
|
||||
bool ACK_single_check(alt_32 i2c_base);
|
||||
bool ACK_check(alt_32 i2c_base);
|
||||
bool OC_I2C_Write(alt_32 i2c_base,alt_u8 device_address,alt_u8 sub_address, alt_u8 *pData, int nWriteLength);
|
||||
bool ACK_judge_for_read(alt_32 i2c_base);
|
||||
bool OC_I2C_Read(alt_32 i2c_base,alt_u8 device_address,alt_u8 sub_address, alt_u8 *pData8, int nReadLength);
|
||||
bool OC_I2CL_Write(alt_32 i2c_base,alt_u8 device_address,alt_u16 sub_address,alt_u8 *pData, int nWriteLength);
|
||||
bool OC_I2CL_Read(alt_32 i2c_base,alt_u8 device_address, alt_u16 sub_address, alt_u8 *pData8, int nReadLength);
|
||||
|
||||
//
|
||||
bool OC_I2C_Read_Continue(alt_32 i2c_base,alt_u8 device_address, alt_u8 *pData8, int nReadLength);
|
||||
|
||||
#endif /* I2C_OCRE_H_ */
|
||||
1083
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/Makefile
Normal file
1083
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/Makefile
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,98 @@
|
|||
/*
|
||||
* auto_focus.c
|
||||
*
|
||||
* Created on: 2015Äê7ÔÂ27ÈÕ
|
||||
* Author: Administrato
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "I2C_core.h"
|
||||
#include "terasic_includes.h"
|
||||
#include "auto_focus.h"
|
||||
|
||||
|
||||
/////////////////////////////////
|
||||
//This is a simple focus function for demonstration, focus function may be not good for some situation
|
||||
//arithmetic not suit for: 1. microspur 2.light source
|
||||
// please look at TERASIC_AUTO_FOCUS IP to see register's detail.
|
||||
alt_u16 video_w = 640;
|
||||
alt_u16 video_h = 480;
|
||||
|
||||
alt_u16 focus_width = 240; // <video w
|
||||
alt_u16 focus_height = 180; // <video h
|
||||
// please observe focus performance when change the scal ,scal_f. or when change camera frame rate
|
||||
alt_u8 focus_scal = 4; // scan 0 -> 1023 , step: SCAL , to find STEP_UP
|
||||
alt_u8 focus_scal_f = 1; // scan STEP_UP + - SCAL/2 , step: SCAL_F
|
||||
alt_u8 focus_th = 20;
|
||||
|
||||
void Focus_Init(void){
|
||||
// please look at TERASIC_AUTO_FOCUS IP to see register's detail.
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_CTRL, 0);// focus mode : 1: window-screen, 0: full-screen
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_FOCUS_W, focus_width);// focus_width
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_FOCUS_H, focus_height);// focus_height
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_FOCUS_X_START, video_w/2-focus_width/2);//x_start
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_FOCUS_Y_START, video_h/2-focus_height/2);// y_start
|
||||
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_SCAL, focus_scal*256 + focus_scal_f); // scan 0 -> 1023 , step: SCAL , to find STEP_UP
|
||||
// scan STEP_UP + - SCAL/2 , step: SCAL_F
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_TH, focus_th);
|
||||
|
||||
//////////// focus at initial time
|
||||
usleep(100);
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_GO, 1);
|
||||
usleep(2);
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_GO, 0);
|
||||
}
|
||||
|
||||
alt_u16 Focus_Window(int x,int y){
|
||||
alt_u16 x_start,y_start;
|
||||
alt_u16 end_focus;
|
||||
|
||||
if(Focus_Released()) { // pre focus done
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_CTRL, 1);// focus mode : 1: window-screen, 0: full-screen
|
||||
|
||||
if(( x - focus_width/2) < 0 ) x_start = 0;
|
||||
else if(( x + focus_width/2 ) > video_w ) x_start = video_w -1 -focus_width;
|
||||
else x_start = x - focus_width/2;
|
||||
|
||||
if(( y - focus_height/2) < 0 ) y_start = 0;
|
||||
else if(( y + focus_height/2 ) > video_h ) y_start = video_h -1 -focus_height;
|
||||
else y_start = y - focus_height/2;
|
||||
|
||||
printf("x_start= %d,y_start= %d\n",x_start,y_start);
|
||||
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_FOCUS_X_START, x_start);//x_start
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_FOCUS_Y_START, y_start);//y_start
|
||||
|
||||
usleep(10);
|
||||
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_GO, 1);
|
||||
usleep(2);
|
||||
IOWR(TERASIC_AUTO_FOCUS_0_BASE,REG_GO, 0);
|
||||
Focus_Released();
|
||||
|
||||
end_focus = IORD(TERASIC_AUTO_FOCUS_0_BASE,REG_STATUS)&0x0FFF;
|
||||
printf("end_focus = %d \n",end_focus);
|
||||
|
||||
return end_focus;
|
||||
|
||||
}
|
||||
return end_focus;
|
||||
|
||||
}
|
||||
|
||||
int Focus_Released(void){
|
||||
int Released = FALSE;
|
||||
alt_u32 TimeOut;
|
||||
|
||||
TimeOut = alt_nticks() + alt_ticks_per_second()*8;
|
||||
|
||||
while((IORD(TERASIC_AUTO_FOCUS_0_BASE,REG_STATUS)&0x8000) ==0 && alt_nticks() < TimeOut ); // waiting for VCM release I2C bus
|
||||
|
||||
if(alt_nticks() < TimeOut ) Released = TRUE;
|
||||
else printf("\n =>¡¡Released check TimeOut!\n");
|
||||
|
||||
usleep(10000);
|
||||
|
||||
return Released;
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* auto_focus.h
|
||||
*
|
||||
* Created on: 2015Äê7ÔÂ27ÈÕ
|
||||
* Author: Administrator
|
||||
*/
|
||||
|
||||
#ifndef AUTO_FOCUS_H_
|
||||
#define AUTO_FOCUS_H_
|
||||
|
||||
// write
|
||||
#define REG_GO 0
|
||||
#define REG_CTRL 1
|
||||
#define REG_FOCUS_W 2
|
||||
#define REG_FOCUS_H 3
|
||||
#define REG_FOCUS_X_START 4
|
||||
#define REG_FOCUS_Y_START 5
|
||||
#define REG_SCAL 6 // scan 0 -> 1023 , step: SCAL , to find STEP_UP
|
||||
// scan STEP_UP + - SCAL/2 , step: SCAL_F
|
||||
#define REG_TH 7
|
||||
|
||||
// read
|
||||
#define REG_STATUS 0
|
||||
|
||||
void Focus_Init(void);
|
||||
alt_u16 Focus_Window(int x,int y);
|
||||
int Focus_Released(void);
|
||||
|
||||
|
||||
#endif /* AUTO_FOCUS_H_ */
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
#!/bin/bash
|
||||
#
|
||||
# This script creates the hello_world application in this directory.
|
||||
|
||||
|
||||
BSP_DIR=../D8M_Camera_Test_bsp
|
||||
QUARTUS_PROJECT_DIR=../../
|
||||
NIOS2_APP_GEN_ARGS="--elf-name D8M_Camera_Test.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_world.c"
|
||||
|
||||
|
||||
# First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
|
||||
# This variable is required for the command line tools to execute correctly.
|
||||
if [ -z "${SOPC_KIT_NIOS2}" ]
|
||||
then
|
||||
echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
|
||||
exit 1
|
||||
fi
|
||||
|
||||
|
||||
# Also make sure that the APP has not been created already. Check for
|
||||
# existence of Makefile in the app directory
|
||||
if [ -f ./Makefile ]
|
||||
then
|
||||
echo Application has already been created! Delete Makefile if you want to create a new application makefile
|
||||
exit 1
|
||||
fi
|
||||
|
||||
|
||||
# We are selecting hal_default bsp because it supports this application.
|
||||
# Check to see if the hal_default has already been generated by checking for
|
||||
# existence of the public.mk file. If not, we need to run
|
||||
# create-this-bsp file to generate the bsp.
|
||||
if [ ! -f ${BSP_DIR}/public.mk ]; then
|
||||
# Since BSP doesn't exist, create the BSP
|
||||
# Pass any command line arguments passed to this script to the BSP.
|
||||
pushd ${BSP_DIR} >> /dev/null
|
||||
./create-this-bsp "$@" || {
|
||||
echo "create-this-bsp failed"
|
||||
exit 1
|
||||
}
|
||||
popd >> /dev/null
|
||||
fi
|
||||
|
||||
|
||||
# Don't run make if create-this-app script is called with --no-make arg
|
||||
SKIP_MAKE=
|
||||
while [ $# -gt 0 ]
|
||||
do
|
||||
case "$1" in
|
||||
--no-make)
|
||||
SKIP_MAKE=1
|
||||
;;
|
||||
esac
|
||||
shift
|
||||
done
|
||||
|
||||
|
||||
# Now we also need to go copy the sources for this application to the
|
||||
# local directory.
|
||||
find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
|
||||
echo "failed during copying example source files"
|
||||
exit 1
|
||||
}
|
||||
|
||||
find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
|
||||
echo "failed copying readme file"
|
||||
}
|
||||
|
||||
if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" ]
|
||||
then
|
||||
cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" . || {
|
||||
echo "failed during copying project support files"
|
||||
exit 1
|
||||
}
|
||||
fi
|
||||
|
||||
chmod -R +w . || {
|
||||
echo "failed during changing file permissions"
|
||||
exit 1
|
||||
}
|
||||
|
||||
cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
|
||||
|
||||
echo "create-this-app: Running \"${cmd}\""
|
||||
$cmd || {
|
||||
echo "nios2-app-generate-makefile failed"
|
||||
exit 1
|
||||
}
|
||||
|
||||
if [ -z "$SKIP_MAKE" ]; then
|
||||
cmd="make"
|
||||
|
||||
echo "create-this-app: Running \"$cmd\""
|
||||
$cmd || {
|
||||
echo "make failed"
|
||||
exit 1
|
||||
}
|
||||
|
||||
echo
|
||||
echo "To download and run the application:"
|
||||
echo " 1. Make sure the board is connected to the system."
|
||||
echo " 2. Run 'nios2-configure-sof <SOF_FILE_PATH>' to configure the FPGA with the hardware design."
|
||||
echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell."
|
||||
echo " 4. Run 'make download-elf' from the application directory."
|
||||
echo
|
||||
echo "To debug the application:"
|
||||
echo " Import the project into Nios II Software Build Tools for Eclipse."
|
||||
echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
|
||||
echo
|
||||
echo -e ""
|
||||
fi
|
||||
|
||||
|
||||
exit 0
|
||||
301
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/main.c
Normal file
301
Vision/DE10_LITE_D8M_VIP_16/software/D8M_Camera_Test/main.c
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
|
||||
|
||||
#include <stdio.h>
|
||||
#include "I2C_core.h"
|
||||
#include "terasic_includes.h"
|
||||
#include "mipi_camera_config.h"
|
||||
#include "mipi_bridge_config.h"
|
||||
|
||||
#include "auto_focus.h"
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <unistd.h>
|
||||
|
||||
//EEE_IMGPROC defines
|
||||
#define EEE_IMGPROC_MSG_START ('R'<<16 | 'B'<<8 | 'B')
|
||||
|
||||
//offsets
|
||||
#define EEE_IMGPROC_STATUS 0
|
||||
#define EEE_IMGPROC_MSG 1
|
||||
#define EEE_IMGPROC_ID 2
|
||||
#define EEE_IMGPROC_BBCOL 3
|
||||
|
||||
#define EXPOSURE_INIT 0x002000
|
||||
#define EXPOSURE_STEP 0x100
|
||||
#define GAIN_INIT 0x080
|
||||
#define GAIN_STEP 0x040
|
||||
#define DEFAULT_LEVEL 3
|
||||
|
||||
#define MIPI_REG_PHYClkCtl 0x0056
|
||||
#define MIPI_REG_PHYData0Ctl 0x0058
|
||||
#define MIPI_REG_PHYData1Ctl 0x005A
|
||||
#define MIPI_REG_PHYData2Ctl 0x005C
|
||||
#define MIPI_REG_PHYData3Ctl 0x005E
|
||||
#define MIPI_REG_PHYTimDly 0x0060
|
||||
#define MIPI_REG_PHYSta 0x0062
|
||||
#define MIPI_REG_CSIStatus 0x0064
|
||||
#define MIPI_REG_CSIErrEn 0x0066
|
||||
#define MIPI_REG_MDLSynErr 0x0068
|
||||
#define MIPI_REG_FrmErrCnt 0x0080
|
||||
#define MIPI_REG_MDLErrCnt 0x0090
|
||||
|
||||
void mipi_clear_error(void){
|
||||
MipiBridgeRegWrite(MIPI_REG_CSIStatus,0x01FF); // clear error
|
||||
MipiBridgeRegWrite(MIPI_REG_MDLSynErr,0x0000); // clear error
|
||||
MipiBridgeRegWrite(MIPI_REG_FrmErrCnt,0x0000); // clear error
|
||||
MipiBridgeRegWrite(MIPI_REG_MDLErrCnt, 0x0000); // clear error
|
||||
|
||||
MipiBridgeRegWrite(0x0082,0x00);
|
||||
MipiBridgeRegWrite(0x0084,0x00);
|
||||
MipiBridgeRegWrite(0x0086,0x00);
|
||||
MipiBridgeRegWrite(0x0088,0x00);
|
||||
MipiBridgeRegWrite(0x008A,0x00);
|
||||
MipiBridgeRegWrite(0x008C,0x00);
|
||||
MipiBridgeRegWrite(0x008E,0x00);
|
||||
MipiBridgeRegWrite(0x0090,0x00);
|
||||
}
|
||||
|
||||
void mipi_show_error_info(void){
|
||||
|
||||
alt_u16 PHY_status, SCI_status, MDLSynErr, FrmErrCnt, MDLErrCnt;
|
||||
|
||||
PHY_status = MipiBridgeRegRead(MIPI_REG_PHYSta);
|
||||
SCI_status = MipiBridgeRegRead(MIPI_REG_CSIStatus);
|
||||
MDLSynErr = MipiBridgeRegRead(MIPI_REG_MDLSynErr);
|
||||
FrmErrCnt = MipiBridgeRegRead(MIPI_REG_FrmErrCnt);
|
||||
MDLErrCnt = MipiBridgeRegRead(MIPI_REG_MDLErrCnt);
|
||||
printf("PHY_status=%xh, CSI_status=%xh, MDLSynErr=%xh, FrmErrCnt=%xh, MDLErrCnt=%xh\r\n", PHY_status, SCI_status, MDLSynErr,FrmErrCnt, MDLErrCnt);
|
||||
}
|
||||
|
||||
void mipi_show_error_info_more(void){
|
||||
printf("FrmErrCnt = %d\n",MipiBridgeRegRead(0x0080));
|
||||
printf("CRCErrCnt = %d\n",MipiBridgeRegRead(0x0082));
|
||||
printf("CorErrCnt = %d\n",MipiBridgeRegRead(0x0084));
|
||||
printf("HdrErrCnt = %d\n",MipiBridgeRegRead(0x0086));
|
||||
printf("EIDErrCnt = %d\n",MipiBridgeRegRead(0x0088));
|
||||
printf("CtlErrCnt = %d\n",MipiBridgeRegRead(0x008A));
|
||||
printf("SoTErrCnt = %d\n",MipiBridgeRegRead(0x008C));
|
||||
printf("SynErrCnt = %d\n",MipiBridgeRegRead(0x008E));
|
||||
printf("MDLErrCnt = %d\n",MipiBridgeRegRead(0x0090));
|
||||
printf("FIFOSTATUS = %d\n",MipiBridgeRegRead(0x00F8));
|
||||
printf("DataType = 0x%04x\n",MipiBridgeRegRead(0x006A));
|
||||
printf("CSIPktLen = %d\n",MipiBridgeRegRead(0x006E));
|
||||
}
|
||||
|
||||
|
||||
|
||||
bool MIPI_Init(void){
|
||||
bool bSuccess;
|
||||
|
||||
|
||||
bSuccess = oc_i2c_init_ex(I2C_OPENCORES_MIPI_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
if (!bSuccess)
|
||||
printf("failed to init MIPI- Bridge i2c\r\n");
|
||||
|
||||
usleep(50*1000);
|
||||
MipiBridgeInit();
|
||||
|
||||
usleep(500*1000);
|
||||
|
||||
// bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
// if (!bSuccess)
|
||||
// printf("failed to init MIPI- Camera i2c\r\n");
|
||||
|
||||
MipiCameraInit();
|
||||
MIPI_BIN_LEVEL(DEFAULT_LEVEL);
|
||||
// OV8865_FOCUS_Move_to(340);
|
||||
|
||||
// oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE); // Release I2C bus , due to two I2C master shared!
|
||||
|
||||
|
||||
usleep(1000);
|
||||
|
||||
|
||||
// oc_i2c_uninit(I2C_OPENCORES_MIPI_BASE);
|
||||
|
||||
return bSuccess;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
int main()
|
||||
{
|
||||
|
||||
fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);
|
||||
|
||||
printf("DE10-LITE D8M VGA Demo\n");
|
||||
printf("Imperial College EEE2 Project version\n");
|
||||
IOWR(MIPI_PWDN_N_BASE, 0x00, 0x00);
|
||||
IOWR(MIPI_RESET_N_BASE, 0x00, 0x00);
|
||||
|
||||
usleep(2000);
|
||||
IOWR(MIPI_PWDN_N_BASE, 0x00, 0xFF);
|
||||
usleep(2000);
|
||||
IOWR(MIPI_RESET_N_BASE, 0x00, 0xFF);
|
||||
|
||||
printf("Image Processor ID: %x\n",IORD(0x42000,EEE_IMGPROC_ID));
|
||||
//printf("Image Processor ID: %x\n",IORD(EEE_IMGPROC_0_BASE,EEE_IMGPROC_ID)); //Don't know why this doesn't work - definition is in system.h in BSP
|
||||
|
||||
|
||||
usleep(2000);
|
||||
|
||||
|
||||
// MIPI Init
|
||||
if (!MIPI_Init()){
|
||||
printf("MIPI_Init Init failed!\r\n");
|
||||
}else{
|
||||
printf("MIPI_Init Init successfully!\r\n");
|
||||
}
|
||||
|
||||
// while(1){
|
||||
mipi_clear_error();
|
||||
usleep(50*1000);
|
||||
mipi_clear_error();
|
||||
usleep(1000*1000);
|
||||
mipi_show_error_info();
|
||||
// mipi_show_error_info_more();
|
||||
printf("\n");
|
||||
// }
|
||||
|
||||
|
||||
#if 0 // focus sweep
|
||||
printf("\nFocus sweep\n");
|
||||
alt_u16 ii= 350;
|
||||
alt_u8 dir = 0;
|
||||
while(1){
|
||||
if(ii< 50) dir = 1;
|
||||
else if (ii> 1000) dir =0;
|
||||
|
||||
if(dir) ii += 20;
|
||||
else ii -= 20;
|
||||
|
||||
printf("%d\n",ii);
|
||||
OV8865_FOCUS_Move_to(ii);
|
||||
usleep(50*1000);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////
|
||||
alt_u16 bin_level = DEFAULT_LEVEL;
|
||||
alt_u8 manual_focus_step = 10;
|
||||
alt_u16 current_focus = 300;
|
||||
int boundingBoxColour = 0;
|
||||
alt_u32 exposureTime = EXPOSURE_INIT;
|
||||
alt_u16 gain = GAIN_INIT;
|
||||
|
||||
OV8865SetExposure(exposureTime);
|
||||
OV8865SetGain(gain);
|
||||
Focus_Init();
|
||||
while(1){
|
||||
|
||||
// touch KEY0 to trigger Auto focus
|
||||
if((IORD(KEY_BASE,0)&0x03) == 0x02){
|
||||
|
||||
current_focus = Focus_Window(320,240);
|
||||
}
|
||||
// touch KEY1 to ZOOM
|
||||
if((IORD(KEY_BASE,0)&0x03) == 0x01){
|
||||
if(bin_level == 3 )bin_level = 1;
|
||||
else bin_level ++;
|
||||
printf("set bin level to %d\n",bin_level);
|
||||
MIPI_BIN_LEVEL(bin_level);
|
||||
usleep(500000);
|
||||
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
if((IORD(KEY_BASE,0)&0x0F) == 0x0E){
|
||||
|
||||
current_focus = Focus_Window(320,240);
|
||||
}
|
||||
|
||||
// touch KEY1 to trigger Manual focus - step
|
||||
if((IORD(KEY_BASE,0)&0x0F) == 0x0D){
|
||||
|
||||
if(current_focus > manual_focus_step) current_focus -= manual_focus_step;
|
||||
else current_focus = 0;
|
||||
OV8865_FOCUS_Move_to(current_focus);
|
||||
|
||||
}
|
||||
|
||||
// touch KEY2 to trigger Manual focus + step
|
||||
if((IORD(KEY_BASE,0)&0x0F) == 0x0B){
|
||||
current_focus += manual_focus_step;
|
||||
if(current_focus >1023) current_focus = 1023;
|
||||
OV8865_FOCUS_Move_to(current_focus);
|
||||
}
|
||||
|
||||
// touch KEY3 to ZOOM
|
||||
if((IORD(KEY_BASE,0)&0x0F) == 0x07){
|
||||
if(bin_level == 3 )bin_level = 1;
|
||||
else bin_level ++;
|
||||
printf("set bin level to %d\n",bin_level);
|
||||
MIPI_BIN_LEVEL(bin_level);
|
||||
usleep(500000);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
//Read messages from the image processor and print them on the terminal
|
||||
while ((IORD(0x42000,EEE_IMGPROC_STATUS)>>8) & 0xff) { //Find out if there are words to read
|
||||
int word = IORD(0x42000,EEE_IMGPROC_MSG); //Get next word from message buffer
|
||||
if (word == EEE_IMGPROC_MSG_START){ //Newline on message identifier
|
||||
printf("\n");
|
||||
}
|
||||
printf("%08x ",word);
|
||||
}
|
||||
|
||||
//Update the bounding box colour
|
||||
boundingBoxColour = ((boundingBoxColour + 1) & 0xff);
|
||||
IOWR(0x42000, EEE_IMGPROC_BBCOL, (boundingBoxColour << 8) | (0xff - boundingBoxColour));
|
||||
|
||||
//Process input commands
|
||||
int in = getchar();
|
||||
switch (in) {
|
||||
case 'e': {
|
||||
exposureTime += EXPOSURE_STEP;
|
||||
OV8865SetExposure(exposureTime);
|
||||
printf("\nExposure = %x ", exposureTime);
|
||||
break;}
|
||||
case 'd': {
|
||||
exposureTime -= EXPOSURE_STEP;
|
||||
OV8865SetExposure(exposureTime);
|
||||
printf("\nExposure = %x ", exposureTime);
|
||||
break;}
|
||||
case 't': {
|
||||
gain += GAIN_STEP;
|
||||
OV8865SetGain(gain);
|
||||
printf("\nGain = %x ", gain);
|
||||
break;}
|
||||
case 'g': {
|
||||
gain -= GAIN_STEP;
|
||||
OV8865SetGain(gain);
|
||||
printf("\nGain = %x ", gain);
|
||||
break;}
|
||||
case 'r': {
|
||||
current_focus += manual_focus_step;
|
||||
if(current_focus >1023) current_focus = 1023;
|
||||
OV8865_FOCUS_Move_to(current_focus);
|
||||
printf("\nFocus = %x ",current_focus);
|
||||
break;}
|
||||
case 'f': {
|
||||
if(current_focus > manual_focus_step) current_focus -= manual_focus_step;
|
||||
OV8865_FOCUS_Move_to(current_focus);
|
||||
printf("\nFocus = %x ",current_focus);
|
||||
break;}
|
||||
}
|
||||
|
||||
|
||||
//Main loop delay
|
||||
usleep(10000);
|
||||
|
||||
};
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* mipi_bridge_config.c
|
||||
*
|
||||
* Created on: 2015¦~4¤ë22¤é
|
||||
* Author: Administrator
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "I2C_core.h"
|
||||
#include "terasic_includes.h"
|
||||
#include "mipi_bridge_config.h"
|
||||
|
||||
|
||||
typedef struct{
|
||||
alt_u16 Addr;
|
||||
alt_u16 Data;
|
||||
}SZ_MIPI_REG_T;
|
||||
|
||||
#define FIFO_LEVEL 8 // try others? [0~511]
|
||||
#define DATA_FORMAT 0x0010
|
||||
|
||||
// REFCLK 20 MHz
|
||||
// PPIrxCLK 100 MHz
|
||||
// PCLK 25 MHz
|
||||
// MCLK 25 MHz
|
||||
|
||||
|
||||
#define PLL_PRD 1 // 0- 15
|
||||
#define PLL_FBD 39 //0-511
|
||||
#define PLL_FRS 1 //0-3
|
||||
|
||||
#define MCLK_HL 1 // (MCLK_HL+1)+ (MCLK_HL+1)
|
||||
|
||||
|
||||
//2b'00: div 8, 2b'01: div 4, 2b'10: div 2
|
||||
#define PPICLKDIV 2 // ppi_clk:must between 66~125MHz
|
||||
#define MCLKREFDIV 2 // mclkref clock: < 125MHz
|
||||
#define SCLKDIV 0 // sys_clk clock: < 100MHz
|
||||
|
||||
#define WORDCOUNT 800
|
||||
|
||||
|
||||
|
||||
static SZ_MIPI_REG_T MipiBridgeReg[] = {
|
||||
|
||||
{0x0002,0x0001}, // System Control Register
|
||||
{0xFFFF,10}, // delay
|
||||
{0x0002,0x0000}, // System Control Register
|
||||
{0x0016,((PLL_PRD <<12) + PLL_FBD)}, //PLL Control Register 0
|
||||
{0x0018,((PLL_FRS<<10) + (0x2<<8) + (0x1<<1)+ 0x1)}, //PLL Control Register 1
|
||||
{0xFFFF,10}, // delay
|
||||
|
||||
{0x0018,((PLL_FRS<<10) + (0x2<<8) + (0x1<<4) + (0x1<<1)+ 0x1)}, //PLL Control Register 1
|
||||
{0x0020,((PPICLKDIV<<4) + (MCLKREFDIV<<2) + SCLKDIV)}, //PLL Control Register 0
|
||||
{0x000C,((MCLK_HL<<8) + MCLK_HL)}, //MCLK Control Register
|
||||
{0x0060,0x8006},
|
||||
{0x0006,FIFO_LEVEL}, // FiFo Control Register [0~511]
|
||||
// when reaches to this level FiFo controller asserts FiFoRdy for Parallel port to start output data
|
||||
{0x0008,DATA_FORMAT}, //Data FormatControl Register
|
||||
// {0x0022,WORDCOUNT}, //Word Count Register
|
||||
{0x0004,0x8047} // Configuration Control Register
|
||||
|
||||
};
|
||||
|
||||
|
||||
alt_u16 nSWAP16(alt_u16 x){
|
||||
alt_u16 y;
|
||||
//y = (((x) >> 8) & 0xff) | (((x) & 0xff) << 8);
|
||||
|
||||
// y = x;
|
||||
y = (x >> 8) & 0x00ff;
|
||||
y |= (x << 8) & 0xff00;
|
||||
return y;
|
||||
}
|
||||
|
||||
|
||||
void MipiBridgeRegWrite(alt_u16 Addr, alt_u16 Value){
|
||||
const alt_u8 device_address = MIPI_BRIDGE_I2C_ADDR;
|
||||
OC_I2CL_Write(I2C_OPENCORES_MIPI_BASE, device_address, Addr, (alt_u8 *)&Value, sizeof(Value));
|
||||
}
|
||||
|
||||
alt_u16 MipiBridgeRegRead(alt_u16 Addr){
|
||||
alt_u16 Value,tValue;
|
||||
const alt_u8 device_address = MIPI_BRIDGE_I2C_ADDR;
|
||||
|
||||
OC_I2CL_Read(I2C_OPENCORES_MIPI_BASE,device_address, Addr,(alt_u8 *)&Value,sizeof(Value));
|
||||
|
||||
tValue = nSWAP16(Value);
|
||||
|
||||
return (tValue);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
void MipiBridgeInit(void){
|
||||
|
||||
alt_u16 data;
|
||||
int i, num;
|
||||
|
||||
printf("\nStart MipiBridgeInit!\n");
|
||||
|
||||
data = MipiBridgeRegRead(0x0000); // read chip and revision id;
|
||||
|
||||
printf("Chip and Revision ID is 0x%04xh(expected: 0x4401);\n",data);
|
||||
|
||||
|
||||
num = sizeof(MipiBridgeReg)/sizeof(MipiBridgeReg[0]);
|
||||
|
||||
for(i=0;i<num;i++){
|
||||
if (MipiBridgeReg[i].Addr == 0xFFFF) usleep(MipiBridgeReg[i].Data*1000);
|
||||
else MipiBridgeRegWrite(MipiBridgeReg[i].Addr, MipiBridgeReg[i].Data);
|
||||
}
|
||||
|
||||
|
||||
// alt_u8 cap = 2; // 0- 3
|
||||
// alt_u8 HsRxRs = 2;// 0-3
|
||||
// alt_u8 ClkDly_clk = 0;
|
||||
// alt_u8 ClkDly_data = 15;
|
||||
//
|
||||
// MipiBridgeRegWrite(0x0056,((cap<<6) + (HsRxRs<<4) + ClkDly_clk));
|
||||
// MipiBridgeRegWrite(0x0058,((cap<<6) + (HsRxRs<<4) + ClkDly_data));
|
||||
// MipiBridgeRegWrite(0x005A,((cap<<6) + (HsRxRs<<4) + ClkDly_data));
|
||||
// MipiBridgeRegWrite(0x005C,((cap<<6) + (HsRxRs<<4) + ClkDly_data));
|
||||
// MipiBridgeRegWrite(0x005E,((cap<<6) + (HsRxRs<<4) + ClkDly_data));
|
||||
//
|
||||
|
||||
printf("End MipiBridgeInit!\n\n");
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* mipi_bridge_config.h
|
||||
*
|
||||
* Created on: 2015Äê4ÔÂ22ÈÕ
|
||||
* Author: Administrator
|
||||
*/
|
||||
|
||||
#ifndef MIPI_BRIDGE_CONFIG_H_
|
||||
#define MIPI_BRIDGE_CONFIG_H_
|
||||
|
||||
#define MIPI_BRIDGE_I2C_ADDR 0x1C // 8'b0001_1100 - 7'b0E + 1'b0 (write bit)
|
||||
|
||||
|
||||
void MipiBridgeInit(void);
|
||||
|
||||
void MipiBridgeRegWrite(alt_u16 Addr, alt_u16 Value);
|
||||
alt_u16 MipiBridgeRegRead(alt_u16 Addr);
|
||||
#endif /* MIPI_BRIDGE_CONFIG_H_ */
|
||||
|
|
@ -0,0 +1,658 @@
|
|||
/*
|
||||
* config_reg.c
|
||||
*
|
||||
* Created on: 2015/3/27
|
||||
* Author: User
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "I2C_core.h"
|
||||
#include "terasic_includes.h"
|
||||
#include "system.h"
|
||||
#include "mipi_camera_config.h"
|
||||
#include "auto_focus.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#define Sleep(x) usleep(x*1000)
|
||||
#define OV8865DB(x) printf(x)
|
||||
|
||||
typedef struct{
|
||||
alt_u8 Type;
|
||||
alt_u16 Addr;
|
||||
alt_u8 Data;
|
||||
}SZ_CONFIG_T;
|
||||
|
||||
|
||||
#define REG_8BIT 1
|
||||
#define REG_16BIT 2
|
||||
#define TIME_DELAY 3
|
||||
#define END_OF_SCRIPT 4
|
||||
|
||||
static SZ_CONFIG_T MipiCameraReg[] = {
|
||||
{0x6c,0x0103, 0x01}, // software reset
|
||||
{TIME_DELAY, 0, 10},
|
||||
{0x6c,0x0100, 0x00}, // software standby
|
||||
{0x6c,0x0100, 0x00}, // software standby
|
||||
{0x6c,0x0100, 0x00}, // software standby
|
||||
{0x6c,0x0100, 0x00}, // software standby
|
||||
{TIME_DELAY, 0, 10},
|
||||
|
||||
{0x6c,0x3638, 0xff}, // analog control
|
||||
// 25MHz MCLK input
|
||||
// PHY_CLK : 600 MHz (data rate,not clock rate)
|
||||
// PCLK : 75 MHz
|
||||
// SCLK : 150 MHz
|
||||
{0x6c,0x0302, 24}, // PLL pll1_multiplier
|
||||
{0x6c,0x0303, 0x00}, // PLL pll1_divm1+pll1_divm
|
||||
{0x6c,0x0304, 3}, // PLL pll1_div_mipi
|
||||
|
||||
{0x6c,0x030e, 0x00}, // PLL pll2_r_divs : /1
|
||||
{0x6c,0x030f, 0x04}, // PLL 1 + pll2_r_divsp
|
||||
{0x6c,0x0312, 0x01}, // PLL pll2_pre_div0: /1,pll2_r_divdac1+pll2_r_divdac
|
||||
{0x6c,0x031e, 0x0c}, // PLL
|
||||
|
||||
{0x6c,0x3015, 0x01}, // clock Div
|
||||
{0x6c,0x3018, 0x72}, // MIPI 4 lane
|
||||
{0x6c,0x3020, 0x93}, // clock normal, pclk/1
|
||||
{0x6c,0x3022, 0x01}, // pd_mini enable when rst_sync
|
||||
{0x6c,0x3031, 0x0a}, // 10-bit
|
||||
{0x6c,0x3106, 0x01}, // PLL
|
||||
{0x6c,0x3305, 0xf1},
|
||||
{0x6c,0x3308, 0x00},
|
||||
{0x6c,0x3309, 0x28},
|
||||
{0x6c,0x330a, 0x00},
|
||||
{0x6c,0x330b, 0x20},
|
||||
{0x6c,0x330c, 0x00},
|
||||
{0x6c,0x330d, 0x00},
|
||||
{0x6c,0x330e, 0x00},
|
||||
{0x6c,0x330f, 0x40},
|
||||
{0x6c,0x3307, 0x04},
|
||||
{0x6c,0x3604, 0x04}, // analog control
|
||||
{0x6c,0x3602, 0x30},
|
||||
{0x6c,0x3605, 0x00},
|
||||
{0x6c,0x3607, 0x20},
|
||||
{0x6c,0x3608, 0x11},
|
||||
{0x6c,0x3609, 0x68},
|
||||
{0x6c,0x360a, 0x40},
|
||||
{0x6c,0x360c, 0xdd},
|
||||
{0x6c,0x360e, 0x0c},
|
||||
{0x6c,0x3610, 0x07},
|
||||
{0x6c,0x3612, 0x86},
|
||||
{0x6c,0x3613, 0x58},
|
||||
{0x6c,0x3614, 0x28},
|
||||
{0x6c,0x3617, 0x40},
|
||||
{0x6c,0x3618, 0x5a},
|
||||
{0x6c,0x3619, 0x9b},
|
||||
{0x6c,0x361c, 0x00},
|
||||
{0x6c,0x361d, 0x60},
|
||||
{0x6c,0x3631, 0x60},
|
||||
{0x6c,0x3633, 0x10},
|
||||
{0x6c,0x3634, 0x10},
|
||||
{0x6c,0x3635, 0x10},
|
||||
{0x6c,0x3636, 0x10},
|
||||
{0x6c,0x3641, 0x55}, // MIPI settings
|
||||
{0x6c,0x3646, 0x86}, // MIPI settings
|
||||
{0x6c,0x3647, 0x27}, // MIPI settings
|
||||
{0x6c,0x364a, 0x1b}, // MIPI settings
|
||||
|
||||
// exposure
|
||||
// {0x6c,0x3500, 0x00}, // exposure HH
|
||||
{0x6c,0x3501, 0x18}, // exposure H
|
||||
// {0x6c,0x3502, 0x60}, // exposure L
|
||||
{0x6c,0x3500, 0x00}, // exposure HH
|
||||
{0x6c,0x3501, 0x2C}, // exposure H
|
||||
{0x6c,0x3502, 0x00}, // exposure L
|
||||
|
||||
{0x6c,0x3503, 0x00}, // gain no delay, exposure no delay
|
||||
{0x6c,0x3508, 0x05}, // gain H
|
||||
{0x6c,0x3509, 0x00}, // gain L
|
||||
{0x6c,0x3700, 0x48}, // sensor control // TODO: to check
|
||||
{0x6c,0x3701, 0x18},
|
||||
{0x6c,0x3702, 0x50},
|
||||
{0x6c,0x3703, 0x32},
|
||||
{0x6c,0x3704, 0x28},
|
||||
{0x6c,0x3705, 0x00},
|
||||
{0x6c,0x3706, 0x70},
|
||||
{0x6c,0x3707, 0x08},
|
||||
{0x6c,0x3708, 0x48},
|
||||
{0x6c,0x3709, 0x80},
|
||||
{0x6c,0x370a, 0x01},
|
||||
{0x6c,0x370b, 0x70},
|
||||
{0x6c,0x370c, 0x07},
|
||||
{0x6c,0x3718, 0x14},
|
||||
{0x6c,0x3719, 0x31},
|
||||
{0x6c,0x3712, 0x44},
|
||||
{0x6c,0x3714, 0x12},
|
||||
{0x6c,0x371e, 0x31},
|
||||
{0x6c,0x371f, 0x7f},
|
||||
{0x6c,0x3720, 0x0a},
|
||||
{0x6c,0x3721, 0x0a},
|
||||
{0x6c,0x3724, 0x04},
|
||||
{0x6c,0x3725, 0x04},
|
||||
{0x6c,0x3726, 0x0c},
|
||||
{0x6c,0x3728, 0x0a},
|
||||
{0x6c,0x3729, 0x03},
|
||||
{0x6c,0x372a, 0x06},
|
||||
{0x6c,0x372b, 0xa6},
|
||||
{0x6c,0x372c, 0xa6},
|
||||
{0x6c,0x372d, 0xa6},
|
||||
{0x6c,0x372e, 0x0c},
|
||||
{0x6c,0x372f, 0x20},
|
||||
{0x6c,0x3730, 0x02},
|
||||
{0x6c,0x3731, 0x0c},
|
||||
{0x6c,0x3732, 0x28},
|
||||
{0x6c,0x3733, 0x10},
|
||||
{0x6c,0x3734, 0x40},
|
||||
{0x6c,0x3736, 0x30},
|
||||
{0x6c,0x373a, 0x04},
|
||||
{0x6c,0x373b, 0x18},
|
||||
{0x6c,0x373c, 0x14},
|
||||
{0x6c,0x373e, 0x06},
|
||||
{0x6c,0x3755, 0x40},
|
||||
{0x6c,0x3758, 0x00},
|
||||
{0x6c,0x3759, 0x4c},
|
||||
{0x6c,0x375a, 0x0c},
|
||||
{0x6c,0x375b, 0x26},
|
||||
{0x6c,0x375c, 0x20},
|
||||
{0x6c,0x375d, 0x04},
|
||||
{0x6c,0x375e, 0x00},
|
||||
{0x6c,0x375f, 0x28},
|
||||
{0x6c,0x3767, 0x04},
|
||||
{0x6c,0x3768, 0x04},
|
||||
{0x6c,0x3769, 0x20},
|
||||
{0x6c,0x376c, 0x00},
|
||||
{0x6c,0x376d, 0x00},
|
||||
{0x6c,0x376a, 0x08},
|
||||
{0x6c,0x3761, 0x00},
|
||||
{0x6c,0x3762, 0x00},
|
||||
{0x6c,0x3763, 0x00},
|
||||
{0x6c,0x3766, 0xff},
|
||||
{0x6c,0x376b, 0x42},
|
||||
{0x6c,0x3772, 0x46},
|
||||
{0x6c,0x3773, 0x04},
|
||||
{0x6c,0x3774, 0x2c},
|
||||
{0x6c,0x3775, 0x13},
|
||||
{0x6c,0x3776, 0x10},
|
||||
{0x6c,0x37a0, 0x88},
|
||||
{0x6c,0x37a1, 0x7a},
|
||||
{0x6c,0x37a2, 0x7a},
|
||||
{0x6c,0x37a3, 0x02},
|
||||
{0x6c,0x37a4, 0x00},
|
||||
{0x6c,0x37a5, 0x09},
|
||||
{0x6c,0x37a6, 0x00},
|
||||
{0x6c,0x37a7, 0x88},
|
||||
{0x6c,0x37a8, 0xb0},
|
||||
{0x6c,0x37a9, 0xb0},
|
||||
{0x6c,0x3760, 0x00},
|
||||
{0x6c,0x376f, 0x01},
|
||||
{0x6c,0x37aa, 0x88},
|
||||
{0x6c,0x37ab, 0x5c},
|
||||
{0x6c,0x37ac, 0x5c},
|
||||
{0x6c,0x37ad, 0x55},
|
||||
{0x6c,0x37ae, 0x19},
|
||||
{0x6c,0x37af, 0x19},
|
||||
{0x6c,0x37b0, 0x00},
|
||||
{0x6c,0x37b1, 0x00},
|
||||
{0x6c,0x37b2, 0x00},
|
||||
{0x6c,0x37b3, 0x84},
|
||||
{0x6c,0x37b4, 0x84},
|
||||
{0x6c,0x37b5, 0x66},
|
||||
{0x6c,0x37b6, 0x00},
|
||||
{0x6c,0x37b7, 0x00},
|
||||
{0x6c,0x37b8, 0x00},
|
||||
{0x6c,0x37b9, 0xff}, // sensor control
|
||||
// don't care , use auto size
|
||||
// {0x6c,0x3800, 0x00}, // X start H
|
||||
// {0x6c,0x3801, 0x0c}, // X start L
|
||||
// {0x6c,0x3802, 0x00}, // Y start H
|
||||
// {0x6c,0x3803, 0x0c}, // Y start L
|
||||
// {0x6c,0x3804, 0x0c}, // X end H
|
||||
// {0x6c,0x3805, 0xd3}, // X end L
|
||||
// {0x6c,0x3806, 0x09}, // Y end H
|
||||
// {0x6c,0x3807, 0xa3}, // Y end L
|
||||
|
||||
|
||||
// // 800x600
|
||||
// {0x6c,0x3808, 0x03}, // X output size H
|
||||
// {0x6c,0x3809, 0x20}, // X output size L
|
||||
// {0x6c,0x380a, 0x02}, // Y output size H
|
||||
// {0x6c,0x380b, 0x58}, // Y output size L
|
||||
|
||||
// 640x480
|
||||
{0x6c,0x3808, 0x02}, // X output size H
|
||||
{0x6c,0x3809, 0x80}, // X output size L
|
||||
{0x6c,0x380a, 0x01}, // Y output size H
|
||||
{0x6c,0x380b, 0xE0}, // Y output size L
|
||||
|
||||
|
||||
|
||||
// 60 fps (combined with pll settings)
|
||||
{0x6c,0x380c, 0x12}, // HTS H
|
||||
{0x6c,0x380d, 0x00}, // HTS L
|
||||
{0x6c,0x380e, 0x02}, // VTS H
|
||||
{0x6c,0x380f, 0x1E}, // VTS L
|
||||
|
||||
|
||||
|
||||
{0x6c,0x3810, 0x00}, // ISP X win H
|
||||
{0x6c,0x3811, 0x04}, // ISP X win L
|
||||
{0x6c,0x3813, 0x02}, // ISP Y win L
|
||||
|
||||
{0x6c,0x3814, 0x01}, // X inc odd
|
||||
{0x6c,0x3815, 0x01}, // X inc even
|
||||
{0x6c,0x3820, 0x06}, // flip on
|
||||
{0x6c,0x3821, 0x70}, // hsync_en_o, fst_vbin, mirror on
|
||||
{0x6c,0x382a, 0x01}, // Y inc odd
|
||||
{0x6c,0x382b, 0x01}, // Y inc even
|
||||
{0x6c,0x3830, 8}, // ablc_use_num[5:1]
|
||||
{0x6c,0x3836, 2}, // zline_use_num[5:1]
|
||||
{0x6c,0x3837, 0x18}, // vts_add_dis, cexp_gt_vts_offs=8
|
||||
{0x6c,0x3841, 0xff}, // auto size
|
||||
{0x6c,0x3846, 0x48}, // Y/X boundary pixel number for auto size mode
|
||||
{0x6c,0x3f08, 0x16},
|
||||
{0x6c,0x4000, 0xf1}, // our range trig en, format chg en, gan chg en, exp chg en, median en
|
||||
{0x6c,0x4001, 0x04}, // left 32 column, final BLC offset limitation enable
|
||||
{0x6c,0x4005, 0x10}, // BLC target
|
||||
{0x6c,0x400b, 0x0c}, // start line =0, offset limitation en, cut range function en
|
||||
{0x6c,0x400d, 0x10}, // offset trigger threshold
|
||||
{0x6c,0x4011, 0x30},
|
||||
{0x6c,0x4013, 0xcf},
|
||||
{0x6c,0x401b, 0x00},
|
||||
{0x6c,0x401d, 0x00},
|
||||
{0x6c,0x4020, 0x02}, // anchor left start H
|
||||
{0x6c,0x4021, 0x40}, // anchor left start L
|
||||
{0x6c,0x4022, 0x03}, // anchor left end H
|
||||
{0x6c,0x4023, 0x3f}, // anchor left end L
|
||||
{0x6c,0x4024, 0x07}, // anchor right start H
|
||||
{0x6c,0x4025, 0xc0}, // anchor right start L
|
||||
{0x6c,0x4026, 0x08}, // anchor right end H
|
||||
{0x6c,0x4027, 0xbf}, // anchor right end L
|
||||
{0x6c,0x4028, 0x00}, // top zero line start
|
||||
{0x6c,0x4029, 0x02}, // top zero line number
|
||||
{0x6c,0x402a, 0x04}, // top black line start
|
||||
{0x6c,0x402b, 0x04}, // top black line number
|
||||
{0x6c,0x402c, 0x02}, // bottom zero line start
|
||||
{0x6c,0x402d, 0x02}, // bottom zero line number
|
||||
{0x6c,0x402e, 0x08}, // bottom black line start
|
||||
{0x6c,0x402f, 0x02}, // bottom black line number
|
||||
{0x6c,0x401f, 0x00}, // anchor one disable
|
||||
{0x6c,0x4034, 0x3f}, // limitation BLC offset
|
||||
{0x6c,0x4300, 0xff}, // clip max H
|
||||
{0x6c,0x4301, 0x00}, // clip min H
|
||||
{0x6c,0x4302, 0x0f}, // clip min L/clip max L
|
||||
{0x6c,0x4500, 0x68}, // ADC sync control
|
||||
|
||||
{0x6c,0x4503, 0x10},
|
||||
{0x6c,0x4601, 0x10}, // V FIFO control
|
||||
|
||||
// clock prepare 50+ Tui*ui_clk_prepare_min(0) : 50 ns
|
||||
{0x6c,0x481f, 70}, // clk_prepare_min
|
||||
|
||||
{0x6c,0x4837, 0x16}, // clock period
|
||||
{0x6c,0x4850, 0x10}, // lane select
|
||||
{0x6c,0x4851, 0x32}, // lane select
|
||||
{0x6c,0x4b00, 0x2a}, // LVDS settings
|
||||
{0x6c,0x4b0d, 0x00}, // LVDS settings
|
||||
{0x6c,0x4d00, 0x04}, // temperature sensor
|
||||
{0x6c,0x4d01, 0x18}, // temperature sensor
|
||||
{0x6c,0x4d02, 0xc3}, // temperature sensor
|
||||
{0x6c,0x4d03, 0xff}, // temperature sensor
|
||||
{0x6c,0x4d04, 0xff}, // temperature sensor
|
||||
{0x6c,0x4d05, 0xff}, // temperature sensor
|
||||
{0x6c,0x5000, 0x16}, // LENC on, MWB on, BPC on, WPC on
|
||||
{0x6c,0x5001, 0x01}, // BLC on
|
||||
{0x6c,0x5002, 0x08}, // vario pixel off
|
||||
{0x6c,0x5901, 0x00},
|
||||
|
||||
{0x6c,0x5e00, 0x00}, // test pattern off
|
||||
|
||||
|
||||
{0x6c,0x5018, 0x15}, // Red MWB gain
|
||||
{0x6c,0x501A, 0x10}, // Green MWB gain
|
||||
{0x6c,0x501C, 0x15}, // Blue MWB gain
|
||||
|
||||
|
||||
#if 0 // test pattern
|
||||
{0x6c,0x5e00, 0x82}, // test pattern on
|
||||
#endif
|
||||
{0x6c,0x5e01, 0x41}, // window cut enable
|
||||
|
||||
|
||||
{TIME_DELAY, 0, 10},
|
||||
|
||||
{0x6c,0x5780, 0xfc},
|
||||
{0x6c,0x5781, 0xdf},
|
||||
{0x6c,0x5782, 0x3f},
|
||||
{0x6c,0x5783, 0x08},
|
||||
{0x6c,0x5784, 0x0c},
|
||||
{0x6c,0x5786, 0x20},
|
||||
{0x6c,0x5787, 0x40},
|
||||
{0x6c,0x5788, 0x08},
|
||||
{0x6c,0x5789, 0x08},
|
||||
{0x6c,0x578a, 0x02},
|
||||
{0x6c,0x578b, 0x01},
|
||||
{0x6c,0x578c, 0x01},
|
||||
{0x6c,0x578d, 0x0c},
|
||||
{0x6c,0x578e, 0x02},
|
||||
{0x6c,0x578f, 0x01},
|
||||
{0x6c,0x5790, 0x01},
|
||||
{0x6c,0x5800, 0x1d}, // lens correction
|
||||
{0x6c,0x5801, 0x0e},
|
||||
{0x6c,0x5802, 0x0c},
|
||||
{0x6c,0x5803, 0x0c},
|
||||
{0x6c,0x5804, 0x0f},
|
||||
{0x6c,0x5805, 0x22},
|
||||
{0x6c,0x5806, 0x0a},
|
||||
{0x6c,0x5807, 0x06},
|
||||
{0x6c,0x5808, 0x05},
|
||||
{0x6c,0x5809, 0x05},
|
||||
{0x6c,0x580a, 0x07},
|
||||
{0x6c,0x580b, 0x0a},
|
||||
{0x6c,0x580c, 0x06},
|
||||
{0x6c,0x580d, 0x02},
|
||||
{0x6c,0x580e, 0x00},
|
||||
{0x6c,0x580f, 0x00},
|
||||
{0x6c,0x5810, 0x03},
|
||||
{0x6c,0x5811, 0x07},
|
||||
{0x6c,0x5812, 0x06},
|
||||
{0x6c,0x5813, 0x02},
|
||||
{0x6c,0x5814, 0x00},
|
||||
{0x6c,0x5815, 0x00},
|
||||
{0x6c,0x5816, 0x03},
|
||||
{0x6c,0x5817, 0x07},
|
||||
{0x6c,0x5818, 0x09},
|
||||
{0x6c,0x5819, 0x06},
|
||||
{0x6c,0x581a, 0x04},
|
||||
{0x6c,0x581b, 0x04},
|
||||
{0x6c,0x581c, 0x06},
|
||||
{0x6c,0x581d, 0x0a},
|
||||
{0x6c,0x581e, 0x19},
|
||||
{0x6c,0x581f, 0x0d},
|
||||
{0x6c,0x5820, 0x0b},
|
||||
{0x6c,0x5821, 0x0b},
|
||||
{0x6c,0x5822, 0x0e},
|
||||
{0x6c,0x5823, 0x22},
|
||||
{0x6c,0x5824, 0x23},
|
||||
{0x6c,0x5825, 0x28},
|
||||
{0x6c,0x5826, 0x29},
|
||||
{0x6c,0x5827, 0x27},
|
||||
{0x6c,0x5828, 0x13},
|
||||
{0x6c,0x5829, 0x26},
|
||||
{0x6c,0x582a, 0x33},
|
||||
{0x6c,0x582b, 0x32},
|
||||
{0x6c,0x582c, 0x33},
|
||||
{0x6c,0x582d, 0x16},
|
||||
{0x6c,0x582e, 0x14},
|
||||
{0x6c,0x582f, 0x30},
|
||||
{0x6c,0x5830, 0x31},
|
||||
{0x6c,0x5831, 0x30},
|
||||
{0x6c,0x5832, 0x15},
|
||||
{0x6c,0x5833, 0x26},
|
||||
{0x6c,0x5834, 0x23},
|
||||
{0x6c,0x5835, 0x21},
|
||||
{0x6c,0x5836, 0x23},
|
||||
{0x6c,0x5837, 0x05},
|
||||
{0x6c,0x5838, 0x36},
|
||||
{0x6c,0x5839, 0x27},
|
||||
{0x6c,0x583a, 0x28},
|
||||
{0x6c,0x583b, 0x26},
|
||||
{0x6c,0x583c, 0x24},
|
||||
{0x6c,0x583d, 0xdf}, // lens correction
|
||||
|
||||
{0x6c,0x0100, 0x01}, //; wake up, streaming
|
||||
|
||||
{END_OF_SCRIPT, 0, 0}
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
alt_u8 OV8865_read_cmos_sensor_8(alt_u16 Addr){
|
||||
const alt_u8 device_address = MIPI_I2C_ADDR;
|
||||
alt_u8 Value;
|
||||
|
||||
//OC_I2CL_Write(I2C_OPENCORES_CAMERA_BASE, device_address, SWAP16(Addr), (alt_u8 *)&Value, sizeof(Value));
|
||||
OC_I2CL_Read(I2C_OPENCORES_CAMERA_BASE, device_address, Addr, (alt_u8 *)&Value, sizeof(Value));
|
||||
|
||||
return (Value);
|
||||
}
|
||||
|
||||
|
||||
void OV8865_write_cmos_sensor_8(alt_u16 Addr, alt_u8 Value){
|
||||
const alt_u8 device_address = MIPI_I2C_ADDR;
|
||||
//OC_I2CL_Write(I2C_OPENCORES_CAMERA_BASE, device_address, SWAP16(Addr), (alt_u8 *)&Value, sizeof(Value));
|
||||
OC_I2CL_Write(I2C_OPENCORES_CAMERA_BASE, device_address, Addr, (alt_u8 *)&Value, sizeof(Value));
|
||||
}
|
||||
|
||||
|
||||
void OV8865_write_AF(alt_u8 msb, alt_u8 lsb){
|
||||
// VCM149C
|
||||
const alt_u8 device_address = MIPI_AF_I2C_ADDR;
|
||||
OC_I2C_Write(I2C_OPENCORES_CAMERA_BASE, device_address, msb, (alt_u8 *)&lsb, sizeof(lsb));
|
||||
}
|
||||
|
||||
void OV8865_read_AF(void){
|
||||
// VCM149C
|
||||
const alt_u8 device_address = MIPI_AF_I2C_ADDR;
|
||||
alt_u8 szData8[2];
|
||||
bool bSuccess;
|
||||
|
||||
bSuccess = OC_I2C_Read_Continue(I2C_OPENCORES_CAMERA_BASE, device_address, szData8, sizeof(szData8));
|
||||
if (bSuccess)
|
||||
printf("Read MSB=%xh, LSB=%xh\r\n", szData8[0], szData8[1]);
|
||||
}
|
||||
|
||||
void OV8865_FOCUS_Move_to(alt_u16 a_u2MovePosition)
|
||||
{
|
||||
if (a_u2MovePosition > 1023) {a_u2MovePosition = 1023;}
|
||||
if (a_u2MovePosition < 0) {a_u2MovePosition = 0;}
|
||||
int bSuccess;
|
||||
|
||||
Focus_Released(); // waiting for VCM release I2C bus
|
||||
|
||||
bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
if (!bSuccess)
|
||||
printf("failed to init MIPI- Camera i2c\r\n");
|
||||
|
||||
//printf("Manual set focus to %d\r\n",a_u2MovePosition);
|
||||
alt_u8 msb,lsb;
|
||||
msb = (a_u2MovePosition >> 4)&0x00FF;
|
||||
lsb = (a_u2MovePosition << 4 )&0x00F0;
|
||||
lsb += 0x06;
|
||||
// printf("Write MSB=%xh, LSB=%xh\r\n", msb, lsb);
|
||||
OV8865_write_AF(msb, lsb+0x6);
|
||||
usleep(1000);
|
||||
// OV8865_read_AF();
|
||||
|
||||
oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE); // Release I2C bus , due to two I2C master shared!
|
||||
|
||||
}
|
||||
|
||||
void OV8865SetExposure(alt_u32 exposure){
|
||||
|
||||
Focus_Released(); // waiting for VCM release I2C bus
|
||||
|
||||
int bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
if (!bSuccess)
|
||||
printf("failed to init MIPI- Camera i2c\r\n");
|
||||
|
||||
if (exposure > 0xFFFFF) exposure = 0xFFFFF;
|
||||
if (exposure < 0x20) exposure = 0x20;
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3500, (exposure >> 16) & 0x0F);
|
||||
OV8865_write_cmos_sensor_8(0x3501, (exposure >> 8) & 0xFF);
|
||||
OV8865_write_cmos_sensor_8(0x3502, exposure & 0xFF);
|
||||
|
||||
|
||||
oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE);
|
||||
}
|
||||
|
||||
void OV8865SetGain(alt_u16 gain){
|
||||
|
||||
Focus_Released(); // waiting for VCM release I2C bus
|
||||
|
||||
int bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
if (!bSuccess)
|
||||
printf("failed to init MIPI- Camera i2c\r\n");
|
||||
|
||||
if (gain > 0x7FF) gain = 0x7FF;
|
||||
if (gain < 0x080) gain = 0x080;
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3508, (gain >> 8) & 0x0F);
|
||||
OV8865_write_cmos_sensor_8(0x3509, gain & 0xFF);
|
||||
|
||||
|
||||
oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE);
|
||||
}
|
||||
|
||||
alt_u32 OV8865ReadExposure(){
|
||||
|
||||
alt_u32 exposure;
|
||||
|
||||
Focus_Released(); // waiting for VCM release I2C bus
|
||||
|
||||
int bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
if (!bSuccess)
|
||||
printf("failed to init MIPI- Camera i2c\r\n");
|
||||
|
||||
exposure = OV8865_read_cmos_sensor_8(0x3500);
|
||||
exposure = (exposure <<8) | OV8865_read_cmos_sensor_8(0x3501);
|
||||
exposure = (exposure <<8) | OV8865_read_cmos_sensor_8(0x3502);
|
||||
|
||||
oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE);
|
||||
|
||||
return exposure;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
//ZOOM
|
||||
void MIPI_BIN_LEVEL(alt_u8 level){
|
||||
if(level <= 1) level = 1;
|
||||
if(level >= 3) level = 3;
|
||||
|
||||
Focus_Released(); // waiting for VCM release I2C bus
|
||||
|
||||
int bSuccess;
|
||||
bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
if (!bSuccess)
|
||||
printf("failed to init MIPI- Camera i2c\r\n");
|
||||
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x0100, 0x00);
|
||||
|
||||
if(level == 1){
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3814, 0x01);
|
||||
OV8865_write_cmos_sensor_8(0x3815, 0x01);
|
||||
OV8865_write_cmos_sensor_8(0x382a, 0x01);
|
||||
OV8865_write_cmos_sensor_8(0x382b, 0x01);
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3830, 8);
|
||||
OV8865_write_cmos_sensor_8(0x3836, 2);
|
||||
}
|
||||
else if(level == 2){
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3814, 0x03);
|
||||
OV8865_write_cmos_sensor_8(0x3815, 0x01);
|
||||
OV8865_write_cmos_sensor_8(0x382a, 0x03);
|
||||
OV8865_write_cmos_sensor_8(0x382b, 0x01);
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3830, 4);
|
||||
OV8865_write_cmos_sensor_8(0x3836, 1);
|
||||
|
||||
}
|
||||
else if(level == 3){
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3814, 0x07);
|
||||
OV8865_write_cmos_sensor_8(0x3815, 0x01);
|
||||
OV8865_write_cmos_sensor_8(0x382a, 0x07);
|
||||
OV8865_write_cmos_sensor_8(0x382b, 0x01);
|
||||
|
||||
OV8865_write_cmos_sensor_8(0x3830, 8);
|
||||
OV8865_write_cmos_sensor_8(0x3836, 2);
|
||||
}
|
||||
usleep(10000);
|
||||
OV8865_write_cmos_sensor_8(0x0100, 0x01);
|
||||
|
||||
oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE); // Release I2C bus , due to two I2C master shared!
|
||||
|
||||
}
|
||||
//
|
||||
//
|
||||
//void BLC_LEVEL(alt_u8 blc0,alt_u8 blc1){
|
||||
// if(blc0 < 1) blc0 = 0;
|
||||
// if(blc0 >= 31) blc0 = 31;
|
||||
//
|
||||
// if(blc1 < 1) blc1 = 0;
|
||||
// if(blc1 >= 31) blc1 = 31;
|
||||
//
|
||||
// printf("BLC0 %d ,BLC1 %d \n",blc0,blc1);
|
||||
// OV8865_write_cmos_sensor_8(0x0100, 0x00);
|
||||
//
|
||||
// OV8865_write_cmos_sensor_8(0x3830, blc0);
|
||||
// OV8865_write_cmos_sensor_8(0x3836, blc1);
|
||||
//
|
||||
// usleep(10000);
|
||||
// OV8865_write_cmos_sensor_8(0x0100, 0x01);
|
||||
//}
|
||||
|
||||
|
||||
void MipiCameraInit(void)
|
||||
{
|
||||
|
||||
int i, num;
|
||||
int bSuccess;
|
||||
|
||||
Focus_Released(); // waiting for VCM release I2C bus
|
||||
|
||||
|
||||
bSuccess = oc_i2c_init_ex(I2C_OPENCORES_CAMERA_BASE, 50*1000*1000,400*1000); //I2C: 400K
|
||||
if (!bSuccess)
|
||||
printf("failed to init MIPI- Camera i2c\r\n");
|
||||
|
||||
// searching for active I2C address.
|
||||
// int ii;
|
||||
// for(ii= 0; ii<256;ii++){
|
||||
// printf("%x: ",ii);
|
||||
// alt_u8 data = 0x30;
|
||||
// OC_I2C_Write(I2C_OPENCORES_CAMERA_BASE, ii, 0x30, (alt_u8 *)&data, 1);
|
||||
// usleep(10000);
|
||||
// }
|
||||
//
|
||||
|
||||
|
||||
OV8865DB("\nStart MipiCameraInit -OV8865!\r\n");
|
||||
OV8865DB("Write Read Test!\n");
|
||||
|
||||
for(i=0;i<10;i++){
|
||||
OV8865_write_cmos_sensor_8(0x3809,i);
|
||||
usleep(100);
|
||||
printf("%d (%d)\n",OV8865_read_cmos_sensor_8(0x3809),i);
|
||||
usleep(100);
|
||||
}
|
||||
num = sizeof(MipiCameraReg)/sizeof(MipiCameraReg[0]);
|
||||
for(i=0;i<num;i++){
|
||||
|
||||
if (MipiCameraReg[i].Type == TIME_DELAY) usleep(MipiCameraReg[i].Data*100);
|
||||
else if(MipiCameraReg[i].Type == END_OF_SCRIPT) break;
|
||||
else if(MipiCameraReg[i].Type == 0x6c) OV8865_write_cmos_sensor_8(MipiCameraReg[i].Addr, MipiCameraReg[i].Data);
|
||||
}
|
||||
|
||||
|
||||
oc_i2c_uninit(I2C_OPENCORES_CAMERA_BASE); // Release I2C bus , due to two I2C master shared!
|
||||
|
||||
|
||||
|
||||
OV8865DB("\nEnd MipiCameraInit! -OV8865!\r\n\n");
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue