From dce62bdd77b894bb3d4b3fb3713208ed024c03c0 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Tue, 18 May 2021 12:20:27 +0100
Subject: [PATCH] Add Vision initial files from vision resource repo
---
Vision/.gitignore | 11 +
.../DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml | 2167 ++
.../.qsys_edit/Qsys_schematic.nlv | 54 +
.../.qsys_edit/filters.xml | 2 +
.../.qsys_edit/preferences.xml | 14 +
Vision/DE10_LITE_D8M_VIP_16/Chain.cdf | 13 +
.../DE10_LITE_D8M_VIP.SDC | 128 +
.../DE10_LITE_D8M_VIP.htm | 1193 +
.../DE10_LITE_D8M_VIP.qpf | 6 +
.../DE10_LITE_D8M_VIP.qsf | 426 +
.../DE10_LITE_D8M_VIP.qws | Bin 0 -> 1312 bytes
.../DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v | 196 +
.../DE10_LITE_D8M_VIP_assignment_defaults.qdf | 808 +
.../DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl | 183 +
Vision/DE10_LITE_D8M_VIP_16/FpsMonitor.v | 82 +
Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys | 1471 +
Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo | 21866 +++++++++++++++
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf | 431 +
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp | 47 +
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html | 5416 ++++
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml | 5410 ++++
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v | 88 +
.../Qsys/Qsys_generation.rpt | 129 +
.../Qsys/Qsys_generation_previous.rpt | 129 +
Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v | 45 +
.../DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd | 93 +
.../demo_batch/D8M_Camera_Test.elf | Bin 0 -> 1098085 bytes
.../demo_batch/DE10_LITE_D8M_VIP.sof | Bin 0 -> 3326881 bytes
.../DE10_LITE_D8M_VIP_16/demo_batch/test.bat | 26 +
.../DE10_LITE_D8M_VIP_16/demo_batch/test.sh | 6 +
.../greybox_tmp/cbx_args.txt | 61 +
.../DE10_LITE_D8M_VIP_16/hs_err_pid13062.log | 1085 +
.../ip/EEE_IMGPROC/EEE_IMGPROC.v | 305 +
.../ip/EEE_IMGPROC/MSG_FIFO.qip | 6 +
.../ip/EEE_IMGPROC/MSG_FIFO.v | 163 +
.../ip/EEE_IMGPROC/MSG_FIFO_bb.v | 124 +
.../ip/EEE_IMGPROC/MSG_FIFO_inst.v | 10 +
.../ip/EEE_IMGPROC/STREAM_REG.v | 39 +
.../ip/EEE_IMGPROC/STREAM_REG_TEST.v | 51 +
.../ip/EEE_IMGPROC/STREAM_REG_TEST.vwf | 1010 +
.../ip/EEE_IMGPROC/greybox_tmp/cbx_args.txt | 18 +
.../ip/TERASIC_AUTO_FOCUS/F_VCM.v | 56 +
.../ip/TERASIC_AUTO_FOCUS/I2C_VCM_Config.v | 160 +
.../TERASIC_AUTO_FOCUS/I2C_VCM_Controller.v | 157 +
.../TERASIC_AUTO_FOCUS/TERASIC_AUTO_FOCUS.v | 298 +
.../TERASIC_AUTO_FOCUS_hw.tcl | 214 +
.../ip/TERASIC_AUTO_FOCUS/VCM_CTRL_P.v | 99 +
.../ip/TERASIC_CAMERA/Bayer2RGB.v | 294 +
.../ip/TERASIC_CAMERA/Bayer_LineBuffer.qip | 3 +
.../ip/TERASIC_CAMERA/Bayer_LineBuffer.v | 112 +
.../ip/TERASIC_CAMERA/CAMERA_Bayer.v | 121 +
.../ip/TERASIC_CAMERA/CAMERA_RGB.v | 95 +
.../ip/TERASIC_CAMERA/TERASIC_CAMERA.v | 198 +
.../ip/TERASIC_CAMERA/TERASIC_CAMERA_hw.tcl | 149 +
.../ip/TERASIC_CAMERA/add2.qip | 4 +
.../ip/TERASIC_CAMERA/add2.v | 103 +
.../ip/TERASIC_CAMERA/add2_bb.v | 71 +
.../ip/TERASIC_CAMERA/add4.qip | 4 +
.../ip/TERASIC_CAMERA/add4.v | 113 +
.../ip/TERASIC_CAMERA/add4_bb.v | 79 +
.../TERASIC_CAMERA/greybox_tmp/cbx_args.txt | 13 +
.../ip/TERASIC_CAMERA/rgb_fifo.qip | 3 +
.../ip/TERASIC_CAMERA/rgb_fifo.v | 178 +
.../ip/TERASIC_CAMERA/rgb_fifo_wave0.jpg | Bin 0 -> 108681 bytes
.../ip/TERASIC_CAMERA/rgb_fifo_wave1.jpg | Bin 0 -> 96651 bytes
.../ip/TERASIC_CAMERA/rgb_fifo_waveforms.html | 16 +
.../ip/i2c_opencores/Docs/I2C_tests.c | 99 +
.../ip/i2c_opencores/Docs/i2c_specs.pdf | Bin 0 -> 211471 bytes
.../ip/i2c_opencores/HAL/inc/i2c_opencores.h | 31 +
.../ip/i2c_opencores/HAL/src/component.mk | 38 +
.../ip/i2c_opencores/HAL/src/i2c_opencores.c | 183 +
.../ip/i2c_opencores/i2c_master_bit_ctrl.v | 540 +
.../ip/i2c_opencores/i2c_master_byte_ctrl.v | 344 +
.../ip/i2c_opencores/i2c_master_defines.v | 64 +
.../ip/i2c_opencores/i2c_master_top.v | 296 +
.../ip/i2c_opencores/i2c_opencores.v | 72 +
.../ip/i2c_opencores/i2c_opencores_hw.tcl | 143 +
.../ip/i2c_opencores/i2c_opencores_sw.tcl | 56 +
.../ip/i2c_opencores/inc/i2c_opencores_regs.h | 75 +
.../ip/i2c_opencores/test.v | 388 +
.../ip/i2c_opencores/timescale.v | 2 +
Vision/DE10_LITE_D8M_VIP_16/readme.pdf | Bin 0 -> 237588 bytes
.../software/D8M_Camera_Test/.cproject | 83 +
.../software/D8M_Camera_Test/.force_rebuild | 0
.../software/D8M_Camera_Test/.force_relink | 0
.../software/D8M_Camera_Test/.project | 40 +
.../.settings/language.settings.xml | 15 +
.../D8M_Camera_Test/D8M_Camera_Test.elf | Bin 0 -> 1128331 bytes
.../D8M_Camera_Test/D8M_Camera_Test.map | 2517 ++
.../D8M_Camera_Test/D8M_Camera_Test.objdump | 22618 ++++++++++++++++
.../software/D8M_Camera_Test/I2C_core.c | 732 +
.../software/D8M_Camera_Test/I2C_core.h | 29 +
.../software/D8M_Camera_Test/Makefile | 1083 +
.../software/D8M_Camera_Test/auto_focus.c | 98 +
.../software/D8M_Camera_Test/auto_focus.h | 30 +
.../software/D8M_Camera_Test/create-this-app | 114 +
.../software/D8M_Camera_Test/main.c | 301 +
.../D8M_Camera_Test/mipi_bridge_config.c | 132 +
.../D8M_Camera_Test/mipi_bridge_config.h | 18 +
.../D8M_Camera_Test/mipi_camera_config.c | 658 +
.../D8M_Camera_Test/mipi_camera_config.h | 30 +
.../software/D8M_Camera_Test/queue.c | 54 +
.../software/D8M_Camera_Test/queue.h | 21 +
.../software/D8M_Camera_Test/readme.txt | 26 +
.../D8M_Camera_Test/terasic_includes.h | 61 +
.../software/D8M_Camera_Test_bsp/.cproject | 56 +
.../D8M_Camera_Test_bsp/.force_rebuild_all | 0
.../D8M_Camera_Test_bsp/.force_relink | 0
.../software/D8M_Camera_Test_bsp/.project | 29 +
.../.settings/language.settings.xml | 15 +
.../D8M_Camera_Test_bsp/HAL/inc/alt_types.h | 54 +
.../HAL/inc/altera_nios2_gen2_irq.h | 80 +
.../software/D8M_Camera_Test_bsp/HAL/inc/io.h | 81 +
.../D8M_Camera_Test_bsp/HAL/inc/nios2.h | 300 +
.../D8M_Camera_Test_bsp/HAL/inc/os/alt_flag.h | 98 +
.../HAL/inc/os/alt_hooks.h | 61 +
.../D8M_Camera_Test_bsp/HAL/inc/os/alt_sem.h | 96 +
.../HAL/inc/os/alt_syscall.h | 75 +
.../HAL/inc/priv/alt_alarm.h | 101 +
.../HAL/inc/priv/alt_busy_sleep.h | 35 +
.../HAL/inc/priv/alt_dev_llist.h | 77 +
.../inc/priv/alt_exception_handler_registry.h | 39 +
.../HAL/inc/priv/alt_file.h | 179 +
.../HAL/inc/priv/alt_iic_isr_register.h | 39 +
.../HAL/inc/priv/alt_irq_table.h | 59 +
.../HAL/inc/priv/alt_legacy_irq.h | 158 +
.../HAL/inc/priv/alt_no_error.h | 77 +
.../HAL/inc/priv/nios2_gmon_data.h | 47 +
.../HAL/inc/sys/alt_alarm.h | 126 +
.../HAL/inc/sys/alt_cache.h | 117 +
.../HAL/inc/sys/alt_debug.h | 45 +
.../D8M_Camera_Test_bsp/HAL/inc/sys/alt_dev.h | 115 +
.../D8M_Camera_Test_bsp/HAL/inc/sys/alt_dma.h | 226 +
.../HAL/inc/sys/alt_dma_dev.h | 200 +
.../HAL/inc/sys/alt_driver.h | 168 +
.../HAL/inc/sys/alt_errno.h | 87 +
.../HAL/inc/sys/alt_exceptions.h | 166 +
.../HAL/inc/sys/alt_flash.h | 181 +
.../HAL/inc/sys/alt_flash_dev.h | 100 +
.../HAL/inc/sys/alt_flash_types.h | 64 +
.../D8M_Camera_Test_bsp/HAL/inc/sys/alt_irq.h | 245 +
.../HAL/inc/sys/alt_irq_entry.h | 39 +
.../HAL/inc/sys/alt_license_reminder_ucosii.h | 77 +
.../HAL/inc/sys/alt_llist.h | 123 +
.../HAL/inc/sys/alt_load.h | 78 +
.../HAL/inc/sys/alt_log_printf.h | 354 +
.../HAL/inc/sys/alt_set_args.h | 71 +
.../D8M_Camera_Test_bsp/HAL/inc/sys/alt_sim.h | 91 +
.../HAL/inc/sys/alt_stack.h | 126 +
.../HAL/inc/sys/alt_stdio.h | 66 +
.../HAL/inc/sys/alt_sys_init.h | 62 +
.../HAL/inc/sys/alt_sys_wrappers.h | 100 +
.../HAL/inc/sys/alt_timestamp.h | 60 +
.../HAL/inc/sys/alt_warning.h | 75 +
.../D8M_Camera_Test_bsp/HAL/inc/sys/ioctl.h | 90 +
.../D8M_Camera_Test_bsp/HAL/inc/sys/termios.h | 181 +
.../HAL/src/alt_alarm_start.c | 112 +
.../HAL/src/alt_busy_sleep.c | 133 +
.../D8M_Camera_Test_bsp/HAL/src/alt_close.c | 103 +
.../HAL/src/alt_dcache_flush.c | 70 +
.../HAL/src/alt_dcache_flush_all.c | 51 +
.../HAL/src/alt_dcache_flush_no_writeback.c | 69 +
.../D8M_Camera_Test_bsp/HAL/src/alt_dev.c | 149 +
.../HAL/src/alt_dev_llist_insert.c | 59 +
.../HAL/src/alt_dma_rxchan_open.c | 63 +
.../HAL/src/alt_dma_txchan_open.c | 63 +
.../HAL/src/alt_do_ctors.c | 64 +
.../HAL/src/alt_do_dtors.c | 64 +
.../HAL/src/alt_ecc_fatal_entry.S | 102 +
.../HAL/src/alt_ecc_fatal_exception.c | 75 +
.../HAL/src/alt_env_lock.c | 53 +
.../D8M_Camera_Test_bsp/HAL/src/alt_environ.c | 42 +
.../D8M_Camera_Test_bsp/HAL/src/alt_errno.c | 44 +
.../HAL/src/alt_exception_entry.S | 402 +
.../HAL/src/alt_exception_muldiv.S | 583 +
.../HAL/src/alt_exception_trap.S | 95 +
.../D8M_Camera_Test_bsp/HAL/src/alt_execve.c | 55 +
.../D8M_Camera_Test_bsp/HAL/src/alt_exit.c | 71 +
.../D8M_Camera_Test_bsp/HAL/src/alt_fcntl.c | 101 +
.../D8M_Camera_Test_bsp/HAL/src/alt_fd_lock.c | 75 +
.../HAL/src/alt_fd_unlock.c | 56 +
.../HAL/src/alt_find_dev.c | 88 +
.../HAL/src/alt_find_file.c | 89 +
.../HAL/src/alt_flash_dev.c | 69 +
.../D8M_Camera_Test_bsp/HAL/src/alt_fork.c | 57 +
.../D8M_Camera_Test_bsp/HAL/src/alt_fs_reg.c | 75 +
.../D8M_Camera_Test_bsp/HAL/src/alt_fstat.c | 128 +
.../D8M_Camera_Test_bsp/HAL/src/alt_get_fd.c | 105 +
.../D8M_Camera_Test_bsp/HAL/src/alt_getchar.c | 70 +
.../D8M_Camera_Test_bsp/HAL/src/alt_getpid.c | 47 +
.../D8M_Camera_Test_bsp/HAL/src/alt_gettod.c | 125 +
.../D8M_Camera_Test_bsp/HAL/src/alt_gmon.c | 272 +
.../HAL/src/alt_icache_flush.c | 84 +
.../HAL/src/alt_icache_flush_all.c | 46 +
.../D8M_Camera_Test_bsp/HAL/src/alt_iic.c | 106 +
.../HAL/src/alt_iic_isr_register.c | 104 +
.../HAL/src/alt_instruction_exception_entry.c | 206 +
.../src/alt_instruction_exception_register.c | 82 +
.../HAL/src/alt_io_redirect.c | 98 +
.../D8M_Camera_Test_bsp/HAL/src/alt_ioctl.c | 170 +
.../HAL/src/alt_irq_entry.S | 108 +
.../HAL/src/alt_irq_handler.c | 169 +
.../HAL/src/alt_irq_register.c | 102 +
.../HAL/src/alt_irq_vars.c | 47 +
.../D8M_Camera_Test_bsp/HAL/src/alt_isatty.c | 125 +
.../D8M_Camera_Test_bsp/HAL/src/alt_kill.c | 121 +
.../D8M_Camera_Test_bsp/HAL/src/alt_link.c | 56 +
.../D8M_Camera_Test_bsp/HAL/src/alt_load.c | 99 +
.../HAL/src/alt_log_macro.S | 60 +
.../HAL/src/alt_log_printf.c | 479 +
.../D8M_Camera_Test_bsp/HAL/src/alt_lseek.c | 117 +
.../D8M_Camera_Test_bsp/HAL/src/alt_main.c | 161 +
.../HAL/src/alt_malloc_lock.c | 52 +
.../D8M_Camera_Test_bsp/HAL/src/alt_mcount.S | 198 +
.../D8M_Camera_Test_bsp/HAL/src/alt_open.c | 173 +
.../D8M_Camera_Test_bsp/HAL/src/alt_printf.c | 132 +
.../D8M_Camera_Test_bsp/HAL/src/alt_putchar.c | 68 +
.../HAL/src/alt_putcharbuf.c | 80 +
.../D8M_Camera_Test_bsp/HAL/src/alt_putstr.c | 64 +
.../D8M_Camera_Test_bsp/HAL/src/alt_read.c | 125 +
.../HAL/src/alt_release_fd.c | 54 +
.../HAL/src/alt_remap_cached.c | 55 +
.../HAL/src/alt_remap_uncached.c | 54 +
.../D8M_Camera_Test_bsp/HAL/src/alt_rename.c | 55 +
.../D8M_Camera_Test_bsp/HAL/src/alt_sbrk.c | 136 +
.../D8M_Camera_Test_bsp/HAL/src/alt_settod.c | 96 +
.../HAL/src/alt_software_exception.S | 53 +
.../D8M_Camera_Test_bsp/HAL/src/alt_stat.c | 59 +
.../D8M_Camera_Test_bsp/HAL/src/alt_tick.c | 149 +
.../D8M_Camera_Test_bsp/HAL/src/alt_times.c | 71 +
.../HAL/src/alt_uncached_free.c | 53 +
.../HAL/src/alt_uncached_malloc.c | 77 +
.../D8M_Camera_Test_bsp/HAL/src/alt_unlink.c | 55 +
.../D8M_Camera_Test_bsp/HAL/src/alt_usleep.c | 52 +
.../D8M_Camera_Test_bsp/HAL/src/alt_wait.c | 52 +
.../D8M_Camera_Test_bsp/HAL/src/alt_write.c | 138 +
.../HAL/src/altera_nios2_gen2_irq.c | 37 +
.../D8M_Camera_Test_bsp/HAL/src/crt0.S | 521 +
.../software/D8M_Camera_Test_bsp/Makefile | 781 +
.../D8M_Camera_Test_bsp/alt_sys_init.c | 99 +
.../D8M_Camera_Test_bsp/create-this-bsp | 52 +
.../drivers/inc/altera_avalon_jtag_uart.h | 198 +
.../drivers/inc/altera_avalon_jtag_uart_fd.h | 125 +
.../inc/altera_avalon_jtag_uart_regs.h | 73 +
.../drivers/inc/altera_avalon_pio_regs.h | 67 +
.../drivers/inc/altera_avalon_sysid_qsys.h | 60 +
.../inc/altera_avalon_sysid_qsys_regs.h | 42 +
.../drivers/inc/altera_avalon_timer.h | 193 +
.../drivers/inc/altera_avalon_timer_regs.h | 202 +
.../drivers/src/altera_avalon_jtag_uart_fd.c | 86 +
.../src/altera_avalon_jtag_uart_init.c | 256 +
.../src/altera_avalon_jtag_uart_ioctl.c | 86 +
.../src/altera_avalon_jtag_uart_read.c | 205 +
.../src/altera_avalon_jtag_uart_write.c | 217 +
.../drivers/src/altera_avalon_sysid_qsys.c | 82 +
.../drivers/src/altera_avalon_timer_sc.c | 110 +
.../drivers/src/altera_avalon_timer_ts.c | 143 +
.../drivers/src/altera_avalon_timer_vars.c | 45 +
.../software/D8M_Camera_Test_bsp/linker.h | 101 +
.../software/D8M_Camera_Test_bsp/linker.x | 386 +
.../software/D8M_Camera_Test_bsp/mem_init.mk | 344 +
.../software/D8M_Camera_Test_bsp/memory.gdb | 50 +
.../software/D8M_Camera_Test_bsp/public.mk | 415 +
.../software/D8M_Camera_Test_bsp/settings.bsp | 1009 +
.../software/D8M_Camera_Test_bsp/summary.html | 2119 ++
.../software/D8M_Camera_Test_bsp/system.h | 496 +
.../software/RemoteSystemsTempFiles/.project | 12 +
Vision/README.md | 14 +
Vision/doc/FPGA-installation.md | 100 +
Vision/doc/FPGA-system.md | 72 +
270 files changed, 99350 insertions(+)
create mode 100644 Vision/.gitignore
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/filters.xml
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Chain.cdf
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.SDC
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.htm
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qpf
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qsf
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP_assignment_defaults.qdf
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/FpsMonitor.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/demo_batch/D8M_Camera_Test.elf
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/demo_batch/DE10_LITE_D8M_VIP.sof
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/demo_batch/test.bat
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/demo_batch/test.sh
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/greybox_tmp/cbx_args.txt
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/hs_err_pid13062.log
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO.qip
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO_bb.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/MSG_FIFO_inst.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG_TEST.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/STREAM_REG_TEST.vwf
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/greybox_tmp/cbx_args.txt
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/F_VCM.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/I2C_VCM_Config.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/I2C_VCM_Controller.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/TERASIC_AUTO_FOCUS.v
create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/TERASIC_AUTO_FOCUS_hw.tcl
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+
+
+
+
+ 6
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+
+
+ Instrumentation - Beta
+
+
+
+
+
+
+
+
+
+ dock.single.Block\ Symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Block Symbol
+
+
+
+
+
+
+
+
+
+ dock.single.Reset\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+ 1
+ dock.single.Reset\ Domains\ \-\ Beta
+
+
+
+
+
+
+ Reset Domains - Beta
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Details
+
+
+
+
+
+
+
+
+
+ 1
+ dock.single.Details
+
+
+
+
+
+
+
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.minimized
+ ccontrol west
+
+
+ 0
+ false
+ 400
+ dock.single.Parameters
+
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Parameters
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Assignments
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Address\ Map
+
+
+
+
+
+
+
+
+
+
+ 1
+ dock.single.Address\ Map
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Schematic
+
+
+
+
+
+
+
+
+
+
+ 4
+ dock.single.Schematic
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Presets
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Messages
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Device\ Family
+
+
+
+
+
+
+
+
+
+
+
+ 4
+ dock.single.Device\ Family
+
+
+
+
+
+
+
+ dock.mode.maximized
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.maximized
+ ccontrol center
+
+
+
+ 0
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+ dock.mode.minimized
+ ccontrol north
+
+
+ 0
+ false
+ 400
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+ 0
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+ 2
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Generation\ Messages
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Connections
+
+
+
+
+
+
+
+
+
+ 5
+ dock.single.Connections
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.System\ Contents
+
+
+
+
+
+
+
+
+
+
+ 0
+ dock.single.System\ Contents
+
+
+
+
+
+
+
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.minimized
+ ccontrol north
+
+
+ 0
+ false
+ 400
+ dock.single.Interconnect\ Requirements
+
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Interconnect\ Requirements
+
+
+
+
+
+
+
+
+
+ 2
+ dock.single.Interconnect\ Requirements
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+
+
+
+
+
+
+ 4
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Instance\ Parameters
+
+
+
+
+
+
+
+
+
+
+ 4
+ dock.single.Instance\ Parameters
+
+
+
+
+
+
+
+ dock.mode.maximized
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.maximized
+ ccontrol center
+
+
+
+ 0
+ dock.single.IP\ Catalog
+
+
+
+
+ dock.mode.minimized
+ ccontrol north
+
+
+ 0
+ false
+ 400
+ dock.single.IP\ Catalog
+
+
+ 0
+ dock.single.IP\ Catalog
+
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.IP\ Catalog
+
+
+
+
+
+
+
+ 0
+ dock.single.IP\ Catalog
+
+
+
+
+
+
+
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.minimized
+ ccontrol north
+
+
+ 0
+ false
+ 400
+ dock.single.Hierarchy
+
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Hierarchy
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Block\ Symbol
+
+
+
+
+
+
+
+
+
+ 1
+ dock.single.Block\ Symbol
+
+
+
+
+
+
+
+ dock.mode.maximized
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.maximized
+ ccontrol center
+
+
+
+ 1
+ dock.single.Reset\ Domains\ \-\ Beta
+
+
+
+
+ dock.mode.minimized
+ ccontrol north
+
+
+ 0
+ false
+ 400
+ dock.single.Reset\ Domains\ \-\ Beta
+
+
+ 1
+ dock.single.Reset\ Domains\ \-\ Beta
+
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Reset\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+ 1
+ dock.single.Reset\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+
+
+ -
+ dock.mode.normal
+
+ dock.mode.normal
+ ccontrol center
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv
new file mode 100644
index 0000000..8cf3162
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv
@@ -0,0 +1,54 @@
+# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35
+#
+preplace inst Qsys.nios2_gen2.clock_bridge -pg 1
+preplace inst Qsys.altpll_0 -pg 1 -lvl 3 -y 250
+preplace inst Qsys.i2c_opencores_camera -pg 1 -lvl 7 -y 30
+preplace inst Qsys.alt_vip_itc_0 -pg 1 -lvl 7 -y 810
+preplace inst Qsys.onchip_memory2_0 -pg 1 -lvl 7 -y 540
+preplace inst Qsys.led -pg 1 -lvl 7 -y 1390
+preplace inst Qsys.clk_50 -pg 1 -lvl 1 -y 720
+preplace inst Qsys.sysid_qsys -pg 1 -lvl 7 -y 1010
+preplace inst Qsys.sdram -pg 1 -lvl 7 -y 910
+preplace inst Qsys.nios2_gen2.reset_bridge -pg 1
+preplace inst Qsys.jtag_uart -pg 1 -lvl 7 -y 330
+preplace inst Qsys.TERASIC_CAMERA_0 -pg 1 -lvl 4 -y 740
+preplace inst Qsys.mipi_reset_n -pg 1 -lvl 7 -y 1190
+preplace inst Qsys.alt_vip_vfb_0 -pg 1 -lvl 5 -y 620
+preplace inst Qsys -pg 1 -lvl 1 -y 40 -regy -20
+preplace inst Qsys.timer -pg 1 -lvl 7 -y 440
+preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 7 -y 1090
+preplace inst Qsys.key -pg 1 -lvl 7 -y 620
+preplace inst Qsys.sw -pg 1 -lvl 7 -y 1290
+preplace inst Qsys.TERASIC_AUTO_FOCUS_0 -pg 1 -lvl 6 -y 560
+preplace inst Qsys.nios2_gen2.cpu -pg 1
+preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 470
+preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 7 -y 170
+preplace netloc INTERCONNECTQsys(SLAVE)sdram.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)led.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)mipi_pwdn_n.reset,(MASTER)clk_50.clk_reset,(SLAVE)mipi_reset_n.reset,(SLAVE)sysid_qsys.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)sw.reset,(SLAVE)key.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)nios2_gen2.reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)jtag_uart.reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(SLAVE)timer.reset) 1 1 6 430 670 870 530 1170 730 1650 730 1890 800 2230
+preplace netloc POINT_TO_POINTQsys(SLAVE)alt_vip_itc_0.din,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 2190
+preplace netloc EXPORTQsys(SLAVE)clk_50.clk_in_reset,(SLAVE)Qsys.reset) 1 0 1 NJ
+preplace netloc EXPORTQsys(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 7 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ
+preplace netloc EXPORTQsys(SLAVE)sdram.wire,(SLAVE)Qsys.sdram_wire) 1 0 7 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ
+preplace netloc EXPORTQsys(SLAVE)led.external_connection,(SLAVE)Qsys.led_external_connection) 1 0 7 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ
+preplace netloc EXPORTQsys(MASTER)Qsys.clk_sdram,(MASTER)altpll_0.c1) 1 3 5 NJ 210 NJ 210 NJ 210 NJ 160 NJ
+preplace netloc EXPORTQsys(SLAVE)Qsys.altpll_0_locked_conduit,(SLAVE)altpll_0.locked_conduit) 1 0 3 NJ 410 NJ 410 NJ
+preplace netloc EXPORTQsys(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit,(SLAVE)Qsys.terasic_auto_focus_0_conduit) 1 0 6 NJ 630 NJ 630 NJ 570 NJ 570 NJ 570 NJ
+preplace netloc EXPORTQsys(SLAVE)altpll_0.areset_conduit,(SLAVE)Qsys.altpll_0_areset_conduit) 1 0 3 NJ 260 NJ 260 NJ
+preplace netloc EXPORTQsys(SLAVE)mipi_reset_n.external_connection,(SLAVE)Qsys.mipi_reset_n_external_connection) 1 0 7 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ
+preplace netloc EXPORTQsys(SLAVE)Qsys.sw_external_connection,(SLAVE)sw.external_connection) 1 0 7 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ
+preplace netloc EXPORTQsys(SLAVE)Qsys.mipi_pwdn_n_external_connection,(SLAVE)mipi_pwdn_n.external_connection) 1 0 7 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ
+preplace netloc EXPORTQsys(MASTER)Qsys.clk_vga,(MASTER)altpll_0.c3) 1 3 5 NJ 360 NJ 360 NJ 360 NJ 320 NJ
+preplace netloc EXPORTQsys(SLAVE)key.external_connection,(SLAVE)Qsys.key_external_connection) 1 0 7 NJ 650 NJ 650 NJ 650 NJ 650 NJ 750 NJ 750 NJ
+preplace netloc EXPORTQsys(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 7 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ
+preplace netloc EXPORTQsys(SLAVE)Qsys.alt_vip_itc_0_clocked_video,(SLAVE)alt_vip_itc_0.clocked_video) 1 0 7 NJ 830 NJ 830 NJ 830 NJ 830 NJ 820 NJ 820 NJ
+preplace netloc FAN_OUTQsys(SLAVE)sdram.clk,(SLAVE)alt_vip_itc_0.is_clk_rst,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)alt_vip_vfb_0.clock,(SLAVE)TERASIC_CAMERA_0.clock_reset,(MASTER)altpll_0.c2) 1 3 4 1190 340 1630 710 1870 780 2150
+preplace netloc POINT_TO_POINTQsys(SLAVE)TERASIC_AUTO_FOCUS_0.din,(MASTER)alt_vip_vfb_0.dout) 1 5 1 1830
+preplace netloc EXPORTQsys(SLAVE)clk_50.clk_in,(SLAVE)Qsys.clk) 1 0 1 NJ
+preplace netloc FAN_INQsys(MASTER)alt_vip_vfb_0.read_master,(MASTER)alt_vip_vfb_0.write_master,(SLAVE)sdram.s1) 1 5 2 1830 960 NJ
+preplace netloc FAN_OUTQsys(SLAVE)jtag_uart.irq,(SLAVE)timer.irq,(MASTER)nios2_gen2.irq,(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)i2c_opencores_camera.interrupt_sender) 1 2 5 NJ 550 NJ 550 NJ 550 NJ 550 2170
+preplace netloc POINT_TO_POINTQsys(MASTER)TERASIC_CAMERA_0.avalon_streaming_source,(SLAVE)alt_vip_vfb_0.din) 1 4 1 1610
+preplace netloc EXPORTQsys(MASTER)Qsys.d8m_xclkin,(MASTER)altpll_0.c4) 1 3 5 NJ 380 NJ 380 NJ 380 NJ 300 NJ
+preplace netloc FAN_OUTQsys(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_camera.clock,(SLAVE)led.clk,(SLAVE)onchip_memory2_0.clk1,(SLAVE)timer.clk,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)sw.clk,(SLAVE)sysid_qsys.clk,(SLAVE)mipi_pwdn_n.clk,(SLAVE)nios2_gen2.clk,(SLAVE)jtag_uart.clk,(MASTER)clk_50.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)key.clk) 1 1 6 410 430 850 400 NJ 400 NJ 400 NJ 400 2210
+preplace netloc INTERCONNECTQsys(SLAVE)altpll_0.pll_slave,(SLAVE)led.s1,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)i2c_opencores_mipi.avalon_slave_0,(SLAVE)mipi_reset_n.s1,(MASTER)nios2_gen2.data_master,(SLAVE)sysid_qsys.control_slave,(SLAVE)timer.s1,(SLAVE)sw.s1,(SLAVE)onchip_memory2_0.s1,(SLAVE)key.s1,(SLAVE)mipi_pwdn_n.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(MASTER)nios2_gen2.instruction_master,(SLAVE)nios2_gen2.debug_mem_slave) 1 1 6 450 610 890 510 NJ 510 NJ 510 1850 690 2130
+preplace netloc EXPORTQsys(SLAVE)Qsys.terasic_camera_0_conduit_end,(SLAVE)TERASIC_CAMERA_0.conduit_end) 1 0 4 NJ 790 NJ 790 NJ 790 NJ
+levelinfo -pg 1 0 200 2570
+levelinfo -hier Qsys 210 240 590 980 1300 1680 1980 2320 2470
diff --git a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/filters.xml b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/filters.xml
new file mode 100644
index 0000000..5ca182d
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml
new file mode 100644
index 0000000..d057998
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml
@@ -0,0 +1,14 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Chain.cdf b/Vision/DE10_LITE_D8M_VIP_16/Chain.cdf
new file mode 100644
index 0000000..f7a1881
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Chain.cdf
@@ -0,0 +1,13 @@
+/* Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Cfg)
+ Device PartName(10M50DAF484) Path("F:/Ed/Stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/output_files/") File("DE10_LITE_D8M_VIP_time_limited.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(JTAG);
+AlteraEnd;
diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.SDC b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.SDC
new file mode 100644
index 0000000..cc5b110
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.SDC
@@ -0,0 +1,128 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+
+
+#SDRAM CLK
+create_generated_clock -source [get_pins { u0|altpll_0|sd1|pll7|clk[1] }] \
+ -name clk_dram_ext [get_ports {DRAM_CLK}]
+#VGA CLK
+#create_generated_clock -source [get_pins { u0|pll_sys|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk }] \
+ -name clk_vga_ext [get_ports {VGA_CLK}] -invert
+#D8M
+create_clock -period "25.0 MHz" -name MIPI_PIXEL_CLK [get_ports MIPI_PIXEL_CLK]
+create_clock -period "25.0 MHz" -name MIPI_PIXEL_CLK_ext
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+# tpd min 1ns ,max 6ns
+set_input_delay -max 6.0 -clock MIPI_PIXEL_CLK_ext [get_ports {MIPI_PIXEL_VS MIPI_PIXEL_HS MIPI_PIXEL_D[*]}]
+set_input_delay -min 1.0 -clock MIPI_PIXEL_CLK_ext [get_ports {MIPI_PIXEL_VS MIPI_PIXEL_HS MIPI_PIXEL_D[*]}]
+
+# SDRAM
+# max 5.4(max) +0.4(trace delay) +0.1 = 5.9
+# min 2.7(min) +0.4(trace delay) -0.1 = 3.0
+set_input_delay -max -clock clk_dram_ext 5.9 [get_ports DRAM_DQ*]
+set_input_delay -min -clock clk_dram_ext 3.0 [get_ports DRAM_DQ*]
+#shift-window
+set_multicycle_path -from [get_clocks {clk_dram_ext}] \
+ -to [get_clocks { u0|altpll_0|sd1|pll7|clk[2] }] \
+ -setup 2
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+# suppose +- 100 ps skew
+# max : Board Delay (Data) - Board Delay (Clock) + tsu (External Device)
+# min : Board Delay (Data) - Board Delay (Clock) - th (External Device)
+
+#SDRAM
+# max 1.5+0.1 = 1.6
+# min -0.8-0.1 = -0.9
+set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_DQ* DRAM_*DQM}]
+set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_DQ* DRAM_*DQM}]
+set_output_delay -max -clock clk_dram_ext 1.6 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]
+set_output_delay -min -clock clk_dram_ext -0.9 [get_ports {DRAM_ADDR* DRAM_BA* DRAM_RAS_N DRAM_CAS_N DRAM_WE_N DRAM_CKE DRAM_CS_N}]
+
+#VGA
+# max 0.2+0.1 = 0.3
+# min -1.5-0.1 = -1.6
+set_output_delay -max -clock clk_vga_ext 0.3 [get_ports {VGA_R* VGA_G* VGA_B* VGA_HS VGA_VS}]
+set_output_delay -min -clock clk_vga_ext -1.6 [get_ports {VGA_R* VGA_G* VGA_B* VGA_HS VGA_VS}]
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+set_clock_groups -asynchronous -group [get_clocks { u0|altpll_0|sd1|pll7|clk[2] }] \
+ -group [get_clocks {MIPI_PIXEL_CLK}]
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+set_false_path -from [get_ports {KEY* SW*}] -to *
+set_false_path -from * -to [get_ports {LED* HEX*}]
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.htm b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.htm
new file mode 100644
index 0000000..b8e6933
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.htm
@@ -0,0 +1,1193 @@
+
+
+DE10-Lite Kit Configuration
+
+
+Pin Assignments:
+
+
+
+
+Pin Assignment Table:
+
+CLOCK
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ ADC_CLK_10 |
+ N5 |
+ input |
+ 3.3-V LVTTL |
+
+
+ MAX10_CLK1_50 |
+ P11 |
+ input |
+ 3.3-V LVTTL |
+
+
+ MAX10_CLK2_50 |
+ N14 |
+ input |
+ 3.3-V LVTTL |
+
+
+
+SDRAM
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ DRAM_ADDR[0] |
+ U17 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[1] |
+ W19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[2] |
+ V18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[3] |
+ U18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[4] |
+ U19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[5] |
+ T18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[6] |
+ T19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[7] |
+ R18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[8] |
+ P18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[9] |
+ P19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[10] |
+ T20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[11] |
+ P20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_ADDR[12] |
+ R20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_BA[0] |
+ T21 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_BA[1] |
+ T22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_CAS_N |
+ U21 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_CKE |
+ N22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_CLK |
+ L14 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_CS_N |
+ U20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[0] |
+ Y21 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[1] |
+ Y20 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[2] |
+ AA22 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[3] |
+ AA21 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[4] |
+ Y22 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[5] |
+ W22 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[6] |
+ W20 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[7] |
+ V21 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[8] |
+ P21 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[9] |
+ J22 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[10] |
+ H21 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[11] |
+ H22 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[12] |
+ G22 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[13] |
+ G20 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[14] |
+ G19 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_DQ[15] |
+ F22 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ DRAM_LDQM |
+ V22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_RAS_N |
+ U22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_UDQM |
+ J21 |
+ output |
+ 3.3-V LVTTL |
+
+
+ DRAM_WE_N |
+ V20 |
+ output |
+ 3.3-V LVTTL |
+
+
+
+SEG7
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ HEX0[0] |
+ C14 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX0[1] |
+ E15 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX0[2] |
+ C15 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX0[3] |
+ C16 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX0[4] |
+ E16 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX0[5] |
+ D17 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX0[6] |
+ C17 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX0[7] |
+ D15 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[0] |
+ C18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[1] |
+ D18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[2] |
+ E18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[3] |
+ B16 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[4] |
+ A17 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[5] |
+ A18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[6] |
+ B17 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX1[7] |
+ A16 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[0] |
+ B20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[1] |
+ A20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[2] |
+ B19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[3] |
+ A21 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[4] |
+ B21 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[5] |
+ C22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[6] |
+ B22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX2[7] |
+ A19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[0] |
+ F21 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[1] |
+ E22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[2] |
+ E21 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[3] |
+ C19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[4] |
+ C20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[5] |
+ D19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[6] |
+ E17 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX3[7] |
+ D22 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[0] |
+ F18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[1] |
+ E20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[2] |
+ E19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[3] |
+ J18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[4] |
+ H19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[5] |
+ F19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[6] |
+ F20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX4[7] |
+ F17 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[0] |
+ J20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[1] |
+ K20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[2] |
+ L18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[3] |
+ N18 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[4] |
+ M20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[5] |
+ N19 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[6] |
+ N20 |
+ output |
+ 3.3-V LVTTL |
+
+
+ HEX5[7] |
+ L19 |
+ output |
+ 3.3-V LVTTL |
+
+
+
+KEY
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ KEY[0] |
+ B8 |
+ input |
+ 3.3 V Schmitt Trigger |
+
+
+ KEY[1] |
+ A7 |
+ input |
+ 3.3 V Schmitt Trigger |
+
+
+
+LED
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ LEDR[0] |
+ A8 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[1] |
+ A9 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[2] |
+ A10 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[3] |
+ B10 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[4] |
+ D13 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[5] |
+ C13 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[6] |
+ E14 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[7] |
+ D14 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[8] |
+ A11 |
+ output |
+ 3.3-V LVTTL |
+
+
+ LEDR[9] |
+ B11 |
+ output |
+ 3.3-V LVTTL |
+
+
+
+SW
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ SW[0] |
+ C10 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[1] |
+ C11 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[2] |
+ D12 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[3] |
+ C12 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[4] |
+ A12 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[5] |
+ B12 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[6] |
+ A13 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[7] |
+ A14 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[8] |
+ B14 |
+ input |
+ 3.3-V LVTTL |
+
+
+ SW[9] |
+ F15 |
+ input |
+ 3.3-V LVTTL |
+
+
+
+VGA
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ VGA_B[0] |
+ P1 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_B[1] |
+ T1 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_B[2] |
+ P4 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_B[3] |
+ N2 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_G[0] |
+ W1 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_G[1] |
+ T2 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_G[2] |
+ R2 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_G[3] |
+ R1 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_HS |
+ N3 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_R[0] |
+ AA1 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_R[1] |
+ V1 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_R[2] |
+ Y2 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_R[3] |
+ Y1 |
+ output |
+ 3.3-V LVTTL |
+
+
+ VGA_VS |
+ N1 |
+ output |
+ 3.3-V LVTTL |
+
+
+
+Accelerometer
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ GSENSOR_CS_N |
+ AB16 |
+ output |
+ 3.3-V LVTTL |
+
+
+ GSENSOR_INT[1] |
+ Y14 |
+ input |
+ 3.3-V LVTTL |
+
+
+ GSENSOR_INT[2] |
+ Y13 |
+ input |
+ 3.3-V LVTTL |
+
+
+ GSENSOR_SCLK |
+ AB15 |
+ output |
+ 3.3-V LVTTL |
+
+
+ GSENSOR_SDI |
+ V11 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ GSENSOR_SDO |
+ V12 |
+ inout |
+ 3.3-V LVTTL |
+
+
+
+Arduino
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+
+
+ ARDUINO_IO[0] |
+ AB5 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[1] |
+ AB6 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[2] |
+ AB7 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[3] |
+ AB8 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[4] |
+ AB9 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[5] |
+ Y10 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[6] |
+ AA11 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[7] |
+ AA12 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[8] |
+ AB17 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[9] |
+ AA17 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[10] |
+ AB19 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[11] |
+ AA19 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[12] |
+ Y19 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[13] |
+ AB20 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[14] |
+ AB21 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_IO[15] |
+ AA20 |
+ inout |
+ 3.3-V LVTTL |
+
+
+ ARDUINO_RESET_N |
+ F16 |
+ inout |
+ 3.3-V LVTTL |
+
+
+
+GPIO connect to D8M-GPIO
+
+
+
+ Name |
+ Location |
+ Direction |
+ Standard |
+ GPIO Pin Index |
+
+
+ CAMERA_I2C_SCL |
+ AA7 |
+ inout |
+ 3.3-V LVTTL |
+ 31 |
+
+
+ CAMERA_I2C_SDA |
+ Y6 |
+ inout |
+ 3.3-V LVTTL |
+ 32 |
+
+
+ CAMERA_PWDN_n |
+ Y7 |
+ output |
+ 3.3-V LVTTL |
+ 28 |
+
+
+ MIPI_CS_n |
+ Y8 |
+ output |
+ 3.3-V LVTTL |
+ 26 |
+
+
+ MIPI_I2C_SCL |
+ AA5 |
+ inout |
+ 3.3-V LVTTL |
+ 35 |
+
+
+ MIPI_I2C_SDA |
+ Y4 |
+ inout |
+ 3.3-V LVTTL |
+ 36 |
+
+
+ MIPI_MCLK |
+ AA6 |
+ output |
+ 3.3-V LVTTL |
+ 33 |
+
+
+ MIPI_PIXEL_CLK |
+ V10 |
+ input |
+ 3.3-V LVTTL |
+ 1 |
+
+
+ MIPI_PIXEL_D[0] |
+ W9 |
+ input |
+ 3.3-V LVTTL |
+ 4 |
+
+
+ MIPI_PIXEL_D[1] |
+ V8 |
+ input |
+ 3.3-V LVTTL |
+ 5 |
+
+
+ MIPI_PIXEL_D[2] |
+ W8 |
+ input |
+ 3.3-V LVTTL |
+ 6 |
+
+
+ MIPI_PIXEL_D[3] |
+ V7 |
+ input |
+ 3.3-V LVTTL |
+ 7 |
+
+
+ MIPI_PIXEL_D[4] |
+ W7 |
+ input |
+ 3.3-V LVTTL |
+ 8 |
+
+
+ MIPI_PIXEL_D[5] |
+ W6 |
+ input |
+ 3.3-V LVTTL |
+ 9 |
+
+
+ MIPI_PIXEL_D[6] |
+ V5 |
+ input |
+ 3.3-V LVTTL |
+ 10 |
+
+
+ MIPI_PIXEL_D[7] |
+ W5 |
+ input |
+ 3.3-V LVTTL |
+ 13 |
+
+
+ MIPI_PIXEL_D[8] |
+ AA15 |
+ input |
+ 3.3-V LVTTL |
+ 14 |
+
+
+ MIPI_PIXEL_D[9] |
+ AA14 |
+ input |
+ 3.3-V LVTTL |
+ 15 |
+
+
+ MIPI_PIXEL_HS |
+ AA9 |
+ input |
+ 3.3-V LVTTL |
+ 25 |
+
+
+ MIPI_PIXEL_VS |
+ AB10 |
+ input |
+ 3.3-V LVTTL |
+ 23 |
+
+
+ MIPI_REFCLK |
+ AB11 |
+ output |
+ 3.3-V LVTTL |
+ 21 |
+
+
+ MIPI_RESET_n |
+ AA8 |
+ output |
+ 3.3-V LVTTL |
+ 27 |
+
+
+
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qpf b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qpf
new file mode 100644
index 0000000..f8d6c57
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qpf
@@ -0,0 +1,6 @@
+DATE = "15:21:37 August 23, 2016"
+QUARTUS_VERSION = "15.1.0"
+
+# Revisions
+
+PROJECT_REVISION = "DE10_LITE_D8M_VIP"
diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qsf b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qsf
new file mode 100644
index 0000000..f5e15d6
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qsf
@@ -0,0 +1,426 @@
+#============================================================
+# Build by Terasic System Builder
+#============================================================
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name TOP_LEVEL_ENTITY DE10_LITE_D8M_VIP
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
+set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:21:37 AUGUST 23,2016"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+#set_global_assignment -name ENABLE_ERAM_PRELOAD ON
+
+#============================================================
+# CLOCK
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
+set_location_assignment PIN_N5 -to ADC_CLK_10
+set_location_assignment PIN_P11 -to MAX10_CLK1_50
+set_location_assignment PIN_N14 -to MAX10_CLK2_50
+
+#============================================================
+# SDRAM
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_location_assignment PIN_U17 -to DRAM_ADDR[0]
+set_location_assignment PIN_W19 -to DRAM_ADDR[1]
+set_location_assignment PIN_V18 -to DRAM_ADDR[2]
+set_location_assignment PIN_U18 -to DRAM_ADDR[3]
+set_location_assignment PIN_U19 -to DRAM_ADDR[4]
+set_location_assignment PIN_T18 -to DRAM_ADDR[5]
+set_location_assignment PIN_T19 -to DRAM_ADDR[6]
+set_location_assignment PIN_R18 -to DRAM_ADDR[7]
+set_location_assignment PIN_P18 -to DRAM_ADDR[8]
+set_location_assignment PIN_P19 -to DRAM_ADDR[9]
+set_location_assignment PIN_T20 -to DRAM_ADDR[10]
+set_location_assignment PIN_P20 -to DRAM_ADDR[11]
+set_location_assignment PIN_R20 -to DRAM_ADDR[12]
+set_location_assignment PIN_T21 -to DRAM_BA[0]
+set_location_assignment PIN_T22 -to DRAM_BA[1]
+set_location_assignment PIN_U21 -to DRAM_CAS_N
+set_location_assignment PIN_N22 -to DRAM_CKE
+set_location_assignment PIN_L14 -to DRAM_CLK
+set_location_assignment PIN_U20 -to DRAM_CS_N
+set_location_assignment PIN_Y21 -to DRAM_DQ[0]
+set_location_assignment PIN_Y20 -to DRAM_DQ[1]
+set_location_assignment PIN_AA22 -to DRAM_DQ[2]
+set_location_assignment PIN_AA21 -to DRAM_DQ[3]
+set_location_assignment PIN_Y22 -to DRAM_DQ[4]
+set_location_assignment PIN_W22 -to DRAM_DQ[5]
+set_location_assignment PIN_W20 -to DRAM_DQ[6]
+set_location_assignment PIN_V21 -to DRAM_DQ[7]
+set_location_assignment PIN_P21 -to DRAM_DQ[8]
+set_location_assignment PIN_J22 -to DRAM_DQ[9]
+set_location_assignment PIN_H21 -to DRAM_DQ[10]
+set_location_assignment PIN_H22 -to DRAM_DQ[11]
+set_location_assignment PIN_G22 -to DRAM_DQ[12]
+set_location_assignment PIN_G20 -to DRAM_DQ[13]
+set_location_assignment PIN_G19 -to DRAM_DQ[14]
+set_location_assignment PIN_F22 -to DRAM_DQ[15]
+set_location_assignment PIN_V22 -to DRAM_LDQM
+set_location_assignment PIN_U22 -to DRAM_RAS_N
+set_location_assignment PIN_J21 -to DRAM_UDQM
+set_location_assignment PIN_V20 -to DRAM_WE_N
+
+#============================================================
+# SEG7
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+set_location_assignment PIN_B20 -to HEX2[0]
+set_location_assignment PIN_A20 -to HEX2[1]
+set_location_assignment PIN_B19 -to HEX2[2]
+set_location_assignment PIN_A21 -to HEX2[3]
+set_location_assignment PIN_B21 -to HEX2[4]
+set_location_assignment PIN_C22 -to HEX2[5]
+set_location_assignment PIN_B22 -to HEX2[6]
+set_location_assignment PIN_A19 -to HEX2[7]
+set_location_assignment PIN_F21 -to HEX3[0]
+set_location_assignment PIN_E22 -to HEX3[1]
+set_location_assignment PIN_E21 -to HEX3[2]
+set_location_assignment PIN_C19 -to HEX3[3]
+set_location_assignment PIN_C20 -to HEX3[4]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_E17 -to HEX3[6]
+set_location_assignment PIN_D22 -to HEX3[7]
+set_location_assignment PIN_F18 -to HEX4[0]
+set_location_assignment PIN_E20 -to HEX4[1]
+set_location_assignment PIN_E19 -to HEX4[2]
+set_location_assignment PIN_J18 -to HEX4[3]
+set_location_assignment PIN_H19 -to HEX4[4]
+set_location_assignment PIN_F19 -to HEX4[5]
+set_location_assignment PIN_F20 -to HEX4[6]
+set_location_assignment PIN_F17 -to HEX4[7]
+set_location_assignment PIN_J20 -to HEX5[0]
+set_location_assignment PIN_K20 -to HEX5[1]
+set_location_assignment PIN_L18 -to HEX5[2]
+set_location_assignment PIN_N18 -to HEX5[3]
+set_location_assignment PIN_M20 -to HEX5[4]
+set_location_assignment PIN_N19 -to HEX5[5]
+set_location_assignment PIN_N20 -to HEX5[6]
+set_location_assignment PIN_L19 -to HEX5[7]
+
+#============================================================
+# KEY
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
+set_location_assignment PIN_B8 -to KEY[0]
+set_location_assignment PIN_A7 -to KEY[1]
+
+#============================================================
+# LED
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_location_assignment PIN_A8 -to LEDR[0]
+set_location_assignment PIN_A9 -to LEDR[1]
+set_location_assignment PIN_A10 -to LEDR[2]
+set_location_assignment PIN_B10 -to LEDR[3]
+set_location_assignment PIN_D13 -to LEDR[4]
+set_location_assignment PIN_C13 -to LEDR[5]
+set_location_assignment PIN_E14 -to LEDR[6]
+set_location_assignment PIN_D14 -to LEDR[7]
+set_location_assignment PIN_A11 -to LEDR[8]
+set_location_assignment PIN_B11 -to LEDR[9]
+
+#============================================================
+# SW
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+
+#============================================================
+# VGA
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_location_assignment PIN_P1 -to VGA_B[0]
+set_location_assignment PIN_T1 -to VGA_B[1]
+set_location_assignment PIN_P4 -to VGA_B[2]
+set_location_assignment PIN_N2 -to VGA_B[3]
+set_location_assignment PIN_W1 -to VGA_G[0]
+set_location_assignment PIN_T2 -to VGA_G[1]
+set_location_assignment PIN_R2 -to VGA_G[2]
+set_location_assignment PIN_R1 -to VGA_G[3]
+set_location_assignment PIN_N3 -to VGA_HS
+set_location_assignment PIN_AA1 -to VGA_R[0]
+set_location_assignment PIN_V1 -to VGA_R[1]
+set_location_assignment PIN_Y2 -to VGA_R[2]
+set_location_assignment PIN_Y1 -to VGA_R[3]
+set_location_assignment PIN_N1 -to VGA_VS
+
+#============================================================
+# Accelerometer
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO
+set_location_assignment PIN_AB16 -to GSENSOR_CS_N
+set_location_assignment PIN_Y14 -to GSENSOR_INT[1]
+set_location_assignment PIN_Y13 -to GSENSOR_INT[2]
+set_location_assignment PIN_AB15 -to GSENSOR_SCLK
+set_location_assignment PIN_V11 -to GSENSOR_SDI
+set_location_assignment PIN_V12 -to GSENSOR_SDO
+
+#============================================================
+# Arduino
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
+set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
+set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
+set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
+set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
+set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
+set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
+set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
+set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
+set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
+set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
+set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
+set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
+set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
+set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
+set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
+set_location_assignment PIN_F16 -to ARDUINO_RESET_N
+
+#============================================================
+# GPIO, GPIO connect to D8M-GPIO
+#============================================================
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAMERA_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAMERA_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CAMERA_PWDN_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_I2C_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_I2C_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_MCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_D[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_PIXEL_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_REFCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MIPI_RESET_n
+set_location_assignment PIN_AA7 -to CAMERA_I2C_SCL
+set_location_assignment PIN_Y6 -to CAMERA_I2C_SDA
+set_location_assignment PIN_Y7 -to CAMERA_PWDN_n
+set_location_assignment PIN_Y8 -to MIPI_CS_n
+set_location_assignment PIN_AA5 -to MIPI_I2C_SCL
+set_location_assignment PIN_Y4 -to MIPI_I2C_SDA
+set_location_assignment PIN_AA6 -to MIPI_MCLK
+set_location_assignment PIN_W10 -to MIPI_PIXEL_CLK
+set_location_assignment PIN_W9 -to MIPI_PIXEL_D[0]
+set_location_assignment PIN_V8 -to MIPI_PIXEL_D[1]
+set_location_assignment PIN_W8 -to MIPI_PIXEL_D[2]
+set_location_assignment PIN_V7 -to MIPI_PIXEL_D[3]
+set_location_assignment PIN_W7 -to MIPI_PIXEL_D[4]
+set_location_assignment PIN_W6 -to MIPI_PIXEL_D[5]
+set_location_assignment PIN_V5 -to MIPI_PIXEL_D[6]
+set_location_assignment PIN_W5 -to MIPI_PIXEL_D[7]
+set_location_assignment PIN_AA15 -to MIPI_PIXEL_D[8]
+set_location_assignment PIN_AA14 -to MIPI_PIXEL_D[9]
+set_location_assignment PIN_AA9 -to MIPI_PIXEL_HS
+set_location_assignment PIN_AB10 -to MIPI_PIXEL_VS
+set_location_assignment PIN_AB11 -to MIPI_REFCLK
+set_location_assignment PIN_AA8 -to MIPI_RESET_n
+
+#============================================================
+# End of pin assignments by Terasic System Builder
+#============================================================
+
+
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name OPTIMIZATION_MODE BALANCED
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name VERILOG_FILE FpsMonitor.v
+set_global_assignment -name QSYS_FILE Qsys.qsys
+set_global_assignment -name SDC_FILE DE10_LITE_D8M_VIP.SDC
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name VERILOG_FILE ip/EEE_IMGPROC/STREAM_REG.v
+set_global_assignment -name VECTOR_WAVEFORM_FILE ip/EEE_IMGPROC/STREAM_REG_TEST.vwf
+set_global_assignment -name VERILOG_FILE DE10_LITE_D8M_VIP.v
+set_global_assignment -name VERILOG_FILE ip/EEE_IMGPROC/STREAM_REG_TEST.v
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name QIP_FILE ip/EEE_IMGPROC/MSG_FIFO.qip
+set_global_assignment -name VERILOG_FILE ip/EEE_IMGPROC/EEE_IMGPROC.v
+set_global_assignment -name CDF_FILE Chain.cdf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws
new file mode 100644
index 0000000000000000000000000000000000000000..9a7beedca978bb85d11ff496ce86170b270e4bde
GIT binary patch
literal 1312
zcmeH_yG{a85QcwN3Q8+03kySt2?)jrc1A^Gf{_?vyK!+r_nm6iY$OSK-&B4C&*(2$F8{AupaGV77@m49`PZi;QG57z-0C@#?ipd#cj6cPkdxl-u-#9_rh9q@-+Rpb
literal 0
HcmV?d00001
diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v
new file mode 100644
index 0000000..c294591
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v
@@ -0,0 +1,196 @@
+
+//=======================================================
+// This code is generated by Terasic System Builder
+//=======================================================
+
+`default_nettype none
+
+module DE10_LITE_D8M_VIP(
+
+ //////////// CLOCK //////////
+ input ADC_CLK_10,
+ input MAX10_CLK1_50,
+ input MAX10_CLK2_50,
+
+ //////////// SDRAM //////////
+ output [12:0] DRAM_ADDR,
+ output [1:0] DRAM_BA,
+ output DRAM_CAS_N,
+ output DRAM_CKE,
+ output DRAM_CLK,
+ output DRAM_CS_N,
+ inout [15:0] DRAM_DQ,
+ output DRAM_LDQM,
+ output DRAM_RAS_N,
+ output DRAM_UDQM,
+ output DRAM_WE_N,
+
+ //////////// SEG7 //////////
+ output [7:0] HEX0,
+ output [7:0] HEX1,
+ output [7:0] HEX2,
+ output [7:0] HEX3,
+ output [7:0] HEX4,
+ output [7:0] HEX5,
+
+ //////////// KEY //////////
+ input [1:0] KEY,
+
+ //////////// LED //////////
+ output [9:0] LEDR,
+
+ //////////// SW //////////
+ input [9:0] SW,
+
+ //////////// VGA //////////
+ output [3:0] VGA_B,
+ output [3:0] VGA_G,
+ output VGA_HS,
+ output [3:0] VGA_R,
+ output VGA_VS,
+
+ //////////// Accelerometer //////////
+ output GSENSOR_CS_N,
+ input [2:1] GSENSOR_INT,
+ output GSENSOR_SCLK,
+ inout GSENSOR_SDI,
+ inout GSENSOR_SDO,
+
+ //////////// Arduino //////////
+ inout [15:0] ARDUINO_IO,
+ inout ARDUINO_RESET_N,
+
+ //////////// GPIO, GPIO connect to D8M-GPIO //////////
+ inout CAMERA_I2C_SCL,
+ inout CAMERA_I2C_SDA,
+ output CAMERA_PWDN_n,
+ output MIPI_CS_n,
+ inout MIPI_I2C_SCL,
+ inout MIPI_I2C_SDA,
+ output MIPI_MCLK,
+ input MIPI_PIXEL_CLK,
+ input [9:0] MIPI_PIXEL_D,
+ input MIPI_PIXEL_HS,
+ input MIPI_PIXEL_VS,
+ output MIPI_REFCLK,
+ output MIPI_RESET_n
+);
+
+
+
+//=======================================================
+// REG/WIRE declarations
+//=======================================================
+wire disp_clk;
+wire disp_hs;
+wire disp_vs;
+wire [23:0] disp_data;
+wire [7 :0] mVGA_R;
+wire [7 :0] mVGA_G;
+wire [7 :0] mVGA_B;
+
+
+
+//=======================================================
+// Structural coding
+//=======================================================
+assign VGA_HS = disp_hs;
+assign VGA_VS = disp_vs;
+assign {mVGA_R, mVGA_G, mVGA_B} = disp_data;
+
+assign VGA_R = mVGA_R[7:4];
+assign VGA_G = mVGA_G[7:4];
+assign VGA_B = mVGA_B[7:4];
+
+assign MIPI_CS_n = 1'b0;
+
+
+
+///////////////////////////////////////
+wire MIPI_PIXEL_CLK_d;
+reg MIPI_PIXEL_VS_d;
+reg MIPI_PIXEL_HS_d;
+reg [9:0] MIPI_PIXEL_D_d;
+
+assign MIPI_PIXEL_CLK_d = ~MIPI_PIXEL_CLK;
+
+always @ (posedge MIPI_PIXEL_CLK_d) begin
+ MIPI_PIXEL_VS_d <= MIPI_PIXEL_VS;
+ MIPI_PIXEL_HS_d <= MIPI_PIXEL_HS;
+ MIPI_PIXEL_D_d <= MIPI_PIXEL_D;
+end
+
+
+
+Qsys u0 (
+ .clk_clk (MAX10_CLK1_50), // clk.clk
+ .reset_reset_n (1'b1), // reset.reset_n
+
+ .clk_sdram_clk (DRAM_CLK), // clk_sdram.clk
+ .clk_vga_clk (disp_clk), // clk_vga.clk
+ .d8m_xclkin_clk (MIPI_REFCLK), // d8m_xclkin.clk
+
+ .key_external_connection_export (KEY), // key_external_connection.export
+ .led_external_connection_export (), // led_external_connection.export
+ .sw_external_connection_export (SW), // sw_external_connection.export
+
+ .i2c_opencores_camera_export_scl_pad_io (CAMERA_I2C_SCL), // i2c_opencores_camera_export.scl_pad_io
+ .i2c_opencores_camera_export_sda_pad_io (CAMERA_I2C_SDA), // .sda_pad_io
+
+ .i2c_opencores_mipi_export_scl_pad_io (MIPI_I2C_SCL), // i2c_opencores_mipi_export.scl_pad_io
+ .i2c_opencores_mipi_export_sda_pad_io (MIPI_I2C_SDA), // .sda_pad_io
+
+ .mipi_pwdn_n_external_connection_export (CAMERA_PWDN_n), // mipi_pwdn_n_external_connection.export
+ .mipi_reset_n_external_connection_export (MIPI_RESET_n), // mipi_reset_n_external_connection.export
+
+ .sdram_wire_addr (DRAM_ADDR), // sdram_wire.addr
+ .sdram_wire_ba (DRAM_BA), // .ba
+ .sdram_wire_cas_n (DRAM_CAS_N), // .cas_n
+ .sdram_wire_cke (DRAM_CKE), // .cke
+ .sdram_wire_cs_n (DRAM_CS_N), // .cs_n
+ .sdram_wire_dq (DRAM_DQ), // .dq
+ .sdram_wire_dqm ({DRAM_UDQM, DRAM_LDQM}), // .dqm
+ .sdram_wire_ras_n (DRAM_RAS_N), // .ras_n
+ .sdram_wire_we_n (DRAM_WE_N), // .we_n
+
+ .terasic_camera_0_conduit_end_D ({MIPI_PIXEL_D_d[9:0], 2'b00}),// terasic_camera_0_conduit_end.D
+ .terasic_camera_0_conduit_end_FVAL (MIPI_PIXEL_VS_d), // .FVAL
+ .terasic_camera_0_conduit_end_LVAL (MIPI_PIXEL_HS_d), // .LVAL
+ .terasic_camera_0_conduit_end_PIXCLK (~MIPI_PIXEL_CLK_d), // .PIXCLK
+
+ .terasic_auto_focus_0_conduit_vcm_i2c_sda (CAMERA_I2C_SDA), // terasic_auto_focus_0_conduit.vcm_i2c_sda
+ .terasic_auto_focus_0_conduit_clk50 (MAX10_CLK1_50), // .clk50
+ .terasic_auto_focus_0_conduit_vcm_i2c_scl (CAMERA_I2C_SCL), // .vcm_i2c_scl
+
+ .alt_vip_itc_0_clocked_video_vid_clk (disp_clk), // alt_vip_itc_0_clocked_video.vid_clk
+ .alt_vip_itc_0_clocked_video_vid_data (disp_data), // .vid_data
+ .alt_vip_itc_0_clocked_video_underflow (), // .underflow
+ .alt_vip_itc_0_clocked_video_vid_datavalid (), // .vid_datavalid
+ .alt_vip_itc_0_clocked_video_vid_v_sync (disp_vs), // .vid_v_sync
+ .alt_vip_itc_0_clocked_video_vid_h_sync (disp_hs), // .vid_h_sync
+ .alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
+ .alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
+ .alt_vip_itc_0_clocked_video_vid_v (), // .vid_v
+
+ .altpll_0_areset_conduit_export (), // altpll_0_areset_conduit.export
+ .altpll_0_locked_conduit_export (), // altpll_0_locked_conduit.export
+ .altpll_0_phasedone_conduit_export (), // altpll_0_phasedone_conduit.export
+
+ .eee_imgproc_0_conduit_mode_new_signal (SW[0])
+ );
+
+FpsMonitor uFps(
+ .clk50(MAX10_CLK2_50),
+ .vs(MIPI_PIXEL_VS),
+
+ .fps(),
+ .hex_fps_h(HEX1),
+ .hex_fps_l(HEX0)
+);
+
+assign HEX2 = 7'h7F;
+assign HEX3 = 7'h7F;
+assign HEX4 = 7'h7F;
+assign HEX5 = 7'h7F;
+
+endmodule
diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP_assignment_defaults.qdf b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP_assignment_defaults.qdf
new file mode 100644
index 0000000..a644b0f
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP_assignment_defaults.qdf
@@ -0,0 +1,808 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020 Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors. Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 13:06:40 March 09, 2021
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+# automatically by the Quartus Prime software and is used
+# to preserve global assignments across Quartus Prime versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base -family "Arria V"
+set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
+set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
+set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
+set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name OCP_HW_EVAL -value OFF
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL ""
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
+set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name PHYSICAL_SYNTHESIS Off
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
+set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
+set_global_assignment -name USE_CONF_DONE AUTO
+set_global_assignment -name USE_PWRMGT_SCL AUTO
+set_global_assignment -name USE_PWRMGT_SDA AUTO
+set_global_assignment -name USE_PWRMGT_ALERT AUTO
+set_global_assignment -name USE_INIT_DONE AUTO
+set_global_assignment -name USE_CVP_CONFDONE AUTO
+set_global_assignment -name USE_SEU_ERROR AUTO
+set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
+set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
+set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
+set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name RESERVE_PR_PINS Off
+set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
+set_global_assignment -name SEU_FIT_REPORT Off
+set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
+set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
+set_global_assignment -name EDA_SIMULATION_TOOL ""
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL ""
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL ""
+set_global_assignment -name EDA_RESYNTHESIS_TOOL ""
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
+set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
+set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
+set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
+set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name GENERATE_PMSF_FILES On
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
diff --git a/Vision/DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl b/Vision/DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl
new file mode 100644
index 0000000..85a03e7
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl
@@ -0,0 +1,183 @@
+# TCL File Generated by Component Editor 16.0
+# Fri Apr 23 12:07:51 BST 2021
+# DO NOT MODIFY
+
+
+#
+# EEE_IMGPROC "EEE_IMGPROC" v1.0
+# 2021.04.23.12:07:51
+#
+#
+
+#
+# request TCL package from ACDS 16.0
+#
+package require -exact qsys 16.0
+
+
+#
+# module EEE_IMGPROC
+#
+set_module_property DESCRIPTION ""
+set_module_property NAME EEE_IMGPROC
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME EEE_IMGPROC
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+#
+# file sets
+#
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL EEE_IMGPROC
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file EEE_IMGPROC.v VERILOG PATH ip/EEE_IMGPROC/EEE_IMGPROC.v TOP_LEVEL_FILE
+
+
+#
+# parameters
+#
+
+
+#
+# display items
+#
+
+
+#
+# connection point clock
+#
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+#
+# connection point reset
+#
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset_n reset_n Input 1
+
+
+#
+# connection point avalon_streaming_sink
+#
+add_interface avalon_streaming_sink avalon_streaming end
+set_interface_property avalon_streaming_sink associatedClock clock
+set_interface_property avalon_streaming_sink associatedReset reset
+set_interface_property avalon_streaming_sink dataBitsPerSymbol 8
+set_interface_property avalon_streaming_sink errorDescriptor ""
+set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true
+set_interface_property avalon_streaming_sink maxChannel 0
+set_interface_property avalon_streaming_sink readyLatency 1
+set_interface_property avalon_streaming_sink ENABLED true
+set_interface_property avalon_streaming_sink EXPORT_OF ""
+set_interface_property avalon_streaming_sink PORT_NAME_MAP ""
+set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_streaming_sink sink_data data Input 24
+add_interface_port avalon_streaming_sink sink_valid valid Input 1
+add_interface_port avalon_streaming_sink sink_ready ready Output 1
+add_interface_port avalon_streaming_sink sink_sop startofpacket Input 1
+add_interface_port avalon_streaming_sink sink_eop endofpacket Input 1
+
+
+#
+# connection point avalon_streaming_source
+#
+add_interface avalon_streaming_source avalon_streaming start
+set_interface_property avalon_streaming_source associatedClock clock
+set_interface_property avalon_streaming_source associatedReset reset
+set_interface_property avalon_streaming_source dataBitsPerSymbol 8
+set_interface_property avalon_streaming_source errorDescriptor ""
+set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true
+set_interface_property avalon_streaming_source maxChannel 0
+set_interface_property avalon_streaming_source readyLatency 1
+set_interface_property avalon_streaming_source ENABLED true
+set_interface_property avalon_streaming_source EXPORT_OF ""
+set_interface_property avalon_streaming_source PORT_NAME_MAP ""
+set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_streaming_source source_data data Output 24
+add_interface_port avalon_streaming_source source_eop endofpacket Output 1
+add_interface_port avalon_streaming_source source_ready ready Input 1
+add_interface_port avalon_streaming_source source_sop startofpacket Output 1
+add_interface_port avalon_streaming_source source_valid valid Output 1
+
+
+#
+# connection point s1
+#
+add_interface s1 avalon end
+set_interface_property s1 addressUnits WORDS
+set_interface_property s1 associatedClock clock
+set_interface_property s1 associatedReset reset
+set_interface_property s1 bitsPerSymbol 8
+set_interface_property s1 burstOnBurstBoundariesOnly false
+set_interface_property s1 burstcountUnits WORDS
+set_interface_property s1 explicitAddressSpan 0
+set_interface_property s1 holdTime 0
+set_interface_property s1 linewrapBursts false
+set_interface_property s1 maximumPendingReadTransactions 0
+set_interface_property s1 maximumPendingWriteTransactions 0
+set_interface_property s1 readLatency 0
+set_interface_property s1 readWaitTime 1
+set_interface_property s1 setupTime 0
+set_interface_property s1 timingUnits Cycles
+set_interface_property s1 writeWaitTime 0
+set_interface_property s1 ENABLED true
+set_interface_property s1 EXPORT_OF ""
+set_interface_property s1 PORT_NAME_MAP ""
+set_interface_property s1 CMSIS_SVD_VARIABLES ""
+set_interface_property s1 SVD_ADDRESS_GROUP ""
+
+add_interface_port s1 s_chipselect chipselect Input 1
+add_interface_port s1 s_read read Input 1
+add_interface_port s1 s_write write Input 1
+add_interface_port s1 s_readdata readdata Output 32
+add_interface_port s1 s_writedata writedata Input 32
+add_interface_port s1 s_address address Input 3
+set_interface_assignment s1 embeddedsw.configuration.isFlash 0
+set_interface_assignment s1 embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment s1 embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment s1 embeddedsw.configuration.isPrintableDevice 0
+
+
+#
+# connection point conduit_mode
+#
+add_interface conduit_mode conduit end
+set_interface_property conduit_mode associatedClock clock
+set_interface_property conduit_mode associatedReset ""
+set_interface_property conduit_mode ENABLED true
+set_interface_property conduit_mode EXPORT_OF ""
+set_interface_property conduit_mode PORT_NAME_MAP ""
+set_interface_property conduit_mode CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_mode SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_mode mode new_signal Input 1
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/FpsMonitor.v b/Vision/DE10_LITE_D8M_VIP_16/FpsMonitor.v
new file mode 100644
index 0000000..b3659b0
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/FpsMonitor.v
@@ -0,0 +1,82 @@
+module FpsMonitor(
+ input clk50,
+ input vs,
+
+ // output frame pixel data
+ output reg [7:0] fps,
+ output wire [6:0] hex_fps_h,
+ output wire [6:0] hex_fps_l
+
+);
+
+
+parameter ONE_SEC = 32'd50_000_000;
+
+reg [3:0] fps_h;
+reg [3:0] fps_l;
+
+reg [7:0] rfps;
+reg [3:0] rfps_l;
+reg [3:0] rfps_h;
+
+reg [26:0] sec_cnt;
+reg pre_vs;
+wire one_sec_mask;
+
+assign one_sec_mask = (sec_cnt>= (ONE_SEC - 1'b1) )?1'b1:1'b0;
+
+always @(posedge clk50)
+ if(one_sec_mask) sec_cnt <= 27'h0;
+ else sec_cnt <= sec_cnt + 1'b1;
+
+
+always @(posedge clk50) begin
+ pre_vs <= vs;
+ if(sec_cnt == 27'd0) begin
+ rfps <= 8'd0;
+ rfps_h <= 4'd0;
+ rfps_l <= 4'd0;
+ end
+ else if({pre_vs,vs} == 2'b01) begin
+ rfps <= rfps + 1'b1;
+
+ if(rfps_l == 4'd9) begin
+ rfps_l <= 4'd0;
+ rfps_h <= rfps_h + 1'b1;
+ end
+ else rfps_l <= rfps_l + 1'b1;
+ end
+
+end
+
+
+always @ (posedge clk50)
+ if(one_sec_mask) begin
+ fps <= rfps;
+ fps_h <= rfps_h;
+ fps_l <= rfps_l;
+ end
+
+assign hex_fps_h = (fps_h == 4'd0)?7'h40: //0
+ (fps_h == 4'd1)?7'h79: //1
+ (fps_h == 4'd2)?7'h24: //2
+ (fps_h == 4'd3)?7'h30: //3
+ (fps_h == 4'd4)?7'h19: //4
+ (fps_h == 4'd5)?7'h12: //5
+ (fps_h == 4'd6)?7'h02: //6
+ (fps_h == 4'd7)?7'h78: //7
+ (fps_h == 4'd8)?7'h00: //8
+ 7'h10; //9
+
+assign hex_fps_l = (fps_l == 4'd0)?7'h40: //0
+ (fps_l == 4'd1)?7'h79: //1
+ (fps_l == 4'd2)?7'h24: //2
+ (fps_l == 4'd3)?7'h30: //3
+ (fps_l == 4'd4)?7'h19: //4
+ (fps_l == 4'd5)?7'h12: //5
+ (fps_l == 4'd6)?7'h02: //6
+ (fps_l == 4'd7)?7'h78: //7
+ (fps_l == 4'd8)?7'h00: //8
+ 7'h10; //9
+endmodule
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys b/Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys
new file mode 100644
index 0000000..08eeb63
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys
@@ -0,0 +1,1471 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DE10_LITE_D8M_VIP.qpf
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+ MyFrameBuffer640480813falsetrue0true0000000032false1024410244110000false]]>
+
+
+
+
+
+
+
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+
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+
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+
+
+ CT#CLK2_DIVIDE_BY 1 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 5 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 2 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 7500 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 2 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_USED
+ altpll_avalon_elaboration
+ altpll_avalon_post_edit
+ IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}
+
+ IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
+ MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
+ PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 20.00000000 PT#OUTPUT_FREQ3 25.00000000 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 270.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 20.000000 PT#EFF_OUTPUT_FREQ_VALUE3 25.000000 PT#EFF_OUTPUT_FREQ_VALUE2 100.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1472001986172141.mif PT#ACTIVECLK_CHECK 0
+ UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
+
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+ NO_INTERACTIVE_WINDOWS
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+ ]]>
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+
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+
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+ ]]>
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+ $${FILENAME}_onchip_memory2_0
+
+
+
+
+
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ single_Micron_MT48LC4M32B2_7_chip
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo b/Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo
new file mode 100644
index 0000000..c3b5fca
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo
@@ -0,0 +1,21866 @@
+
+
+
+
+
+
+ java.lang.Integer
+ 1621008007
+ false
+ true
+ false
+ true
+ GENERATION_ID
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+ UNIQUE_ID
+
+
+ java.lang.String
+ MAX10FPGA
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ java.lang.String
+ 10M50DAF484C7G
+ false
+ true
+ false
+ true
+ DEVICE
+
+
+ java.lang.String
+ 7
+ false
+ true
+ false
+ true
+ DEVICE_SPEEDGRADE
+
+
+ java.lang.Long
+ -1
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ java.lang.Integer
+ -1
+ false
+ true
+ false
+ true
+ CLOCK_DOMAIN
+ clk
+
+
+ java.lang.Integer
+ -1
+ false
+ true
+ false
+ true
+ RESET_DOMAIN
+ clk
+
+
+ java.lang.String
+ MAX 10
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ [Ljava.lang.String;
+
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon_streaming
+ false
+
+ sink_data
+ Input
+ 24
+ data
+
+
+ sink_valid
+ Input
+ 1
+ valid
+
+
+ sink_ready
+ Output
+ 1
+ ready
+
+
+ sink_sop
+ Input
+ 1
+ startofpacket
+
+
+ sink_eop
+ Input
+ 1
+ endofpacket
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ [Ljava.lang.String;
+
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon_streaming
+ true
+
+ source_data
+ Output
+ 24
+ data
+
+
+ source_eop
+ Output
+ 1
+ endofpacket
+
+
+ source_ready
+ Input
+ 1
+ ready
+
+
+ source_sop
+ Output
+ 1
+ startofpacket
+
+
+ source_valid
+ Output
+ 1
+ valid
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 32
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ s_chipselect
+ Input
+ 1
+ chipselect
+
+
+ s_read
+ Input
+ 1
+ read
+
+
+ s_write
+ Input
+ 1
+ write
+
+
+ s_readdata
+ Output
+ 32
+ readdata
+
+
+ s_writedata
+ Input
+ 32
+ writedata
+
+
+ s_address
+ Input
+ 3
+ address
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ mode
+ Input
+ 1
+ new_signal
+
+
+
+
+
+
+ int
+ 640
+ false
+ true
+ true
+ true
+
+
+ int
+ 480
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 32
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ s_chipselect
+ Input
+ 1
+ chipselect
+
+
+ s_read
+ Input
+ 1
+ read
+
+
+ s_write
+ Input
+ 1
+ write
+
+
+ s_readdata
+ Output
+ 32
+ readdata
+
+
+ s_writedata
+ Input
+ 32
+ writedata
+
+
+ s_address
+ Input
+ 3
+ address
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ [Ljava.lang.String;
+
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon_streaming
+ false
+
+ sink_data
+ Input
+ 24
+ data
+
+
+ sink_valid
+ Input
+ 1
+ valid
+
+
+ sink_ready
+ Output
+ 1
+ ready
+
+
+ sink_sop
+ Input
+ 1
+ startofpacket
+
+
+ sink_eop
+ Input
+ 1
+ endofpacket
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ [Ljava.lang.String;
+
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon_streaming
+ true
+
+ source_data
+ Output
+ 24
+ data
+
+
+ source_valid
+ Output
+ 1
+ valid
+
+
+ source_ready
+ Input
+ 1
+ ready
+
+
+ source_sop
+ Output
+ 1
+ startofpacket
+
+
+ source_eop
+ Output
+ 1
+ endofpacket
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ vcm_i2c_sda
+ Bidir
+ 1
+ vcm_i2c_sda
+
+
+ clk50
+ Input
+ 1
+ clk50
+
+
+ vcm_i2c_scl
+ Bidir
+ 1
+ vcm_i2c_scl
+
+
+
+
+
+
+ int
+ 640
+ false
+ true
+ true
+ true
+
+
+ int
+ 480
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clock_reset
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ CAMERA_D
+ Input
+ 12
+ export
+
+
+ CAMERA_FVAL
+ Input
+ 1
+ export
+
+
+ CAMERA_LVAL
+ Input
+ 1
+ export
+
+
+ CAMERA_PIXCLK
+ Input
+ 1
+ export
+
+
+
+
+
+ java.lang.String
+ clock_reset
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock_reset_reset
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ [Ljava.lang.String;
+
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
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+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon_streaming
+ true
+
+ st_data
+ Output
+ 24
+ data
+
+
+ st_sop
+ Output
+ 1
+ startofpacket
+
+
+ st_eop
+ Output
+ 1
+ endofpacket
+
+
+ st_ready
+ Input
+ 1
+ ready
+
+
+ st_valid
+ Output
+ 1
+ valid
+
+
+
+
+
+
+ java.lang.String
+ MAX10FPGA
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ int
+ 3
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 640
+ false
+ true
+ true
+ true
+
+
+ int
+ 480
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 640
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 639
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
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+ true
+
+
+ int
+ 0
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+ true
+
+
+ int
+ 0
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+ true
+ true
+ true
+
+
+ int
+ 96
+ false
+ true
+ true
+ true
+
+
+ int
+ 16
+ false
+ true
+ true
+ true
+
+
+ int
+ 48
+ false
+ true
+ true
+ true
+
+
+ int
+ 2
+ false
+ true
+ true
+ true
+
+
+ int
+ 10
+ false
+ true
+ true
+ true
+
+
+ int
+ 33
+ false
+ true
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+ true
+
+
+ int
+ 0
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+ true
+
+
+ int
+ 0
+ false
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+ true
+ true
+
+
+ int
+ 0
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+ true
+ true
+
+
+ int
+ 0
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+
+
+ int
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+
+
+ int
+ 0
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+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
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+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ is_clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ is_clk_rst
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ rst
+ Input
+ 1
+ reset
+
+
+
+
+
+ java.lang.String
+ is_clk_rst
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ is_clk_rst_reset
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ [Ljava.lang.String;
+
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ int
+ 3
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon_streaming
+ false
+
+ is_data
+ Input
+ 24
+ data
+
+
+ is_valid
+ Input
+ 1
+ valid
+
+
+ is_ready
+ Output
+ 1
+ ready
+
+
+ is_sop
+ Input
+ 1
+ startofpacket
+
+
+ is_eop
+ Input
+ 1
+ endofpacket
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ vid_clk
+ Input
+ 1
+ export
+
+
+ vid_data
+ Output
+ 24
+ export
+
+
+ underflow
+ Output
+ 1
+ export
+
+
+ vid_datavalid
+ Output
+ 1
+ export
+
+
+ vid_v_sync
+ Output
+ 1
+ export
+
+
+ vid_h_sync
+ Output
+ 1
+ export
+
+
+ vid_f
+ Output
+ 1
+ export
+
+
+ vid_h
+ Output
+ 1
+ export
+
+
+ vid_v
+ Output
+ 1
+ export
+
+
+
+
+
+
+ java.lang.String
+ 0
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 0
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 2
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 0
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 2
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ MAX10FPGA
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ java.lang.String
+ 0
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 0
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 0
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 27
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ 27
+ true
+ true
+ true
+ true
+
+
+ java.lang.String
+ MyFrameBuffer640480813falsetrue0true0000000032false1024410244110000false]]>
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ MAX 10
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ clock
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset
+ Input
+ 1
+ reset
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ boolean
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+ CT#CLK2_DIVIDE_BY 1 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 5 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 2 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 7500 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 2 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_USED
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 20.00000000 PT#OUTPUT_FREQ3 25.00000000 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 270.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 20.000000 PT#EFF_OUTPUT_FREQ_VALUE3 25.000000 PT#EFF_OUTPUT_FREQ_VALUE2 100.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1472001986172141.mif PT#ACTIVECLK_CHECK 0
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ MAX10FPGA
+ false
+ true
+ false
+ true
+ DEVICE_FAMILY
+
+
+ java.lang.Long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ inclk_interface
+
+
+ java.lang.String
+ MAX 10
+ false
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+ false
+ true
+ DEVICE_FAMILY
+
+
+ boolean
+ false
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+ boolean
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+ java.lang.Long
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+ true
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+ true
+
+ clock
+ false
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+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ inclk_interface
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
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+ true
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+
+ boolean
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+ false
+
+ reset
+ Input
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+
+
+
+ embeddedsw.configuration.isMemoryDevice
+ false
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ false
+
+
+ embeddedsw.configuration.isPrintableDevice
+ false
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
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+ true
+
+
+ java.math.BigInteger
+ 16
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+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
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+ false
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+ false
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+
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+ true
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+
+ java.lang.String
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+ false
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+
+ int
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+ false
+ true
+ true
+ true
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+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
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+ true
+ true
+
+
+ boolean
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+ true
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+
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+ false
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+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
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+ false
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+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ read
+ Input
+ 1
+ read
+
+
+ write
+ Input
+ 1
+ write
+
+
+ address
+ Input
+ 2
+ address
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+ writedata
+ Input
+ 32
+ writedata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ long
+ 100000000
+ false
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+ true
+ true
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+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ true
+
+ c0
+ Output
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ long
+ 100000000
+ false
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+
+
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+ true
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+
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+ true
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+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ true
+
+ c1
+ Output
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ long
+ 100000000
+ false
+ true
+ true
+ true
+
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+
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+ UNKNOWN
+ false
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+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ true
+
+ c2
+ Output
+ 1
+ clk
+
+
+ false
+ sdram
+ clk
+ sdram.clk
+
+
+ false
+ TERASIC_AUTO_FOCUS_0
+ clock
+ TERASIC_AUTO_FOCUS_0.clock
+
+
+ false
+ alt_vip_vfb_0
+ clock
+ alt_vip_vfb_0.clock
+
+
+ false
+ EEE_IMGPROC_0
+ clock
+ EEE_IMGPROC_0.clock
+
+
+ false
+ TERASIC_CAMERA_0
+ clock_reset
+ TERASIC_CAMERA_0.clock_reset
+
+
+ false
+ alt_vip_itc_0
+ is_clk_rst
+ alt_vip_itc_0.is_clk_rst
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ long
+ 25000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ true
+
+ c3
+ Output
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ long
+ 20000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ true
+
+ c4
+ Output
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ areset
+ Input
+ 1
+ export
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ locked
+ Output
+ 1
+ export
+
+
+
+
+
+
+ long
+ 50000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ long
+ 0
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk_in
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ NONE
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ qsys.ui.export_name
+ clk
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ in_clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ qsys.ui.export_name
+ reset
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ NONE
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ java.lang.String
+ clk_in
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ true
+
+ clk_out
+ Output
+ 1
+ clk
+
+
+ false
+ jtag_uart
+ clk
+ jtag_uart.clk
+
+
+ false
+ sysid_qsys
+ clk
+ sysid_qsys.clk
+
+
+ false
+ timer
+ clk
+ timer.clk
+
+
+ false
+ led
+ clk
+ led.clk
+
+
+ false
+ sw
+ clk
+ sw.clk
+
+
+ false
+ key
+ clk
+ key.clk
+
+
+ false
+ mipi_reset_n
+ clk
+ mipi_reset_n.clk
+
+
+ false
+ mipi_pwdn_n
+ clk
+ mipi_pwdn_n.clk
+
+
+ false
+ nios2_gen2
+ clk
+ nios2_gen2.clk
+
+
+ false
+ onchip_memory2_0
+ clk1
+ onchip_memory2_0.clk1
+
+
+ false
+ i2c_opencores_mipi
+ clock
+ i2c_opencores_mipi.clock
+
+
+ false
+ i2c_opencores_camera
+ clock
+ i2c_opencores_camera.clock
+
+
+ false
+ altpll_0
+ inclk_interface
+ altpll_0.inclk_interface
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clk_in_reset
+ false
+ true
+ true
+ true
+
+
+ [Ljava.lang.String;
+ clk_in_reset
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ NONE
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ true
+
+ reset_n_out
+ Output
+ 1
+ reset_n
+
+
+
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ wb_clk_i
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ wb_rst_i
+ Input
+ 1
+ reset
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ scl_pad_io
+ Bidir
+ 1
+ export
+
+
+ sda_pad_io
+ Bidir
+ 1
+ export
+
+
+
+
+
+ embeddedsw.configuration.isMemoryDevice
+ false
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ false
+
+
+ embeddedsw.configuration.isPrintableDevice
+ false
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 8
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clock_reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ wb_adr_i
+ Input
+ 3
+ address
+
+
+ wb_dat_i
+ Input
+ 8
+ writedata
+
+
+ wb_dat_o
+ Output
+ 8
+ readdata
+
+
+ wb_we_i
+ Input
+ 1
+ write
+
+
+ wb_stb_i
+ Input
+ 1
+ chipselect
+
+
+ wb_ack_o
+ Output
+ 1
+ waitrequest_n
+
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+ i2c_opencores_camera.avalon_slave_0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock_reset
+ false
+ true
+ false
+ true
+
+
+ java.lang.Integer
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme
+ NONE
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ interrupt
+ false
+
+ wb_inta_o
+ Output
+ 1
+ irq
+
+
+
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ wb_clk_i
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ wb_rst_i
+ Input
+ 1
+ reset
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ scl_pad_io
+ Bidir
+ 1
+ export
+
+
+ sda_pad_io
+ Bidir
+ 1
+ export
+
+
+
+
+
+ embeddedsw.configuration.isMemoryDevice
+ false
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ false
+
+
+ embeddedsw.configuration.isPrintableDevice
+ false
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 8
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clock_reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ wb_adr_i
+ Input
+ 3
+ address
+
+
+ wb_dat_i
+ Input
+ 8
+ writedata
+
+
+ wb_dat_o
+ Output
+ 8
+ readdata
+
+
+ wb_we_i
+ Input
+ 1
+ write
+
+
+ wb_stb_i
+ Input
+ 1
+ chipselect
+
+
+ wb_ack_o
+ Output
+ 1
+ waitrequest_n
+
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+ i2c_opencores_mipi.avalon_slave_0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clock
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clock_reset
+ false
+ true
+ false
+ true
+
+
+ java.lang.Integer
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme
+ NONE
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ interrupt
+ false
+
+ wb_inta_o
+ Output
+ 1
+ irq
+
+
+
+
+
+
+ embeddedsw.CMacro.READ_DEPTH
+ 64
+
+
+ embeddedsw.CMacro.READ_THRESHOLD
+ 8
+
+
+ embeddedsw.CMacro.WRITE_DEPTH
+ 64
+
+
+ embeddedsw.CMacro.WRITE_THRESHOLD
+ 8
+
+
+ embeddedsw.dts.compatible
+ altr,juart-1.0
+
+
+ embeddedsw.dts.group
+ serial
+
+
+ embeddedsw.dts.name
+ juart
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 64
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ false
+ false
+ true
+
+
+ java.lang.String
+ NO_INTERACTIVE_WINDOWS
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 64
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ java.lang.String
+ 2.0
+ false
+ true
+ false
+ true
+ AVALON_SPEC
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ rst_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 1
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 2
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ true
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ av_chipselect
+ Input
+ 1
+ chipselect
+
+
+ av_address
+ Input
+ 1
+ address
+
+
+ av_read_n
+ Input
+ 1
+ read_n
+
+
+ av_readdata
+ Output
+ 32
+ readdata
+
+
+ av_write_n
+ Input
+ 1
+ write_n
+
+
+ av_writedata
+ Input
+ 32
+ writedata
+
+
+ av_waitrequest
+ Output
+ 1
+ waitrequest
+
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+ jtag_uart.avalon_jtag_slave
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ java.lang.Integer
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme
+ NONE
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ interrupt
+ false
+
+ av_irq
+ Output
+ 1
+ irq
+
+
+
+
+
+
+ embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.CAPTURE
+ 0
+
+
+ embeddedsw.CMacro.DATA_WIDTH
+ 2
+
+
+ embeddedsw.CMacro.DO_TEST_BENCH_WIRING
+ 0
+
+
+ embeddedsw.CMacro.DRIVEN_SIM_VALUE
+ 0
+
+
+ embeddedsw.CMacro.EDGE_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.FREQ
+ 50000000
+
+
+ embeddedsw.CMacro.HAS_IN
+ 1
+
+
+ embeddedsw.CMacro.HAS_OUT
+ 0
+
+
+ embeddedsw.CMacro.HAS_TRI
+ 0
+
+
+ embeddedsw.CMacro.IRQ_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.RESET_VALUE
+ 0
+
+
+ embeddedsw.dts.compatible
+ altr,pio-1.0
+
+
+ embeddedsw.dts.group
+ gpio
+
+
+ embeddedsw.dts.name
+ pio
+
+
+ embeddedsw.dts.params.altr,gpio-bank-width
+ 2
+
+
+ embeddedsw.dts.params.resetvalue
+ 0
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ Input
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ RISING
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ LEVEL
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 2
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 4
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ address
+ Input
+ 2
+ address
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ in_port
+ Input
+ 2
+ export
+
+
+
+
+
+
+ embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.CAPTURE
+ 0
+
+
+ embeddedsw.CMacro.DATA_WIDTH
+ 10
+
+
+ embeddedsw.CMacro.DO_TEST_BENCH_WIRING
+ 0
+
+
+ embeddedsw.CMacro.DRIVEN_SIM_VALUE
+ 0
+
+
+ embeddedsw.CMacro.EDGE_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.FREQ
+ 50000000
+
+
+ embeddedsw.CMacro.HAS_IN
+ 0
+
+
+ embeddedsw.CMacro.HAS_OUT
+ 1
+
+
+ embeddedsw.CMacro.HAS_TRI
+ 0
+
+
+ embeddedsw.CMacro.IRQ_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.RESET_VALUE
+ 0
+
+
+ embeddedsw.dts.compatible
+ altr,pio-1.0
+
+
+ embeddedsw.dts.group
+ gpio
+
+
+ embeddedsw.dts.name
+ pio
+
+
+ embeddedsw.dts.params.altr,gpio-bank-width
+ 10
+
+
+ embeddedsw.dts.params.resetvalue
+ 0
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ Output
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ RISING
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ LEVEL
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 10
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 4
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ address
+ Input
+ 2
+ address
+
+
+ write_n
+ Input
+ 1
+ write_n
+
+
+ writedata
+ Input
+ 32
+ writedata
+
+
+ chipselect
+ Input
+ 1
+ chipselect
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ out_port
+ Output
+ 10
+ export
+
+
+
+
+
+
+ embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.CAPTURE
+ 0
+
+
+ embeddedsw.CMacro.DATA_WIDTH
+ 1
+
+
+ embeddedsw.CMacro.DO_TEST_BENCH_WIRING
+ 0
+
+
+ embeddedsw.CMacro.DRIVEN_SIM_VALUE
+ 0
+
+
+ embeddedsw.CMacro.EDGE_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.FREQ
+ 50000000
+
+
+ embeddedsw.CMacro.HAS_IN
+ 0
+
+
+ embeddedsw.CMacro.HAS_OUT
+ 1
+
+
+ embeddedsw.CMacro.HAS_TRI
+ 0
+
+
+ embeddedsw.CMacro.IRQ_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.RESET_VALUE
+ 0
+
+
+ embeddedsw.dts.compatible
+ altr,pio-1.0
+
+
+ embeddedsw.dts.group
+ gpio
+
+
+ embeddedsw.dts.name
+ pio
+
+
+ embeddedsw.dts.params.altr,gpio-bank-width
+ 1
+
+
+ embeddedsw.dts.params.resetvalue
+ 0
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ Output
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ RISING
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ LEVEL
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 4
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ address
+ Input
+ 2
+ address
+
+
+ write_n
+ Input
+ 1
+ write_n
+
+
+ writedata
+ Input
+ 32
+ writedata
+
+
+ chipselect
+ Input
+ 1
+ chipselect
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ out_port
+ Output
+ 1
+ export
+
+
+
+
+
+
+ embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.CAPTURE
+ 0
+
+
+ embeddedsw.CMacro.DATA_WIDTH
+ 1
+
+
+ embeddedsw.CMacro.DO_TEST_BENCH_WIRING
+ 0
+
+
+ embeddedsw.CMacro.DRIVEN_SIM_VALUE
+ 0
+
+
+ embeddedsw.CMacro.EDGE_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.FREQ
+ 50000000
+
+
+ embeddedsw.CMacro.HAS_IN
+ 0
+
+
+ embeddedsw.CMacro.HAS_OUT
+ 1
+
+
+ embeddedsw.CMacro.HAS_TRI
+ 0
+
+
+ embeddedsw.CMacro.IRQ_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.RESET_VALUE
+ 0
+
+
+ embeddedsw.dts.compatible
+ altr,pio-1.0
+
+
+ embeddedsw.dts.group
+ gpio
+
+
+ embeddedsw.dts.name
+ pio
+
+
+ embeddedsw.dts.params.altr,gpio-bank-width
+ 1
+
+
+ embeddedsw.dts.params.resetvalue
+ 0
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ Output
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ RISING
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ LEVEL
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 4
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ address
+ Input
+ 2
+ address
+
+
+ write_n
+ Input
+ 1
+ write_n
+
+
+ writedata
+ Input
+ 32
+ writedata
+
+
+ chipselect
+ Input
+ 1
+ chipselect
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ out_port
+ Output
+ 1
+ export
+
+
+
+
+
+
+ debug.hostConnection
+ type jtag id 70:34|110:135
+
+
+ embeddedsw.CMacro.BIG_ENDIAN
+ 0
+
+
+ embeddedsw.CMacro.BREAK_ADDR
+ 0x00040820
+
+
+ embeddedsw.CMacro.CPU_ARCH_NIOS2_R1
+
+
+
+ embeddedsw.CMacro.CPU_FREQ
+ 50000000u
+
+
+ embeddedsw.CMacro.CPU_ID_SIZE
+ 1
+
+
+ embeddedsw.CMacro.CPU_ID_VALUE
+ 0x00000000
+
+
+ embeddedsw.CMacro.CPU_IMPLEMENTATION
+ "fast"
+
+
+ embeddedsw.CMacro.DATA_ADDR_WIDTH
+ 19
+
+
+ embeddedsw.CMacro.DCACHE_BYPASS_MASK
+ 0x80000000
+
+
+ embeddedsw.CMacro.DCACHE_LINE_SIZE
+ 32
+
+
+ embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2
+ 5
+
+
+ embeddedsw.CMacro.DCACHE_SIZE
+ 2048
+
+
+ embeddedsw.CMacro.EXCEPTION_ADDR
+ 0x00020020
+
+
+ embeddedsw.CMacro.FLASH_ACCELERATOR_LINES
+ 0
+
+
+ embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE
+ 0
+
+
+ embeddedsw.CMacro.FLUSHDA_SUPPORTED
+
+
+
+ embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT
+ 0
+
+
+ embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT
+ 1
+
+
+ embeddedsw.CMacro.HARDWARE_MULX_PRESENT
+ 0
+
+
+ embeddedsw.CMacro.HAS_DEBUG_CORE
+ 1
+
+
+ embeddedsw.CMacro.HAS_DEBUG_STUB
+
+
+
+ embeddedsw.CMacro.HAS_EXTRA_EXCEPTION_INFO
+
+
+
+ embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+
+
+
+ embeddedsw.CMacro.HAS_JMPI_INSTRUCTION
+
+
+
+ embeddedsw.CMacro.ICACHE_LINE_SIZE
+ 32
+
+
+ embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2
+ 5
+
+
+ embeddedsw.CMacro.ICACHE_SIZE
+ 4096
+
+
+ embeddedsw.CMacro.INITDA_SUPPORTED
+
+
+
+ embeddedsw.CMacro.INST_ADDR_WIDTH
+ 19
+
+
+ embeddedsw.CMacro.NUM_OF_SHADOW_REG_SETS
+ 0
+
+
+ embeddedsw.CMacro.OCI_VERSION
+ 1
+
+
+ embeddedsw.CMacro.RESET_ADDR
+ 0x00020000
+
+
+ embeddedsw.configuration.DataCacheVictimBufImpl
+ ram
+
+
+ embeddedsw.configuration.HDLSimCachesCleared
+ 1
+
+
+ embeddedsw.configuration.breakOffset
+ 32
+
+
+ embeddedsw.configuration.breakSlave
+ nios2_gen2.debug_mem_slave
+
+
+ embeddedsw.configuration.cpuArchitecture
+ Nios II
+
+
+ embeddedsw.configuration.exceptionOffset
+ 32
+
+
+ embeddedsw.configuration.exceptionSlave
+ onchip_memory2_0.s1
+
+
+ embeddedsw.configuration.resetOffset
+ 0
+
+
+ embeddedsw.configuration.resetSlave
+ onchip_memory2_0.s1
+
+
+ embeddedsw.dts.compatible
+ altr,nios2-1.1
+
+
+ embeddedsw.dts.group
+ cpu
+
+
+ embeddedsw.dts.name
+ nios2
+
+
+ embeddedsw.dts.params.altr,exception-addr
+ 0x00020020
+
+
+ embeddedsw.dts.params.altr,has-initda
+ 1
+
+
+ embeddedsw.dts.params.altr,has-mul
+ 1
+
+
+ embeddedsw.dts.params.altr,implementation
+ "fast"
+
+
+ embeddedsw.dts.params.altr,reset-addr
+ 0x00020000
+
+
+ embeddedsw.dts.params.clock-frequency
+ 50000000u
+
+
+ embeddedsw.dts.params.dcache-line-size
+ 32
+
+
+ embeddedsw.dts.params.dcache-size
+ 2048
+
+
+ embeddedsw.dts.params.icache-line-size
+ 32
+
+
+ embeddedsw.dts.params.icache-size
+ 4096
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ true
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
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+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 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HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 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+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 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+
+
+ java.lang.String
+ clk1
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset
+ Input
+ 1
+ reset
+
+
+ reset_req
+ Input
+ 1
+ reset_req
+
+
+
+
+
+
+ embeddedsw.CMacro.CAS_LATENCY
+ 3
+
+
+ embeddedsw.CMacro.CONTENTS_INFO
+
+
+
+ embeddedsw.CMacro.INIT_NOP_DELAY
+ 0.0
+
+
+ embeddedsw.CMacro.INIT_REFRESH_COMMANDS
+ 2
+
+
+ embeddedsw.CMacro.IS_INITIALIZED
+ 1
+
+
+ embeddedsw.CMacro.POWERUP_DELAY
+ 100.0
+
+
+ embeddedsw.CMacro.REFRESH_PERIOD
+ 15.625
+
+
+ embeddedsw.CMacro.REGISTER_DATA_IN
+ 1
+
+
+ embeddedsw.CMacro.SDRAM_ADDR_WIDTH
+ 25
+
+
+ embeddedsw.CMacro.SDRAM_BANK_WIDTH
+ 2
+
+
+ embeddedsw.CMacro.SDRAM_COL_WIDTH
+ 10
+
+
+ embeddedsw.CMacro.SDRAM_DATA_WIDTH
+ 16
+
+
+ embeddedsw.CMacro.SDRAM_NUM_BANKS
+ 4
+
+
+ embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS
+ 1
+
+
+ embeddedsw.CMacro.SDRAM_ROW_WIDTH
+ 13
+
+
+ embeddedsw.CMacro.SHARED_DATA
+ 0
+
+
+ embeddedsw.CMacro.SIM_MODEL_BASE
+ 1
+
+
+ embeddedsw.CMacro.STARVATION_INDICATOR
+ 0
+
+
+ embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE
+ ""
+
+
+ embeddedsw.CMacro.T_AC
+ 5.5
+
+
+ embeddedsw.CMacro.T_MRD
+ 3
+
+
+ embeddedsw.CMacro.T_RCD
+ 20.0
+
+
+ embeddedsw.CMacro.T_RFC
+ 70.0
+
+
+ embeddedsw.CMacro.T_RP
+ 20.0
+
+
+ embeddedsw.CMacro.T_WR
+ 14.0
+
+
+ embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR
+ SIM_DIR
+
+
+ embeddedsw.memoryInfo.GENERATE_DAT_SYM
+ 1
+
+
+ embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH
+ 16
+
+
+ postgeneration.simulation.init_file.param_name
+ INIT_FILE
+
+
+ postgeneration.simulation.init_file.param_owner
+ wire
+
+
+ postgeneration.simulation.init_file.type
+ MEM_INIT
+
+
+ testbench.partner.map.clk
+ my_partner.clk
+
+
+ testbench.partner.map.wire
+ my_partner.conduit
+
+
+ testbench.partner.my_partner.class
+ altera_sdram_partner_module
+
+
+ testbench.partner.my_partner.parameter.CAS_LATENCY
+ 3
+
+
+ testbench.partner.my_partner.parameter.CONTR_NAME
+ Qsys_sdram
+
+
+ testbench.partner.my_partner.parameter.SDRAM_BANK_WIDTH
+ 2
+
+
+ testbench.partner.my_partner.parameter.SDRAM_COL_WIDTH
+ 10
+
+
+ testbench.partner.my_partner.parameter.SDRAM_DATA_WIDTH
+ 16
+
+
+ testbench.partner.my_partner.parameter.SDRAM_NUM_CHIPSELECTS
+ 1
+
+
+ testbench.partner.my_partner.parameter.SDRAM_ROW_WIDTH
+ 13
+
+
+ double
+ 5.5
+ false
+ true
+ true
+ true
+
+
+ double
+ 20.0
+ false
+ true
+ true
+ true
+
+
+ double
+ 70.0
+ false
+ true
+ true
+ true
+
+
+ double
+ 20.0
+ false
+ true
+ true
+ true
+
+
+ double
+ 14.0
+ false
+ true
+ true
+ true
+
+
+ int
+ 3
+ false
+ true
+ true
+ true
+
+
+ int
+ 10
+ false
+ true
+ true
+ true
+
+
+ int
+ 16
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ int
+ 2
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ single_Micron_MT48LC4M32B2_7_chip
+ false
+ true
+ false
+ true
+
+
+ int
+ 4
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ double
+ 100.0
+ false
+ true
+ true
+ true
+
+
+ double
+ 15.625
+ false
+ true
+ true
+ true
+
+
+ int
+ 13
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ false
+ true
+
+
+ long
+ 3
+ false
+ true
+ false
+ true
+
+
+ double
+ 0.0
+ false
+ true
+ false
+ true
+
+
+ boolean
+ true
+ false
+ true
+ false
+ true
+
+
+ long
+ 100000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ java.lang.String
+ Qsys_sdram
+ false
+ true
+ false
+ true
+ UNIQUE_ID
+
+
+ long
+ 67108864
+ true
+ true
+ false
+ true
+
+
+ int
+ 25
+ true
+ true
+ false
+ true
+
+
+ int
+ 2
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 100000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 1
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 67108864
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ true
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 7
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ az_addr
+ Input
+ 25
+ address
+
+
+ az_be_n
+ Input
+ 2
+ byteenable_n
+
+
+ az_cs
+ Input
+ 1
+ chipselect
+
+
+ az_data
+ Input
+ 16
+ writedata
+
+
+ az_rd_n
+ Input
+ 1
+ read_n
+
+
+ az_wr_n
+ Input
+ 1
+ write_n
+
+
+ za_data
+ Output
+ 16
+ readdata
+
+
+ za_valid
+ Output
+ 1
+ readdatavalid
+
+
+ za_waitrequest
+ Output
+ 1
+ waitrequest
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ zs_addr
+ Output
+ 13
+ export
+
+
+ zs_ba
+ Output
+ 2
+ export
+
+
+ zs_cas_n
+ Output
+ 1
+ export
+
+
+ zs_cke
+ Output
+ 1
+ export
+
+
+ zs_cs_n
+ Output
+ 1
+ export
+
+
+ zs_dq
+ Bidir
+ 16
+ export
+
+
+ zs_dqm
+ Output
+ 2
+ export
+
+
+ zs_ras_n
+ Output
+ 1
+ export
+
+
+ zs_we_n
+ Output
+ 1
+ export
+
+
+
+
+
+
+ embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER
+ 0
+
+
+ embeddedsw.CMacro.CAPTURE
+ 0
+
+
+ embeddedsw.CMacro.DATA_WIDTH
+ 10
+
+
+ embeddedsw.CMacro.DO_TEST_BENCH_WIRING
+ 0
+
+
+ embeddedsw.CMacro.DRIVEN_SIM_VALUE
+ 0
+
+
+ embeddedsw.CMacro.EDGE_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.FREQ
+ 50000000
+
+
+ embeddedsw.CMacro.HAS_IN
+ 1
+
+
+ embeddedsw.CMacro.HAS_OUT
+ 0
+
+
+ embeddedsw.CMacro.HAS_TRI
+ 0
+
+
+ embeddedsw.CMacro.IRQ_TYPE
+ NONE
+
+
+ embeddedsw.CMacro.RESET_VALUE
+ 0
+
+
+ embeddedsw.dts.compatible
+ altr,pio-1.0
+
+
+ embeddedsw.dts.group
+ gpio
+
+
+ embeddedsw.dts.name
+ pio
+
+
+ embeddedsw.dts.params.altr,gpio-bank-width
+ 10
+
+
+ embeddedsw.dts.params.resetvalue
+ 0
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ Input
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ RISING
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ LEVEL
+ false
+ false
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ long
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 10
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ NONE
+ true
+ true
+ false
+ true
+
+
+ boolean
+ false
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 4
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ address
+ Input
+ 2
+ address
+
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ conduit
+ false
+
+ in_port
+ Input
+ 10
+ export
+
+
+
+
+
+
+ embeddedsw.CMacro.ID
+ 0
+
+
+ embeddedsw.CMacro.TIMESTAMP
+ 1621008007
+
+
+ embeddedsw.dts.compatible
+ altr,sysid-1.0
+
+
+ embeddedsw.dts.group
+ sysid
+
+
+ embeddedsw.dts.name
+ sysid
+
+
+ embeddedsw.dts.params.id
+ 0
+
+
+ embeddedsw.dts.params.timestamp
+ 1621008007
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1621008007
+ true
+ false
+ false
+ true
+ GENERATION_ID
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clock
+ false
+
+ clock
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isMemoryDevice
+ false
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ false
+
+
+ embeddedsw.configuration.isPrintableDevice
+ false
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ DYNAMIC
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 8
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ readdata
+ Output
+ 32
+ readdata
+
+
+ address
+ Input
+ 1
+ address
+
+
+
+
+
+
+ embeddedsw.CMacro.ALWAYS_RUN
+ 0
+
+
+ embeddedsw.CMacro.COUNTER_SIZE
+ 32
+
+
+ embeddedsw.CMacro.FIXED_PERIOD
+ 0
+
+
+ embeddedsw.CMacro.FREQ
+ 50000000
+
+
+ embeddedsw.CMacro.LOAD_VALUE
+ 49999
+
+
+ embeddedsw.CMacro.MULT
+ 0.001
+
+
+ embeddedsw.CMacro.PERIOD
+ 1
+
+
+ embeddedsw.CMacro.PERIOD_UNITS
+ ms
+
+
+ embeddedsw.CMacro.RESET_OUTPUT
+ 0
+
+
+ embeddedsw.CMacro.SNAPSHOT
+ 1
+
+
+ embeddedsw.CMacro.TICKS_PER_SEC
+ 1000
+
+
+ embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT
+ 0
+
+
+ embeddedsw.dts.compatible
+ altr,timer-1.0
+
+
+ embeddedsw.dts.group
+ timer
+
+
+ embeddedsw.dts.name
+ timer
+
+
+ embeddedsw.dts.params.clock-frequency
+ 50000000
+
+
+ embeddedsw.dts.vendor
+ altr
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 32
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ MSEC
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ boolean
+ true
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ long
+ 50000000
+ false
+ true
+ false
+ true
+ CLOCK_RATE
+ clk
+
+
+ int
+ 2
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ FULL_FEATURED
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ ms
+ true
+ true
+ false
+ true
+
+
+ double
+ 0.001
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ 49999
+ true
+ true
+ false
+ true
+
+
+ double
+ 0.001
+ true
+ true
+ false
+ true
+
+
+ double
+ 1000.0
+ true
+ true
+ false
+ true
+
+
+ int
+ 3
+ true
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.Boolean
+ true
+ true
+ true
+ false
+ true
+
+
+ java.lang.Long
+ 50000000
+ true
+ true
+ false
+ true
+
+ clock
+ false
+
+ clk
+ Input
+ 1
+ clk
+
+
+
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.reset.Reset$Edges
+ DEASSERT
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ reset
+ false
+
+ reset_n
+ Input
+ 1
+ reset_n
+
+
+
+
+
+ embeddedsw.configuration.isFlash
+ 0
+
+
+ embeddedsw.configuration.isMemoryDevice
+ 0
+
+
+ embeddedsw.configuration.isNonVolatileStorage
+ 0
+
+
+ embeddedsw.configuration.isPrintableDevice
+ 0
+
+
+ embeddedsw.configuration.isTimerDevice
+ 1
+
+
+ com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment
+ NATIVE
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 8
+ true
+ true
+ false
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ true
+ true
+
+
+ int
+ 8
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+
+ false
+ true
+ false
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.EAddrBurstUnits
+ WORDS
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ java.math.BigInteger
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 0
+ false
+ false
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ int
+ 1
+ false
+ true
+ false
+ true
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.avalon.TimingUnits
+ Cycles
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ boolean
+ false
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ false
+ true
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ avalon
+ false
+
+ address
+ Input
+ 3
+ address
+
+
+ writedata
+ Input
+ 16
+ writedata
+
+
+ readdata
+ Output
+ 16
+ readdata
+
+
+ chipselect
+ Input
+ 1
+ chipselect
+
+
+ write_n
+ Input
+ 1
+ write_n
+
+
+
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+ timer.s1
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ clk
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ reset
+ false
+ true
+ false
+ true
+
+
+ java.lang.Integer
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.entityinterfaces.IConnectionPoint
+
+ false
+ true
+ true
+ true
+
+
+ com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme
+ NONE
+ false
+ true
+ false
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ interrupt
+ false
+
+ irq
+ Output
+ 1
+ irq
+
+
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x000410e8
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ jtag_uart
+ avalon_jtag_slave
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00041060
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ i2c_opencores_mipi
+ avalon_slave_0
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00041040
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ i2c_opencores_camera
+ avalon_slave_0
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x000410e0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ sysid_qsys
+ control_slave
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00040800
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ nios2_gen2
+ debug_mem_slave
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00041020
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ TERASIC_AUTO_FOCUS_0
+ mm_ctrl
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x000410d0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ altpll_0
+ pll_slave
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00020000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ onchip_memory2_0
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00041000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ timer
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x000410c0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ led
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x000410b0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ sw
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x000410a0
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ key
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00041090
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ mipi_reset_n
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00041080
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ mipi_pwdn_n
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00042000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ data_master
+ EEE_IMGPROC_0
+ s1
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00040800
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ instruction_master
+ nios2_gen2
+ debug_mem_slave
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x00020000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ instruction_master
+ onchip_memory2_0
+ s1
+
+
+
+ int
+ 50
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x04000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ alt_vip_vfb_0
+ read_master
+ sdram
+ s1
+
+
+
+ int
+ 30
+ false
+ true
+ true
+ true
+
+
+ java.math.BigInteger
+ 0x04000000
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ alt_vip_vfb_0
+ write_master
+ sdram
+ s1
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ TERASIC_CAMERA_0
+ avalon_streaming_source
+ alt_vip_vfb_0
+ din
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ EEE_IMGPROC_0
+ avalon_streaming_source
+ alt_vip_itc_0
+ din
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ TERASIC_AUTO_FOCUS_0
+ dout
+ EEE_IMGPROC_0
+ avalon_streaming_sink
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ alt_vip_vfb_0
+ dout
+ TERASIC_AUTO_FOCUS_0
+ din
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ altpll_0
+ c2
+ sdram
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ altpll_0
+ c2
+ TERASIC_AUTO_FOCUS_0
+ clock
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ altpll_0
+ c2
+ alt_vip_vfb_0
+ clock
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ altpll_0
+ c2
+ EEE_IMGPROC_0
+ clock
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ altpll_0
+ c2
+ TERASIC_CAMERA_0
+ clock_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ altpll_0
+ c2
+ alt_vip_itc_0
+ is_clk_rst
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ jtag_uart
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ sysid_qsys
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ timer
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ led
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ sw
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ key
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ mipi_reset_n
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ mipi_pwdn_n
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ nios2_gen2
+ clk
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ onchip_memory2_0
+ clk1
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ i2c_opencores_mipi
+ clock
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ i2c_opencores_camera
+ clock
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk
+ altpll_0
+ inclk_interface
+
+
+
+ int
+ 0
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ irq
+ i2c_opencores_mipi
+ interrupt_sender
+
+
+
+ int
+ 1
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ irq
+ i2c_opencores_camera
+ interrupt_sender
+
+
+
+ int
+ 2
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ irq
+ jtag_uart
+ irq
+
+
+
+ int
+ 3
+ false
+ true
+ true
+ true
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ irq
+ timer
+ irq
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ i2c_opencores_mipi
+ clock_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ i2c_opencores_camera
+ clock_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ TERASIC_CAMERA_0
+ clock_reset_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ altpll_0
+ inclk_interface_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ alt_vip_itc_0
+ is_clk_rst_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ sdram
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ nios2_gen2
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ alt_vip_vfb_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ jtag_uart
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ key
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ led
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ mipi_pwdn_n
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ mipi_reset_n
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ sw
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ sysid_qsys
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ timer
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ TERASIC_AUTO_FOCUS_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ EEE_IMGPROC_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ clk_50
+ clk_reset
+ onchip_memory2_0
+ reset1
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ i2c_opencores_mipi
+ clock_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ i2c_opencores_camera
+ clock_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ TERASIC_CAMERA_0
+ clock_reset_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ alt_vip_itc_0
+ is_clk_rst_reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ jtag_uart
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ sysid_qsys
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ timer
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ led
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ sw
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ key
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ mipi_reset_n
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ mipi_pwdn_n
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ nios2_gen2
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ sdram
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ alt_vip_vfb_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ TERASIC_AUTO_FOCUS_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ EEE_IMGPROC_0
+ reset
+
+
+
+ java.lang.String
+ UNKNOWN
+ false
+ true
+ true
+ true
+
+
+ boolean
+ false
+ false
+ true
+ true
+ true
+
+ nios2_gen2
+ debug_reset_request
+ onchip_memory2_0
+ reset1
+
+
+ 1
+ EEE_IMGPROC
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ EEE_IMGPROC
+ 1.0
+
+
+ 19
+ clock_sink
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Clock Input
+ 16.1
+
+
+ 19
+ reset_sink
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Reset Input
+ 16.1
+
+
+ 4
+ avalon_streaming_sink
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Avalon Streaming Sink
+ 16.1
+
+
+ 4
+ avalon_streaming_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Avalon Streaming Source
+ 16.1
+
+
+ 16
+ avalon_slave
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Avalon Memory Mapped Slave
+ 16.1
+
+
+ 14
+ conduit_end
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Conduit
+ 16.1
+
+
+ 1
+ TERASIC_AUTO_FOCUS
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ TERASIC_AUTO_FOCUS
+ 1.0
+
+
+ 1
+ TERASIC_CAMERA
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ TERASIC_CAMERA
+ 1.0
+
+
+ 1
+ alt_vip_itc
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Clocked Video Output
+ 14.0
+
+
+ 1
+ alt_vip_vfb
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Frame Buffer
+ 13.1
+
+
+ 4
+ avalon_master
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Avalon Memory Mapped Master
+ 16.1
+
+
+ 1
+ altpll
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Avalon ALTPLL
+ 16.1
+
+
+ 5
+ clock_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Clock Output
+ 16.1
+
+
+ 1
+ clock_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Clock Source
+ 16.1
+
+
+ 1
+ clock_sink
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Clock Input
+ 16.1
+
+
+ 1
+ reset_sink
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Reset Input
+ 16.1
+
+
+ 1
+ clock_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Clock Output
+ 16.1
+
+
+ 1
+ reset_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Reset Output
+ 16.1
+
+
+ 2
+ i2c_opencores
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ I2C Master (opencores.org)
+ 12.0
+
+
+ 4
+ interrupt_sender
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Interrupt Sender
+ 16.1
+
+
+ 1
+ altera_avalon_jtag_uart
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ JTAG UART
+ 16.1
+
+
+ 5
+ altera_avalon_pio
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ PIO (Parallel I/O)
+ 16.1
+
+
+ 1
+ altera_nios2_gen2
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Nios II Processor
+ 16.1
+
+
+ 1
+ interrupt_receiver
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Interrupt Receiver
+ 16.1
+
+
+ 1
+ reset_source
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Reset Output
+ 16.1
+
+
+ 1
+ nios_custom_instruction_master
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IMutableConnectionPoint
+ Custom Instruction Master
+ 16.1
+
+
+ 1
+ altera_avalon_onchip_memory2
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ On-Chip Memory (RAM or ROM)
+ 16.1
+
+
+ 1
+ altera_avalon_new_sdram_controller
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ SDRAM Controller
+ 16.1
+
+
+ 1
+ altera_avalon_sysid_qsys
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ System ID Peripheral
+ 16.1
+
+
+ 1
+ altera_avalon_timer
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IModule
+ Interval Timer
+ 16.1
+
+
+ 19
+ avalon
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IConnection
+ Avalon Memory Mapped Connection
+ 16.1
+
+
+ 4
+ avalon_streaming
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IConnection
+ Avalon Streaming Connection
+ 16.1
+
+
+ 19
+ clock
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IConnection
+ Clock Connection
+ 16.1
+
+
+ 4
+ interrupt
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IConnection
+ Interrupt Connection
+ 16.1
+
+
+ 37
+ reset
+ com.altera.entityinterfaces.IElementClass
+ com.altera.entityinterfaces.IConnection
+ Reset Connection
+ 16.1
+
+ 16.1 196
+
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf
new file mode 100644
index 0000000..9a0cbd5
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf
@@ -0,0 +1,431 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other
+applicable license agreement, including, without limitation,
+that your use is for the sole purpose of programming logic
+devices manufactured by Altera and sold by Altera or its
+authorized distributors. Please refer to the applicable
+agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 576 1072)
+ (text "Qsys" (rect 273 -1 295 11)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 1056 20 1068)(font "Arial" ))
+ (port
+ (pt 0 72)
+ (input)
+ (text "alt_vip_itc_0_clocked_video_vid_clk" (rect 0 0 147 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_clk" (rect 4 61 214 72)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 240 72)(line_width 1))
+ )
+ (port
+ (pt 0 240)
+ (input)
+ (text "altpll_0_areset_conduit_export" (rect 0 0 120 12)(font "Arial" (font_size 8)))
+ (text "altpll_0_areset_conduit_export" (rect 4 229 184 240)(font "Arial" (font_size 8)))
+ (line (pt 0 240)(pt 240 240)(line_width 1))
+ )
+ (port
+ (pt 0 320)
+ (input)
+ (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
+ (text "clk_clk" (rect 4 309 46 320)(font "Arial" (font_size 8)))
+ (line (pt 0 320)(pt 240 320)(line_width 1))
+ )
+ (port
+ (pt 0 360)
+ (input)
+ (text "eee_imgproc_0_conduit_mode_new_signal" (rect 0 0 172 12)(font "Arial" (font_size 8)))
+ (text "eee_imgproc_0_conduit_mode_new_signal" (rect 4 349 226 360)(font "Arial" (font_size 8)))
+ (line (pt 0 360)(pt 240 360)(line_width 1))
+ )
+ (port
+ (pt 0 512)
+ (input)
+ (text "key_external_connection_export[1..0]" (rect 0 0 148 12)(font "Arial" (font_size 8)))
+ (text "key_external_connection_export[1..0]" (rect 4 501 220 512)(font "Arial" (font_size 8)))
+ (line (pt 0 512)(pt 240 512)(line_width 3))
+ )
+ (port
+ (pt 0 672)
+ (input)
+ (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
+ (text "reset_reset_n" (rect 4 661 82 672)(font "Arial" (font_size 8)))
+ (line (pt 0 672)(pt 240 672)(line_width 1))
+ )
+ (port
+ (pt 0 880)
+ (input)
+ (text "sw_external_connection_export[9..0]" (rect 0 0 145 12)(font "Arial" (font_size 8)))
+ (text "sw_external_connection_export[9..0]" (rect 4 869 214 880)(font "Arial" (font_size 8)))
+ (line (pt 0 880)(pt 240 880)(line_width 3))
+ )
+ (port
+ (pt 0 936)
+ (input)
+ (text "terasic_auto_focus_0_conduit_clk50" (rect 0 0 146 12)(font "Arial" (font_size 8)))
+ (text "terasic_auto_focus_0_conduit_clk50" (rect 4 925 208 936)(font "Arial" (font_size 8)))
+ (line (pt 0 936)(pt 240 936)(line_width 1))
+ )
+ (port
+ (pt 0 992)
+ (input)
+ (text "terasic_camera_0_conduit_end_D[11..0]" (rect 0 0 161 12)(font "Arial" (font_size 8)))
+ (text "terasic_camera_0_conduit_end_D[11..0]" (rect 4 981 226 992)(font "Arial" (font_size 8)))
+ (line (pt 0 992)(pt 240 992)(line_width 3))
+ )
+ (port
+ (pt 0 1008)
+ (input)
+ (text "terasic_camera_0_conduit_end_FVAL" (rect 0 0 160 12)(font "Arial" (font_size 8)))
+ (text "terasic_camera_0_conduit_end_FVAL" (rect 4 997 202 1008)(font "Arial" (font_size 8)))
+ (line (pt 0 1008)(pt 240 1008)(line_width 1))
+ )
+ (port
+ (pt 0 1024)
+ (input)
+ (text "terasic_camera_0_conduit_end_LVAL" (rect 0 0 160 12)(font "Arial" (font_size 8)))
+ (text "terasic_camera_0_conduit_end_LVAL" (rect 4 1013 202 1024)(font "Arial" (font_size 8)))
+ (line (pt 0 1024)(pt 240 1024)(line_width 1))
+ )
+ (port
+ (pt 0 1040)
+ (input)
+ (text "terasic_camera_0_conduit_end_PIXCLK" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+ (text "terasic_camera_0_conduit_end_PIXCLK" (rect 4 1029 214 1040)(font "Arial" (font_size 8)))
+ (line (pt 0 1040)(pt 240 1040)(line_width 1))
+ )
+ (port
+ (pt 0 88)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_vid_data[23..0]" (rect 0 0 178 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_data[23..0]" (rect 4 77 262 88)(font "Arial" (font_size 8)))
+ (line (pt 0 88)(pt 240 88)(line_width 3))
+ )
+ (port
+ (pt 0 104)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_underflow" (rect 0 0 156 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_underflow" (rect 4 93 226 104)(font "Arial" (font_size 8)))
+ (line (pt 0 104)(pt 240 104)(line_width 1))
+ )
+ (port
+ (pt 0 120)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_vid_datavalid" (rect 0 0 171 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_datavalid" (rect 4 109 250 120)(font "Arial" (font_size 8)))
+ (line (pt 0 120)(pt 240 120)(line_width 1))
+ )
+ (port
+ (pt 0 136)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_vid_v_sync" (rect 0 0 168 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_v_sync" (rect 4 125 232 136)(font "Arial" (font_size 8)))
+ (line (pt 0 136)(pt 240 136)(line_width 1))
+ )
+ (port
+ (pt 0 152)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_vid_h_sync" (rect 0 0 167 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_h_sync" (rect 4 141 232 152)(font "Arial" (font_size 8)))
+ (line (pt 0 152)(pt 240 152)(line_width 1))
+ )
+ (port
+ (pt 0 168)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_vid_f" (rect 0 0 140 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_f" (rect 4 157 202 168)(font "Arial" (font_size 8)))
+ (line (pt 0 168)(pt 240 168)(line_width 1))
+ )
+ (port
+ (pt 0 184)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_vid_h" (rect 0 0 141 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_h" (rect 4 173 202 184)(font "Arial" (font_size 8)))
+ (line (pt 0 184)(pt 240 184)(line_width 1))
+ )
+ (port
+ (pt 0 200)
+ (output)
+ (text "alt_vip_itc_0_clocked_video_vid_v" (rect 0 0 142 12)(font "Arial" (font_size 8)))
+ (text "alt_vip_itc_0_clocked_video_vid_v" (rect 4 189 202 200)(font "Arial" (font_size 8)))
+ (line (pt 0 200)(pt 240 200)(line_width 1))
+ )
+ (port
+ (pt 0 280)
+ (output)
+ (text "altpll_0_locked_conduit_export" (rect 0 0 120 12)(font "Arial" (font_size 8)))
+ (text "altpll_0_locked_conduit_export" (rect 4 269 184 280)(font "Arial" (font_size 8)))
+ (line (pt 0 280)(pt 240 280)(line_width 1))
+ )
+ (port
+ (pt 576 72)
+ (output)
+ (text "clk_sdram_clk" (rect 0 0 59 12)(font "Arial" (font_size 8)))
+ (text "clk_sdram_clk" (rect 504 61 582 72)(font "Arial" (font_size 8)))
+ (line (pt 576 72)(pt 336 72)(line_width 1))
+ )
+ (port
+ (pt 576 112)
+ (output)
+ (text "clk_vga_clk" (rect 0 0 48 12)(font "Arial" (font_size 8)))
+ (text "clk_vga_clk" (rect 516 101 582 112)(font "Arial" (font_size 8)))
+ (line (pt 576 112)(pt 336 112)(line_width 1))
+ )
+ (port
+ (pt 576 152)
+ (output)
+ (text "d8m_xclkin_clk" (rect 0 0 61 12)(font "Arial" (font_size 8)))
+ (text "d8m_xclkin_clk" (rect 500 141 584 152)(font "Arial" (font_size 8)))
+ (line (pt 576 152)(pt 336 152)(line_width 1))
+ )
+ (port
+ (pt 0 552)
+ (output)
+ (text "led_external_connection_export[9..0]" (rect 0 0 145 12)(font "Arial" (font_size 8)))
+ (text "led_external_connection_export[9..0]" (rect 4 541 220 552)(font "Arial" (font_size 8)))
+ (line (pt 0 552)(pt 240 552)(line_width 3))
+ )
+ (port
+ (pt 0 592)
+ (output)
+ (text "mipi_pwdn_n_external_connection_export" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+ (text "mipi_pwdn_n_external_connection_export" (rect 4 581 232 592)(font "Arial" (font_size 8)))
+ (line (pt 0 592)(pt 240 592)(line_width 1))
+ )
+ (port
+ (pt 0 632)
+ (output)
+ (text "mipi_reset_n_external_connection_export" (rect 0 0 166 12)(font "Arial" (font_size 8)))
+ (text "mipi_reset_n_external_connection_export" (rect 4 621 238 632)(font "Arial" (font_size 8)))
+ (line (pt 0 632)(pt 240 632)(line_width 1))
+ )
+ (port
+ (pt 0 712)
+ (output)
+ (text "sdram_wire_addr[12..0]" (rect 0 0 94 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_addr[12..0]" (rect 4 701 136 712)(font "Arial" (font_size 8)))
+ (line (pt 0 712)(pt 240 712)(line_width 3))
+ )
+ (port
+ (pt 0 728)
+ (output)
+ (text "sdram_wire_ba[1..0]" (rect 0 0 81 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_ba[1..0]" (rect 4 717 118 728)(font "Arial" (font_size 8)))
+ (line (pt 0 728)(pt 240 728)(line_width 3))
+ )
+ (port
+ (pt 0 744)
+ (output)
+ (text "sdram_wire_cas_n" (rect 0 0 77 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_cas_n" (rect 4 733 100 744)(font "Arial" (font_size 8)))
+ (line (pt 0 744)(pt 240 744)(line_width 1))
+ )
+ (port
+ (pt 0 760)
+ (output)
+ (text "sdram_wire_cke" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_cke" (rect 4 749 88 760)(font "Arial" (font_size 8)))
+ (line (pt 0 760)(pt 240 760)(line_width 1))
+ )
+ (port
+ (pt 0 776)
+ (output)
+ (text "sdram_wire_cs_n" (rect 0 0 73 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_cs_n" (rect 4 765 94 776)(font "Arial" (font_size 8)))
+ (line (pt 0 776)(pt 240 776)(line_width 1))
+ )
+ (port
+ (pt 0 808)
+ (output)
+ (text "sdram_wire_dqm[1..0]" (rect 0 0 89 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_dqm[1..0]" (rect 4 797 124 808)(font "Arial" (font_size 8)))
+ (line (pt 0 808)(pt 240 808)(line_width 3))
+ )
+ (port
+ (pt 0 824)
+ (output)
+ (text "sdram_wire_ras_n" (rect 0 0 76 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_ras_n" (rect 4 813 100 824)(font "Arial" (font_size 8)))
+ (line (pt 0 824)(pt 240 824)(line_width 1))
+ )
+ (port
+ (pt 0 840)
+ (output)
+ (text "sdram_wire_we_n" (rect 0 0 74 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_we_n" (rect 4 829 94 840)(font "Arial" (font_size 8)))
+ (line (pt 0 840)(pt 240 840)(line_width 1))
+ )
+ (port
+ (pt 0 400)
+ (bidir)
+ (text "i2c_opencores_camera_export_scl_pad_io" (rect 0 0 173 12)(font "Arial" (font_size 8)))
+ (text "i2c_opencores_camera_export_scl_pad_io" (rect 4 389 232 400)(font "Arial" (font_size 8)))
+ (line (pt 0 400)(pt 240 400)(line_width 1))
+ )
+ (port
+ (pt 0 416)
+ (bidir)
+ (text "i2c_opencores_camera_export_sda_pad_io" (rect 0 0 177 12)(font "Arial" (font_size 8)))
+ (text "i2c_opencores_camera_export_sda_pad_io" (rect 4 405 232 416)(font "Arial" (font_size 8)))
+ (line (pt 0 416)(pt 240 416)(line_width 1))
+ )
+ (port
+ (pt 0 456)
+ (bidir)
+ (text "i2c_opencores_mipi_export_scl_pad_io" (rect 0 0 158 12)(font "Arial" (font_size 8)))
+ (text "i2c_opencores_mipi_export_scl_pad_io" (rect 4 445 220 456)(font "Arial" (font_size 8)))
+ (line (pt 0 456)(pt 240 456)(line_width 1))
+ )
+ (port
+ (pt 0 472)
+ (bidir)
+ (text "i2c_opencores_mipi_export_sda_pad_io" (rect 0 0 161 12)(font "Arial" (font_size 8)))
+ (text "i2c_opencores_mipi_export_sda_pad_io" (rect 4 461 220 472)(font "Arial" (font_size 8)))
+ (line (pt 0 472)(pt 240 472)(line_width 1))
+ )
+ (port
+ (pt 0 792)
+ (bidir)
+ (text "sdram_wire_dq[15..0]" (rect 0 0 86 12)(font "Arial" (font_size 8)))
+ (text "sdram_wire_dq[15..0]" (rect 4 781 124 792)(font "Arial" (font_size 8)))
+ (line (pt 0 792)(pt 240 792)(line_width 3))
+ )
+ (port
+ (pt 0 920)
+ (bidir)
+ (text "terasic_auto_focus_0_conduit_vcm_i2c_sda" (rect 0 0 181 12)(font "Arial" (font_size 8)))
+ (text "terasic_auto_focus_0_conduit_vcm_i2c_sda" (rect 4 909 244 920)(font "Arial" (font_size 8)))
+ (line (pt 0 920)(pt 240 920)(line_width 1))
+ )
+ (port
+ (pt 0 952)
+ (bidir)
+ (text "terasic_auto_focus_0_conduit_vcm_i2c_scl" (rect 0 0 178 12)(font "Arial" (font_size 8)))
+ (text "terasic_auto_focus_0_conduit_vcm_i2c_scl" (rect 4 941 244 952)(font "Arial" (font_size 8)))
+ (line (pt 0 952)(pt 240 952)(line_width 1))
+ )
+ (drawing
+ (text "alt_vip_itc_0_clocked_video" (rect 78 43 318 99)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "vid_clk" (rect 245 67 532 144)(font "Arial" (color 0 0 0)))
+ (text "vid_data" (rect 245 83 538 176)(font "Arial" (color 0 0 0)))
+ (text "underflow" (rect 245 99 544 208)(font "Arial" (color 0 0 0)))
+ (text "vid_datavalid" (rect 245 115 568 240)(font "Arial" (color 0 0 0)))
+ (text "vid_v_sync" (rect 245 131 550 272)(font "Arial" (color 0 0 0)))
+ (text "vid_h_sync" (rect 245 147 550 304)(font "Arial" (color 0 0 0)))
+ (text "vid_f" (rect 245 163 520 336)(font "Arial" (color 0 0 0)))
+ (text "vid_h" (rect 245 179 520 368)(font "Arial" (color 0 0 0)))
+ (text "vid_v" (rect 245 195 520 400)(font "Arial" (color 0 0 0)))
+ (text "altpll_0_areset_conduit" (rect 105 211 348 435)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "export" (rect 245 235 526 480)(font "Arial" (color 0 0 0)))
+ (text "altpll_0_locked_conduit" (rect 105 251 348 515)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "export" (rect 245 275 526 560)(font "Arial" (color 0 0 0)))
+ (text "clk" (rect 225 291 468 595)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 245 315 508 640)(font "Arial" (color 0 0 0)))
+ (text "clk_sdram" (rect 337 43 728 99)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 321 67 660 144)(font "Arial" (color 0 0 0)))
+ (text "clk_vga" (rect 337 83 716 179)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 321 107 660 224)(font "Arial" (color 0 0 0)))
+ (text "d8m_xclkin" (rect 337 123 734 259)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "clk" (rect 321 147 660 304)(font "Arial" (color 0 0 0)))
+ (text "eee_imgproc_0_conduit_mode" (rect 62 331 280 675)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "new_signal" (rect 245 355 550 720)(font "Arial" (color 0 0 0)))
+ (text "i2c_opencores_camera_export" (rect 62 371 286 755)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "scl_pad_io" (rect 245 395 550 800)(font "Arial" (color 0 0 0)))
+ (text "sda_pad_io" (rect 245 411 550 832)(font "Arial" (color 0 0 0)))
+ (text "i2c_opencores_mipi_export" (rect 81 427 312 867)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "scl_pad_io" (rect 245 451 550 912)(font "Arial" (color 0 0 0)))
+ (text "sda_pad_io" (rect 245 467 550 944)(font "Arial" (color 0 0 0)))
+ (text "key_external_connection" (rect 98 483 334 979)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "export" (rect 245 507 526 1024)(font "Arial" (color 0 0 0)))
+ (text "led_external_connection" (rect 101 523 340 1059)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "export" (rect 245 547 526 1104)(font "Arial" (color 0 0 0)))
+ (text "mipi_pwdn_n_external_connection" (rect 40 563 266 1139)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "export" (rect 245 587 526 1184)(font "Arial" (color 0 0 0)))
+ (text "mipi_reset_n_external_connection" (rect 41 603 274 1219)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "export" (rect 245 627 526 1264)(font "Arial" (color 0 0 0)))
+ (text "reset" (rect 211 643 452 1299)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "reset_n" (rect 245 667 532 1344)(font "Arial" (color 0 0 0)))
+ (text "sdram_wire" (rect 171 683 402 1379)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "addr" (rect 245 707 514 1424)(font "Arial" (color 0 0 0)))
+ (text "ba" (rect 245 723 502 1456)(font "Arial" (color 0 0 0)))
+ (text "cas_n" (rect 245 739 520 1488)(font "Arial" (color 0 0 0)))
+ (text "cke" (rect 245 755 508 1520)(font "Arial" (color 0 0 0)))
+ (text "cs_n" (rect 245 771 514 1552)(font "Arial" (color 0 0 0)))
+ (text "dq" (rect 245 787 502 1584)(font "Arial" (color 0 0 0)))
+ (text "dqm" (rect 245 803 508 1616)(font "Arial" (color 0 0 0)))
+ (text "ras_n" (rect 245 819 520 1648)(font "Arial" (color 0 0 0)))
+ (text "we_n" (rect 245 835 514 1680)(font "Arial" (color 0 0 0)))
+ (text "sw_external_connection" (rect 101 851 334 1715)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "export" (rect 245 875 526 1760)(font "Arial" (color 0 0 0)))
+ (text "terasic_auto_focus_0_conduit" (rect 65 891 298 1795)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "vcm_i2c_sda" (rect 245 915 556 1840)(font "Arial" (color 0 0 0)))
+ (text "clk50" (rect 245 931 520 1872)(font "Arial" (color 0 0 0)))
+ (text "vcm_i2c_scl" (rect 245 947 556 1904)(font "Arial" (color 0 0 0)))
+ (text "terasic_camera_0_conduit_end" (rect 58 963 284 1939)(font "Arial" (color 128 0 0)(font_size 9)))
+ (text "D" (rect 245 987 496 1984)(font "Arial" (color 0 0 0)))
+ (text "FVAL" (rect 245 1003 514 2016)(font "Arial" (color 0 0 0)))
+ (text "LVAL" (rect 245 1019 514 2048)(font "Arial" (color 0 0 0)))
+ (text "PIXCLK" (rect 245 1035 526 2080)(font "Arial" (color 0 0 0)))
+ (text " system " (rect 541 1056 1130 2122)(font "Arial" ))
+ (line (pt 240 32)(pt 336 32)(line_width 1))
+ (line (pt 336 32)(pt 336 1056)(line_width 1))
+ (line (pt 240 1056)(pt 336 1056)(line_width 1))
+ (line (pt 240 32)(pt 240 1056)(line_width 1))
+ (line (pt 241 52)(pt 241 204)(line_width 1))
+ (line (pt 242 52)(pt 242 204)(line_width 1))
+ (line (pt 241 220)(pt 241 244)(line_width 1))
+ (line (pt 242 220)(pt 242 244)(line_width 1))
+ (line (pt 241 260)(pt 241 284)(line_width 1))
+ (line (pt 242 260)(pt 242 284)(line_width 1))
+ (line (pt 241 300)(pt 241 324)(line_width 1))
+ (line (pt 242 300)(pt 242 324)(line_width 1))
+ (line (pt 335 52)(pt 335 76)(line_width 1))
+ (line (pt 334 52)(pt 334 76)(line_width 1))
+ (line (pt 335 92)(pt 335 116)(line_width 1))
+ (line (pt 334 92)(pt 334 116)(line_width 1))
+ (line (pt 335 132)(pt 335 156)(line_width 1))
+ (line (pt 334 132)(pt 334 156)(line_width 1))
+ (line (pt 241 340)(pt 241 364)(line_width 1))
+ (line (pt 242 340)(pt 242 364)(line_width 1))
+ (line (pt 241 380)(pt 241 420)(line_width 1))
+ (line (pt 242 380)(pt 242 420)(line_width 1))
+ (line (pt 241 436)(pt 241 476)(line_width 1))
+ (line (pt 242 436)(pt 242 476)(line_width 1))
+ (line (pt 241 492)(pt 241 516)(line_width 1))
+ (line (pt 242 492)(pt 242 516)(line_width 1))
+ (line (pt 241 532)(pt 241 556)(line_width 1))
+ (line (pt 242 532)(pt 242 556)(line_width 1))
+ (line (pt 241 572)(pt 241 596)(line_width 1))
+ (line (pt 242 572)(pt 242 596)(line_width 1))
+ (line (pt 241 612)(pt 241 636)(line_width 1))
+ (line (pt 242 612)(pt 242 636)(line_width 1))
+ (line (pt 241 652)(pt 241 676)(line_width 1))
+ (line (pt 242 652)(pt 242 676)(line_width 1))
+ (line (pt 241 692)(pt 241 844)(line_width 1))
+ (line (pt 242 692)(pt 242 844)(line_width 1))
+ (line (pt 241 860)(pt 241 884)(line_width 1))
+ (line (pt 242 860)(pt 242 884)(line_width 1))
+ (line (pt 241 900)(pt 241 956)(line_width 1))
+ (line (pt 242 900)(pt 242 956)(line_width 1))
+ (line (pt 241 972)(pt 241 1044)(line_width 1))
+ (line (pt 242 972)(pt 242 1044)(line_width 1))
+ (line (pt 0 0)(pt 576 0)(line_width 1))
+ (line (pt 576 0)(pt 576 1072)(line_width 1))
+ (line (pt 0 1072)(pt 576 1072)(line_width 1))
+ (line (pt 0 0)(pt 0 1072)(line_width 1))
+ )
+)
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp
new file mode 100644
index 0000000..6375a52
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.cmp
@@ -0,0 +1,47 @@
+ component Qsys is
+ port (
+ alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
+ alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(23 downto 0); -- vid_data
+ alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
+ alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
+ alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
+ alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
+ alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
+ alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
+ alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
+ altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
+ altpll_0_locked_conduit_export : out std_logic; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ clk_sdram_clk : out std_logic; -- clk
+ clk_vga_clk : out std_logic; -- clk
+ d8m_xclkin_clk : out std_logic; -- clk
+ eee_imgproc_0_conduit_mode_new_signal : in std_logic := 'X'; -- new_signal
+ i2c_opencores_camera_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
+ i2c_opencores_camera_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
+ i2c_opencores_mipi_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
+ i2c_opencores_mipi_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
+ key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
+ led_external_connection_export : out std_logic_vector(9 downto 0); -- export
+ mipi_pwdn_n_external_connection_export : out std_logic; -- export
+ mipi_reset_n_external_connection_export : out std_logic; -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
+ sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
+ sdram_wire_cas_n : out std_logic; -- cas_n
+ sdram_wire_cke : out std_logic; -- cke
+ sdram_wire_cs_n : out std_logic; -- cs_n
+ sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
+ sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
+ sdram_wire_ras_n : out std_logic; -- ras_n
+ sdram_wire_we_n : out std_logic; -- we_n
+ sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
+ terasic_auto_focus_0_conduit_vcm_i2c_sda : inout std_logic := 'X'; -- vcm_i2c_sda
+ terasic_auto_focus_0_conduit_clk50 : in std_logic := 'X'; -- clk50
+ terasic_auto_focus_0_conduit_vcm_i2c_scl : inout std_logic := 'X'; -- vcm_i2c_scl
+ terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
+ terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
+ terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
+ terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X' -- PIXCLK
+ );
+ end component Qsys;
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html
new file mode 100644
index 0000000..d039e8c
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html
@@ -0,0 +1,5416 @@
+
+
+
+
+ datasheet for Qsys
+
+
+
+
+
+
+ 2021.03.30.09:18:34 |
+ Datasheet |
+
+
+
+ Overview
+
+
+
+
+ clk_50 |
+ Qsys |
+
+
+ |
+
+
+
+
+
+
+ Memory Map
+
+
+ |
+
+ alt_vip_vfb_0
+
+ |
+
+ nios2_gen2
+
+ |
+
+
+ read_master |
+ write_master |
+ data_master |
+ instruction_master |
+
+
+
+ TERASIC_AUTO_FOCUS_0
+
+ |
+ |
+ |
+ |
+ |
+
+
+ mm_ctrl |
+ |
+ |
+ 0x00041020 |
+ |
+
+
+
+ altpll_0
+
+ |
+ |
+ |
+ |
+ |
+
+
+ pll_slave |
+ |
+ |
+ 0x000410d0 |
+ |
+
+
+
+ i2c_opencores_camera
+
+ |
+ |
+ |
+ |
+ |
+
+
+ avalon_slave_0 |
+ |
+ |
+ 0x00041040 |
+ |
+
+
+
+ i2c_opencores_mipi
+
+ |
+ |
+ |
+ |
+ |
+
+
+ avalon_slave_0 |
+ |
+ |
+ 0x00041060 |
+ |
+
+
+
+ jtag_uart
+
+ |
+ |
+ |
+ |
+ |
+
+
+ avalon_jtag_slave |
+ |
+ |
+ 0x000410e8 |
+ |
+
+
+
+ key
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ |
+ |
+ 0x000410a0 |
+ |
+
+
+
+ led
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ |
+ |
+ 0x000410c0 |
+ |
+
+
+
+ mipi_pwdn_n
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ |
+ |
+ 0x00041080 |
+ |
+
+
+
+ mipi_reset_n
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ |
+ |
+ 0x00041090 |
+ |
+
+
+
+ nios2_gen2
+
+ |
+ |
+ |
+ |
+ |
+
+
+ debug_mem_slave |
+ |
+ |
+ 0x00040800 |
+ 0x00040800 |
+
+
+
+ onchip_memory2_0
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ |
+ |
+ 0x00020000 |
+ 0x00020000 |
+
+
+
+ sdram
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ 0x04000000 |
+ 0x04000000 |
+ |
+ |
+
+
+
+ sw
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ |
+ |
+ 0x000410b0 |
+ |
+
+
+
+ sysid_qsys
+
+ |
+ |
+ |
+ |
+ |
+
+
+ control_slave |
+ |
+ |
+ 0x000410e0 |
+ |
+
+
+
+ timer
+
+ |
+ |
+ |
+ |
+ |
+
+
+ s1 |
+ |
+ |
+ 0x00041000 |
+ |
+
+
+
+
+
+
TERASIC_AUTO_FOCUS_0
TERASIC_AUTO_FOCUS v1.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ TERASIC_AUTO_FOCUS_0 |
+
+
+ mm_ctrl |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ alt_vip_vfb_0
+ |
+ dout |
+
+
+ din |
+
+
+ |
+
+
+
+ altpll_0
+ |
+ c2 |
+
+
+ clock |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk_reset |
+
+
+ reset |
+
+
+ |
+ |
+ dout |
+
+ alt_vip_itc_0
+ |
+
+
+ |
+ |
+ din |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ VIDEO_W |
+ 640 |
+
+
+ VIDEO_H |
+ 480 |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
TERASIC_CAMERA_0
TERASIC_CAMERA v1.0
+
+
+
+
+
+ altpll_0
+ |
+ c2 |
+ TERASIC_CAMERA_0 |
+
+
+ clock_reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk_reset |
+
+
+ clock_reset_reset |
+
+
+ |
+
+
+
+ nios2_gen2
+ |
+ debug_reset_request |
+
+
+ clock_reset_reset |
+
+
+ |
+ |
+ avalon_streaming_source |
+
+ alt_vip_vfb_0
+ |
+
+
+ |
+ |
+ din |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ VIDEO_W |
+ 640 |
+
+
+ VIDEO_H |
+ 480 |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
alt_vip_itc_0
alt_vip_itc v14.0
+
+
+
+
+
+ TERASIC_AUTO_FOCUS_0
+ |
+ dout |
+ alt_vip_itc_0 |
+
+
+ din |
+
+
+ |
+
+
+
+ altpll_0
+ |
+ c2 |
+
+
+ is_clk_rst |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk_reset |
+
+
+ is_clk_rst_reset |
+
+
+ |
+
+
+
+ nios2_gen2
+ |
+ debug_reset_request |
+
+
+ is_clk_rst_reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ FAMILY |
+ MAX10FPGA |
+
+
+ NUMBER_OF_COLOUR_PLANES |
+ 3 |
+
+
+ COLOUR_PLANES_ARE_IN_PARALLEL |
+ 1 |
+
+
+ BPS |
+ 8 |
+
+
+ INTERLACED |
+ 0 |
+
+
+ H_ACTIVE_PIXELS |
+ 640 |
+
+
+ V_ACTIVE_LINES |
+ 480 |
+
+
+ ACCEPT_COLOURS_IN_SEQ |
+ 0 |
+
+
+ FIFO_DEPTH |
+ 640 |
+
+
+ CLOCKS_ARE_SAME |
+ 0 |
+
+
+ USE_CONTROL |
+ 0 |
+
+
+ NO_OF_MODES |
+ 1 |
+
+
+ THRESHOLD |
+ 639 |
+
+
+ STD_WIDTH |
+ 1 |
+
+
+ GENERATE_SYNC |
+ 0 |
+
+
+ USE_EMBEDDED_SYNCS |
+ 0 |
+
+
+ AP_LINE |
+ 0 |
+
+
+ V_BLANK |
+ 0 |
+
+
+ H_BLANK |
+ 0 |
+
+
+ H_SYNC_LENGTH |
+ 96 |
+
+
+ H_FRONT_PORCH |
+ 16 |
+
+
+ H_BACK_PORCH |
+ 48 |
+
+
+ V_SYNC_LENGTH |
+ 2 |
+
+
+ V_FRONT_PORCH |
+ 10 |
+
+
+ V_BACK_PORCH |
+ 33 |
+
+
+ F_RISING_EDGE |
+ 0 |
+
+
+ F_FALLING_EDGE |
+ 0 |
+
+
+ FIELD0_V_RISING_EDGE |
+ 0 |
+
+
+ FIELD0_V_BLANK |
+ 0 |
+
+
+ FIELD0_V_SYNC_LENGTH |
+ 0 |
+
+
+ FIELD0_V_FRONT_PORCH |
+ 0 |
+
+
+ FIELD0_V_BACK_PORCH |
+ 0 |
+
+
+ ANC_LINE |
+ 0 |
+
+
+ FIELD0_ANC_LINE |
+ 0 |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
alt_vip_vfb_0
alt_vip_vfb v13.1
+
+
+
+
+
+ TERASIC_CAMERA_0
+ |
+ avalon_streaming_source |
+ alt_vip_vfb_0 |
+
+
+ din |
+
+
+ |
+
+
+
+ altpll_0
+ |
+ c2 |
+
+
+ clock |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk_reset |
+
+
+ reset |
+
+
+ |
+
+
+
+ nios2_gen2
+ |
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+ |
+ read_master |
+
+ sdram
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ write_master |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+
+
+ |
+ |
+ dout |
+
+ TERASIC_AUTO_FOCUS_0
+ |
+
+
+ |
+ |
+ din |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ AUTO_WRITE_MASTER_CLOCKS_SAME |
+ 0 |
+
+
+ AUTO_WRITE_MASTER_INTERRUPT_USED_MASK |
+ 0 |
+
+
+ AUTO_READ_MASTER_MAX_READ_LATENCY |
+ 2 |
+
+
+ AUTO_READ_MASTER_CLOCKS_SAME |
+ 0 |
+
+
+ AUTO_WRITE_MASTER_MAX_READ_LATENCY |
+ 2 |
+
+
+ AUTO_DEVICE_FAMILY |
+ MAX10FPGA |
+
+
+ AUTO_WRITER_CONTROL_CLOCKS_SAME |
+ 0 |
+
+
+ AUTO_READ_MASTER_INTERRUPT_USED_MASK |
+ 0 |
+
+
+ AUTO_READER_CONTROL_CLOCKS_SAME |
+ 0 |
+
+
+ AUTO_READ_MASTER_NEED_ADDR_WIDTH |
+ 27 |
+
+
+ AUTO_WRITE_MASTER_NEED_ADDR_WIDTH |
+ 27 |
+
+
+ PARAMETERISATION |
+ <frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>640</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>480</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>false</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>true</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>true</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>false</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>1024</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>4</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>1024</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>4</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>false</VFB_DROP_INVALID_FIELDS></frameBufferParams> |
+
+
+ deviceFamily |
+ MAX 10 |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
altpll_0
altpll v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ altpll_0 |
+
+
+ pll_slave |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ inclk_interface |
+
+
+ clk_reset |
+
+
+ inclk_interface_reset |
+
+
+ |
+ |
+ c2 |
+
+ sdram
+ |
+
+
+ |
+ |
+ clk |
+
+
+ |
+
+
+ |
+ |
+ c2 |
+
+ TERASIC_AUTO_FOCUS_0
+ |
+
+
+ |
+ |
+ clock |
+
+
+ |
+
+
+ |
+ |
+ c2 |
+
+ alt_vip_vfb_0
+ |
+
+
+ |
+ |
+ clock |
+
+
+ |
+
+
+ |
+ |
+ c2 |
+
+ TERASIC_CAMERA_0
+ |
+
+
+ |
+ |
+ clock_reset |
+
+
+ |
+
+
+ |
+ |
+ c2 |
+
+ alt_vip_itc_0
+ |
+
+
+ |
+ |
+ is_clk_rst |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ HIDDEN_CUSTOM_ELABORATION |
+ altpll_avalon_elaboration |
+
+
+ HIDDEN_CUSTOM_POST_EDIT |
+ altpll_avalon_post_edit |
+
+
+ INTENDED_DEVICE_FAMILY |
+ MAX 10 |
+
+
+ WIDTH_CLOCK |
+ 5 |
+
+
+ WIDTH_PHASECOUNTERSELECT |
+ |
+
+
+ PRIMARY_CLOCK |
+ |
+
+
+ INCLK0_INPUT_FREQUENCY |
+ 20000 |
+
+
+ INCLK1_INPUT_FREQUENCY |
+ |
+
+
+ OPERATION_MODE |
+ NORMAL |
+
+
+ PLL_TYPE |
+ AUTO |
+
+
+ QUALIFY_CONF_DONE |
+ |
+
+
+ COMPENSATE_CLOCK |
+ CLK0 |
+
+
+ SCAN_CHAIN |
+ |
+
+
+ GATE_LOCK_SIGNAL |
+ |
+
+
+ GATE_LOCK_COUNTER |
+ |
+
+
+ LOCK_HIGH |
+ |
+
+
+ LOCK_LOW |
+ |
+
+
+ VALID_LOCK_MULTIPLIER |
+ |
+
+
+ INVALID_LOCK_MULTIPLIER |
+ |
+
+
+ SWITCH_OVER_ON_LOSSCLK |
+ |
+
+
+ SWITCH_OVER_ON_GATED_LOCK |
+ |
+
+
+ ENABLE_SWITCH_OVER_COUNTER |
+ |
+
+
+ SKIP_VCO |
+ |
+
+
+ SWITCH_OVER_COUNTER |
+ |
+
+
+ SWITCH_OVER_TYPE |
+ |
+
+
+ FEEDBACK_SOURCE |
+ |
+
+
+ BANDWIDTH |
+ |
+
+
+ BANDWIDTH_TYPE |
+ AUTO |
+
+
+ SPREAD_FREQUENCY |
+ |
+
+
+ DOWN_SPREAD |
+ |
+
+
+ SELF_RESET_ON_GATED_LOSS_LOCK |
+ |
+
+
+ SELF_RESET_ON_LOSS_LOCK |
+ |
+
+
+ CLK0_MULTIPLY_BY |
+ 2 |
+
+
+ CLK1_MULTIPLY_BY |
+ 2 |
+
+
+ CLK2_MULTIPLY_BY |
+ 2 |
+
+
+ CLK3_MULTIPLY_BY |
+ 1 |
+
+
+ CLK4_MULTIPLY_BY |
+ 2 |
+
+
+ CLK5_MULTIPLY_BY |
+ |
+
+
+ CLK6_MULTIPLY_BY |
+ |
+
+
+ CLK7_MULTIPLY_BY |
+ |
+
+
+ CLK8_MULTIPLY_BY |
+ |
+
+
+ CLK9_MULTIPLY_BY |
+ |
+
+
+ EXTCLK0_MULTIPLY_BY |
+ |
+
+
+ EXTCLK1_MULTIPLY_BY |
+ |
+
+
+ EXTCLK2_MULTIPLY_BY |
+ |
+
+
+ EXTCLK3_MULTIPLY_BY |
+ |
+
+
+ CLK0_DIVIDE_BY |
+ 1 |
+
+
+ CLK1_DIVIDE_BY |
+ 1 |
+
+
+ CLK2_DIVIDE_BY |
+ 1 |
+
+
+ CLK3_DIVIDE_BY |
+ 2 |
+
+
+ CLK4_DIVIDE_BY |
+ 5 |
+
+
+ CLK5_DIVIDE_BY |
+ |
+
+
+ CLK6_DIVIDE_BY |
+ |
+
+
+ CLK7_DIVIDE_BY |
+ |
+
+
+ CLK8_DIVIDE_BY |
+ |
+
+
+ CLK9_DIVIDE_BY |
+ |
+
+
+ EXTCLK0_DIVIDE_BY |
+ |
+
+
+ EXTCLK1_DIVIDE_BY |
+ |
+
+
+ EXTCLK2_DIVIDE_BY |
+ |
+
+
+ EXTCLK3_DIVIDE_BY |
+ |
+
+
+ CLK0_PHASE_SHIFT |
+ 0 |
+
+
+ CLK1_PHASE_SHIFT |
+ 7500 |
+
+
+ CLK2_PHASE_SHIFT |
+ 0 |
+
+
+ CLK3_PHASE_SHIFT |
+ 0 |
+
+
+ CLK4_PHASE_SHIFT |
+ 0 |
+
+
+ CLK5_PHASE_SHIFT |
+ |
+
+
+ CLK6_PHASE_SHIFT |
+ |
+
+
+ CLK7_PHASE_SHIFT |
+ |
+
+
+ CLK8_PHASE_SHIFT |
+ |
+
+
+ CLK9_PHASE_SHIFT |
+ |
+
+
+ EXTCLK0_PHASE_SHIFT |
+ |
+
+
+ EXTCLK1_PHASE_SHIFT |
+ |
+
+
+ EXTCLK2_PHASE_SHIFT |
+ |
+
+
+ EXTCLK3_PHASE_SHIFT |
+ |
+
+
+ CLK0_DUTY_CYCLE |
+ 50 |
+
+
+ CLK1_DUTY_CYCLE |
+ 50 |
+
+
+ CLK2_DUTY_CYCLE |
+ 50 |
+
+
+ CLK3_DUTY_CYCLE |
+ 50 |
+
+
+ CLK4_DUTY_CYCLE |
+ 50 |
+
+
+ CLK5_DUTY_CYCLE |
+ |
+
+
+ CLK6_DUTY_CYCLE |
+ |
+
+
+ CLK7_DUTY_CYCLE |
+ |
+
+
+ CLK8_DUTY_CYCLE |
+ |
+
+
+ CLK9_DUTY_CYCLE |
+ |
+
+
+ EXTCLK0_DUTY_CYCLE |
+ |
+
+
+ EXTCLK1_DUTY_CYCLE |
+ |
+
+
+ EXTCLK2_DUTY_CYCLE |
+ |
+
+
+ EXTCLK3_DUTY_CYCLE |
+ |
+
+
+ PORT_clkena0 |
+ PORT_UNUSED |
+
+
+ PORT_clkena1 |
+ PORT_UNUSED |
+
+
+ PORT_clkena2 |
+ PORT_UNUSED |
+
+
+ PORT_clkena3 |
+ PORT_UNUSED |
+
+
+ PORT_clkena4 |
+ PORT_UNUSED |
+
+
+ PORT_clkena5 |
+ PORT_UNUSED |
+
+
+ PORT_extclkena0 |
+ |
+
+
+ PORT_extclkena1 |
+ |
+
+
+ PORT_extclkena2 |
+ |
+
+
+ PORT_extclkena3 |
+ |
+
+
+ PORT_extclk0 |
+ PORT_UNUSED |
+
+
+ PORT_extclk1 |
+ PORT_UNUSED |
+
+
+ PORT_extclk2 |
+ PORT_UNUSED |
+
+
+ PORT_extclk3 |
+ PORT_UNUSED |
+
+
+ PORT_CLKBAD0 |
+ PORT_UNUSED |
+
+
+ PORT_CLKBAD1 |
+ PORT_UNUSED |
+
+
+ PORT_clk0 |
+ PORT_USED |
+
+
+ PORT_clk1 |
+ PORT_USED |
+
+
+ PORT_clk2 |
+ PORT_USED |
+
+
+ PORT_clk3 |
+ PORT_USED |
+
+
+ PORT_clk4 |
+ PORT_USED |
+
+
+ PORT_clk5 |
+ PORT_UNUSED |
+
+
+ PORT_clk6 |
+ |
+
+
+ PORT_clk7 |
+ |
+
+
+ PORT_clk8 |
+ |
+
+
+ PORT_clk9 |
+ |
+
+
+ PORT_SCANDATA |
+ PORT_UNUSED |
+
+
+ PORT_SCANDATAOUT |
+ PORT_UNUSED |
+
+
+ PORT_SCANDONE |
+ PORT_UNUSED |
+
+
+ PORT_SCLKOUT1 |
+ |
+
+
+ PORT_SCLKOUT0 |
+ |
+
+
+ PORT_ACTIVECLOCK |
+ PORT_UNUSED |
+
+
+ PORT_CLKLOSS |
+ PORT_UNUSED |
+
+
+ PORT_INCLK1 |
+ PORT_UNUSED |
+
+
+ PORT_INCLK0 |
+ PORT_USED |
+
+
+ PORT_FBIN |
+ PORT_UNUSED |
+
+
+ PORT_PLLENA |
+ PORT_UNUSED |
+
+
+ PORT_CLKSWITCH |
+ PORT_UNUSED |
+
+
+ PORT_ARESET |
+ PORT_USED |
+
+
+ PORT_PFDENA |
+ PORT_UNUSED |
+
+
+ PORT_SCANCLK |
+ PORT_UNUSED |
+
+
+ PORT_SCANACLR |
+ PORT_UNUSED |
+
+
+ PORT_SCANREAD |
+ PORT_UNUSED |
+
+
+ PORT_SCANWRITE |
+ PORT_UNUSED |
+
+
+ PORT_ENABLE0 |
+ |
+
+
+ PORT_ENABLE1 |
+ |
+
+
+ PORT_LOCKED |
+ PORT_USED |
+
+
+ PORT_CONFIGUPDATE |
+ PORT_UNUSED |
+
+
+ PORT_FBOUT |
+ |
+
+
+ PORT_PHASEDONE |
+ PORT_UNUSED |
+
+
+ PORT_PHASESTEP |
+ PORT_UNUSED |
+
+
+ PORT_PHASEUPDOWN |
+ PORT_UNUSED |
+
+
+ PORT_SCANCLKENA |
+ PORT_UNUSED |
+
+
+ PORT_PHASECOUNTERSELECT |
+ PORT_UNUSED |
+
+
+ PORT_VCOOVERRANGE |
+ |
+
+
+ PORT_VCOUNDERRANGE |
+ |
+
+
+ DPA_MULTIPLY_BY |
+ |
+
+
+ DPA_DIVIDE_BY |
+ |
+
+
+ DPA_DIVIDER |
+ |
+
+
+ VCO_MULTIPLY_BY |
+ |
+
+
+ VCO_DIVIDE_BY |
+ |
+
+
+ SCLKOUT0_PHASE_SHIFT |
+ |
+
+
+ SCLKOUT1_PHASE_SHIFT |
+ |
+
+
+ VCO_FREQUENCY_CONTROL |
+ |
+
+
+ VCO_PHASE_SHIFT_STEP |
+ |
+
+
+ USING_FBMIMICBIDIR_PORT |
+ |
+
+
+ SCAN_CHAIN_MIF_FILE |
+ |
+
+
+ AVALON_USE_SEPARATE_SYSCLK |
+ NO |
+
+
+ HIDDEN_CONSTANTS |
+ CT#CLK2_DIVIDE_BY 1 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 5 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 2 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 7500 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 2 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_USED |
+
+
+ HIDDEN_PRIVATES |
+ PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 20.00000000 PT#OUTPUT_FREQ3 25.00000000 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 270.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 20.000000 PT#EFF_OUTPUT_FREQ_VALUE3 25.000000 PT#EFF_OUTPUT_FREQ_VALUE2 100.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1472001986172141.mif PT#ACTIVECLK_CHECK 0 |
+
+
+ HIDDEN_USED_PORTS |
+ UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used |
+
+
+ HIDDEN_IS_NUMERIC |
+ IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 |
+
+
+ HIDDEN_MF_PORTS |
+ MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 |
+
+
+ HIDDEN_IF_PORTS |
+ IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} |
+
+
+ HIDDEN_IS_FIRST_EDIT |
+ 0 |
+
+
+ AUTO_DEVICE_FAMILY |
+ MAX10FPGA |
+
+
+ AUTO_INCLK_INTERFACE_CLOCK_RATE |
+ 50000000 |
+
+
+ deviceFamily |
+ MAX 10 |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
clk_50
clock_source v16.0
+
+
+
+
+
+
+ Parameters
+
+
+ clockFrequency |
+ 50000000 |
+
+
+ clockFrequencyKnown |
+ true |
+
+
+ inputClockFrequency |
+ 0 |
+
+
+ resetSynchronousEdges |
+ NONE |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
i2c_opencores_camera
i2c_opencores v12.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ i2c_opencores_camera |
+
+
+ avalon_slave_0 |
+
+
+ irq |
+
+
+ interrupt_sender |
+
+
+ debug_reset_request |
+
+
+ clock_reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clock |
+
+
+ clk_reset |
+
+
+ clock_reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
i2c_opencores_mipi
i2c_opencores v12.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ i2c_opencores_mipi |
+
+
+ avalon_slave_0 |
+
+
+ irq |
+
+
+ interrupt_sender |
+
+
+ debug_reset_request |
+
+
+ clock_reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clock |
+
+
+ clk_reset |
+
+
+ clock_reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments(none) |
+
+
+
+
+
+
+
jtag_uart
altera_avalon_jtag_uart v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ jtag_uart |
+
+
+ avalon_jtag_slave |
+
+
+ irq |
+
+
+ irq |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ allowMultipleConnections |
+ false |
+
+
+ hubInstanceID |
+ 0 |
+
+
+ readBufferDepth |
+ 64 |
+
+
+ readIRQThreshold |
+ 8 |
+
+
+ simInputCharacterStream |
+ |
+
+
+ simInteractiveOptions |
+ NO_INTERACTIVE_WINDOWS |
+
+
+ useRegistersForReadBuffer |
+ false |
+
+
+ useRegistersForWriteBuffer |
+ false |
+
+
+ useRelativePathForSimFile |
+ false |
+
+
+ writeBufferDepth |
+ 64 |
+
+
+ writeIRQThreshold |
+ 8 |
+
+
+ clkFreq |
+ 50000000 |
+
+
+ avalonSpec |
+ 2.0 |
+
+
+ legacySignalAllow |
+ false |
+
+
+ enableInteractiveInput |
+ false |
+
+
+ enableInteractiveOutput |
+ false |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ READ_DEPTH |
+ 64 |
+
+
+ READ_THRESHOLD |
+ 8 |
+
+
+ WRITE_DEPTH |
+ 64 |
+
+
+ WRITE_THRESHOLD |
+ 8 |
+
+
+ |
+
+
+
+
+
+
+
key
altera_avalon_pio v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ key |
+
+
+ s1 |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ bitClearingEdgeCapReg |
+ false |
+
+
+ bitModifyingOutReg |
+ false |
+
+
+ captureEdge |
+ false |
+
+
+ direction |
+ Input |
+
+
+ edgeType |
+ RISING |
+
+
+ generateIRQ |
+ false |
+
+
+ irqType |
+ LEVEL |
+
+
+ resetValue |
+ 0 |
+
+
+ simDoTestBenchWiring |
+ false |
+
+
+ simDrivenValue |
+ 0 |
+
+
+ width |
+ 2 |
+
+
+ clockRate |
+ 50000000 |
+
+
+ derived_has_tri |
+ false |
+
+
+ derived_has_out |
+ false |
+
+
+ derived_has_in |
+ true |
+
+
+ derived_do_test_bench_wiring |
+ false |
+
+
+ derived_capture |
+ false |
+
+
+ derived_edge_type |
+ NONE |
+
+
+ derived_irq_type |
+ NONE |
+
+
+ derived_has_irq |
+ false |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ BIT_CLEARING_EDGE_REGISTER |
+ 0 |
+
+
+ BIT_MODIFYING_OUTPUT_REGISTER |
+ 0 |
+
+
+ CAPTURE |
+ 0 |
+
+
+ DATA_WIDTH |
+ 2 |
+
+
+ DO_TEST_BENCH_WIRING |
+ 0 |
+
+
+ DRIVEN_SIM_VALUE |
+ 0 |
+
+
+ EDGE_TYPE |
+ NONE |
+
+
+ FREQ |
+ 50000000 |
+
+
+ HAS_IN |
+ 1 |
+
+
+ HAS_OUT |
+ 0 |
+
+
+ HAS_TRI |
+ 0 |
+
+
+ IRQ_TYPE |
+ NONE |
+
+
+ RESET_VALUE |
+ 0 |
+
+
+ |
+
+
+
+
+
+
+
led
altera_avalon_pio v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ led |
+
+
+ s1 |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ bitClearingEdgeCapReg |
+ false |
+
+
+ bitModifyingOutReg |
+ false |
+
+
+ captureEdge |
+ false |
+
+
+ direction |
+ Output |
+
+
+ edgeType |
+ RISING |
+
+
+ generateIRQ |
+ false |
+
+
+ irqType |
+ LEVEL |
+
+
+ resetValue |
+ 0 |
+
+
+ simDoTestBenchWiring |
+ false |
+
+
+ simDrivenValue |
+ 0 |
+
+
+ width |
+ 10 |
+
+
+ clockRate |
+ 50000000 |
+
+
+ derived_has_tri |
+ false |
+
+
+ derived_has_out |
+ true |
+
+
+ derived_has_in |
+ false |
+
+
+ derived_do_test_bench_wiring |
+ false |
+
+
+ derived_capture |
+ false |
+
+
+ derived_edge_type |
+ NONE |
+
+
+ derived_irq_type |
+ NONE |
+
+
+ derived_has_irq |
+ false |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ BIT_CLEARING_EDGE_REGISTER |
+ 0 |
+
+
+ BIT_MODIFYING_OUTPUT_REGISTER |
+ 0 |
+
+
+ CAPTURE |
+ 0 |
+
+
+ DATA_WIDTH |
+ 10 |
+
+
+ DO_TEST_BENCH_WIRING |
+ 0 |
+
+
+ DRIVEN_SIM_VALUE |
+ 0 |
+
+
+ EDGE_TYPE |
+ NONE |
+
+
+ FREQ |
+ 50000000 |
+
+
+ HAS_IN |
+ 0 |
+
+
+ HAS_OUT |
+ 1 |
+
+
+ HAS_TRI |
+ 0 |
+
+
+ IRQ_TYPE |
+ NONE |
+
+
+ RESET_VALUE |
+ 0 |
+
+
+ |
+
+
+
+
+
+
+
mipi_pwdn_n
altera_avalon_pio v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ mipi_pwdn_n |
+
+
+ s1 |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ bitClearingEdgeCapReg |
+ false |
+
+
+ bitModifyingOutReg |
+ false |
+
+
+ captureEdge |
+ false |
+
+
+ direction |
+ Output |
+
+
+ edgeType |
+ RISING |
+
+
+ generateIRQ |
+ false |
+
+
+ irqType |
+ LEVEL |
+
+
+ resetValue |
+ 0 |
+
+
+ simDoTestBenchWiring |
+ false |
+
+
+ simDrivenValue |
+ 0 |
+
+
+ width |
+ 1 |
+
+
+ clockRate |
+ 50000000 |
+
+
+ derived_has_tri |
+ false |
+
+
+ derived_has_out |
+ true |
+
+
+ derived_has_in |
+ false |
+
+
+ derived_do_test_bench_wiring |
+ false |
+
+
+ derived_capture |
+ false |
+
+
+ derived_edge_type |
+ NONE |
+
+
+ derived_irq_type |
+ NONE |
+
+
+ derived_has_irq |
+ false |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ BIT_CLEARING_EDGE_REGISTER |
+ 0 |
+
+
+ BIT_MODIFYING_OUTPUT_REGISTER |
+ 0 |
+
+
+ CAPTURE |
+ 0 |
+
+
+ DATA_WIDTH |
+ 1 |
+
+
+ DO_TEST_BENCH_WIRING |
+ 0 |
+
+
+ DRIVEN_SIM_VALUE |
+ 0 |
+
+
+ EDGE_TYPE |
+ NONE |
+
+
+ FREQ |
+ 50000000 |
+
+
+ HAS_IN |
+ 0 |
+
+
+ HAS_OUT |
+ 1 |
+
+
+ HAS_TRI |
+ 0 |
+
+
+ IRQ_TYPE |
+ NONE |
+
+
+ RESET_VALUE |
+ 0 |
+
+
+ |
+
+
+
+
+
+
+
mipi_reset_n
altera_avalon_pio v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ mipi_reset_n |
+
+
+ s1 |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ bitClearingEdgeCapReg |
+ false |
+
+
+ bitModifyingOutReg |
+ false |
+
+
+ captureEdge |
+ false |
+
+
+ direction |
+ Output |
+
+
+ edgeType |
+ RISING |
+
+
+ generateIRQ |
+ false |
+
+
+ irqType |
+ LEVEL |
+
+
+ resetValue |
+ 0 |
+
+
+ simDoTestBenchWiring |
+ false |
+
+
+ simDrivenValue |
+ 0 |
+
+
+ width |
+ 1 |
+
+
+ clockRate |
+ 50000000 |
+
+
+ derived_has_tri |
+ false |
+
+
+ derived_has_out |
+ true |
+
+
+ derived_has_in |
+ false |
+
+
+ derived_do_test_bench_wiring |
+ false |
+
+
+ derived_capture |
+ false |
+
+
+ derived_edge_type |
+ NONE |
+
+
+ derived_irq_type |
+ NONE |
+
+
+ derived_has_irq |
+ false |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ BIT_CLEARING_EDGE_REGISTER |
+ 0 |
+
+
+ BIT_MODIFYING_OUTPUT_REGISTER |
+ 0 |
+
+
+ CAPTURE |
+ 0 |
+
+
+ DATA_WIDTH |
+ 1 |
+
+
+ DO_TEST_BENCH_WIRING |
+ 0 |
+
+
+ DRIVEN_SIM_VALUE |
+ 0 |
+
+
+ EDGE_TYPE |
+ NONE |
+
+
+ FREQ |
+ 50000000 |
+
+
+ HAS_IN |
+ 0 |
+
+
+ HAS_OUT |
+ 1 |
+
+
+ HAS_TRI |
+ 0 |
+
+
+ IRQ_TYPE |
+ NONE |
+
+
+ RESET_VALUE |
+ 0 |
+
+
+ |
+
+
+
+
+
+
+
nios2_gen2
altera_nios2_gen2 v16.0
+
+
+
+
+
+ clk_50
+ |
+ clk |
+ nios2_gen2 |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+ |
+ |
+ data_master |
+
+ jtag_uart
+ |
+
+
+ |
+ |
+ avalon_jtag_slave |
+
+
+ |
+ |
+ irq |
+
+
+ |
+ |
+ irq |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ i2c_opencores_mipi
+ |
+
+
+ |
+ |
+ avalon_slave_0 |
+
+
+ |
+ |
+ irq |
+
+
+ |
+ |
+ interrupt_sender |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ clock_reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ i2c_opencores_camera
+ |
+
+
+ |
+ |
+ avalon_slave_0 |
+
+
+ |
+ |
+ irq |
+
+
+ |
+ |
+ interrupt_sender |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ clock_reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ sysid_qsys
+ |
+
+
+ |
+ |
+ control_slave |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ TERASIC_AUTO_FOCUS_0
+ |
+
+
+ |
+ |
+ mm_ctrl |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ altpll_0
+ |
+
+
+ |
+ |
+ pll_slave |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ onchip_memory2_0
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ instruction_master |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset1 |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ timer
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ irq |
+
+
+ |
+ |
+ irq |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ led
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ sw
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ key
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ mipi_reset_n
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ data_master |
+
+ mipi_pwdn_n
+ |
+
+
+ |
+ |
+ s1 |
+
+
+ |
+ |
+ debug_reset_request |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ debug_reset_request |
+
+ TERASIC_CAMERA_0
+ |
+
+
+ |
+ |
+ clock_reset_reset |
+
+
+ |
+
+
+ |
+ |
+ debug_reset_request |
+
+ alt_vip_itc_0
+ |
+
+
+ |
+ |
+ is_clk_rst_reset |
+
+
+ |
+
+
+ |
+ |
+ debug_reset_request |
+
+ sdram
+ |
+
+
+ |
+ |
+ reset |
+
+
+ |
+
+
+ |
+ |
+ debug_reset_request |
+
+ alt_vip_vfb_0
+ |
+
+
+ |
+ |
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ tmr_enabled |
+ false |
+
+
+ setting_disable_tmr_inj |
+ false |
+
+
+ setting_showUnpublishedSettings |
+ false |
+
+
+ setting_showInternalSettings |
+ false |
+
+
+ setting_preciseIllegalMemAccessException |
+ false |
+
+
+ setting_exportPCB |
+ false |
+
+
+ setting_exportdebuginfo |
+ false |
+
+
+ setting_clearXBitsLDNonBypass |
+ true |
+
+
+ setting_bigEndian |
+ false |
+
+
+ setting_export_large_RAMs |
+ false |
+
+
+ setting_asic_enabled |
+ false |
+
+
+ setting_asic_synopsys_translate_on_off |
+ false |
+
+
+ setting_asic_third_party_synthesis |
+ false |
+
+
+ setting_asic_add_scan_mode_input |
+ false |
+
+
+ setting_oci_version |
+ 1 |
+
+
+ setting_fast_register_read |
+ false |
+
+
+ setting_exportHostDebugPort |
+ false |
+
+
+ setting_oci_export_jtag_signals |
+ false |
+
+
+ setting_avalonDebugPortPresent |
+ false |
+
+
+ setting_alwaysEncrypt |
+ true |
+
+
+ io_regionbase |
+ 0 |
+
+
+ io_regionsize |
+ 0 |
+
+
+ setting_support31bitdcachebypass |
+ true |
+
+
+ setting_activateTrace |
+ false |
+
+
+ setting_allow_break_inst |
+ false |
+
+
+ setting_activateTestEndChecker |
+ false |
+
+
+ setting_ecc_sim_test_ports |
+ false |
+
+
+ setting_disableocitrace |
+ false |
+
+
+ setting_activateMonitors |
+ true |
+
+
+ setting_HDLSimCachesCleared |
+ true |
+
+
+ setting_HBreakTest |
+ false |
+
+
+ setting_breakslaveoveride |
+ false |
+
+
+ mpu_useLimit |
+ false |
+
+
+ mpu_enabled |
+ false |
+
+
+ mmu_enabled |
+ false |
+
+
+ mmu_autoAssignTlbPtrSz |
+ true |
+
+
+ cpuReset |
+ false |
+
+
+ resetrequest_enabled |
+ true |
+
+
+ setting_removeRAMinit |
+ false |
+
+
+ setting_tmr_output_disable |
+ false |
+
+
+ setting_shadowRegisterSets |
+ 0 |
+
+
+ mpu_numOfInstRegion |
+ 8 |
+
+
+ mpu_numOfDataRegion |
+ 8 |
+
+
+ mmu_TLBMissExcOffset |
+ 0 |
+
+
+ resetOffset |
+ 0 |
+
+
+ exceptionOffset |
+ 32 |
+
+
+ cpuID |
+ 0 |
+
+
+ breakOffset |
+ 32 |
+
+
+ userDefinedSettings |
+ |
+
+
+ tracefilename |
+ |
+
+
+ resetSlave |
+ onchip_memory2_0.s1 |
+
+
+ mmu_TLBMissExcSlave |
+ None |
+
+
+ exceptionSlave |
+ onchip_memory2_0.s1 |
+
+
+ breakSlave |
+ None |
+
+
+ setting_interruptControllerType |
+ Internal |
+
+
+ setting_branchpredictiontype |
+ Dynamic |
+
+
+ setting_bhtPtrSz |
+ 8 |
+
+
+ cpuArchRev |
+ 1 |
+
+
+ stratix_dspblock_shift_mul |
+ false |
+
+
+ shifterType |
+ fast_le_shift |
+
+
+ multiplierType |
+ mul_fast32 |
+
+
+ mul_shift_choice |
+ 0 |
+
+
+ mul_32_impl |
+ 2 |
+
+
+ mul_64_impl |
+ 0 |
+
+
+ shift_rot_impl |
+ 1 |
+
+
+ dividerType |
+ no_div |
+
+
+ mpu_minInstRegionSize |
+ 12 |
+
+
+ mpu_minDataRegionSize |
+ 12 |
+
+
+ mmu_uitlbNumEntries |
+ 4 |
+
+
+ mmu_udtlbNumEntries |
+ 6 |
+
+
+ mmu_tlbPtrSz |
+ 7 |
+
+
+ mmu_tlbNumWays |
+ 16 |
+
+
+ mmu_processIDNumBits |
+ 8 |
+
+
+ impl |
+ Fast |
+
+
+ icache_size |
+ 4096 |
+
+
+ fa_cache_line |
+ 2 |
+
+
+ fa_cache_linesize |
+ 0 |
+
+
+ icache_tagramBlockType |
+ Automatic |
+
+
+ icache_ramBlockType |
+ Automatic |
+
+
+ icache_numTCIM |
+ 0 |
+
+
+ icache_burstType |
+ None |
+
+
+ dcache_bursts |
+ false |
+
+
+ dcache_victim_buf_impl |
+ ram |
+
+
+ dcache_size |
+ 2048 |
+
+
+ dcache_tagramBlockType |
+ Automatic |
+
+
+ dcache_ramBlockType |
+ Automatic |
+
+
+ dcache_numTCDM |
+ 0 |
+
+
+ setting_exportvectors |
+ false |
+
+
+ setting_usedesignware |
+ false |
+
+
+ setting_ecc_present |
+ false |
+
+
+ setting_ic_ecc_present |
+ true |
+
+
+ setting_rf_ecc_present |
+ true |
+
+
+ setting_mmu_ecc_present |
+ true |
+
+
+ setting_dc_ecc_present |
+ true |
+
+
+ setting_itcm_ecc_present |
+ true |
+
+
+ setting_dtcm_ecc_present |
+ true |
+
+
+ regfile_ramBlockType |
+ Automatic |
+
+
+ ocimem_ramBlockType |
+ Automatic |
+
+
+ ocimem_ramInit |
+ false |
+
+
+ mmu_ramBlockType |
+ Automatic |
+
+
+ bht_ramBlockType |
+ Automatic |
+
+
+ cdx_enabled |
+ false |
+
+
+ mpx_enabled |
+ false |
+
+
+ debug_enabled |
+ true |
+
+
+ debug_triggerArming |
+ true |
+
+
+ debug_debugReqSignals |
+ false |
+
+
+ debug_assignJtagInstanceID |
+ false |
+
+
+ debug_jtagInstanceID |
+ 0 |
+
+
+ debug_OCIOnchipTrace |
+ _128 |
+
+
+ debug_hwbreakpoint |
+ 0 |
+
+
+ debug_datatrigger |
+ 0 |
+
+
+ debug_traceType |
+ none |
+
+
+ debug_traceStorage |
+ onchip_trace |
+
+
+ master_addr_map |
+ false |
+
+
+ instruction_master_paddr_base |
+ 0 |
+
+
+ instruction_master_paddr_size |
+ 0 |
+
+
+ flash_instruction_master_paddr_base |
+ 0 |
+
+
+ flash_instruction_master_paddr_size |
+ 0 |
+
+
+ data_master_paddr_base |
+ 0 |
+
+
+ data_master_paddr_size |
+ 0 |
+
+
+ tightly_coupled_instruction_master_0_paddr_base |
+ 0 |
+
+
+ tightly_coupled_instruction_master_0_paddr_size |
+ 0 |
+
+
+ tightly_coupled_instruction_master_1_paddr_base |
+ 0 |
+
+
+ tightly_coupled_instruction_master_1_paddr_size |
+ 0 |
+
+
+ tightly_coupled_instruction_master_2_paddr_base |
+ 0 |
+
+
+ tightly_coupled_instruction_master_2_paddr_size |
+ 0 |
+
+
+ tightly_coupled_instruction_master_3_paddr_base |
+ 0 |
+
+
+ tightly_coupled_instruction_master_3_paddr_size |
+ 0 |
+
+
+ tightly_coupled_data_master_0_paddr_base |
+ 0 |
+
+
+ tightly_coupled_data_master_0_paddr_size |
+ 0 |
+
+
+ tightly_coupled_data_master_1_paddr_base |
+ 0 |
+
+
+ tightly_coupled_data_master_1_paddr_size |
+ 0 |
+
+
+ tightly_coupled_data_master_2_paddr_base |
+ 0 |
+
+
+ tightly_coupled_data_master_2_paddr_size |
+ 0 |
+
+
+ tightly_coupled_data_master_3_paddr_base |
+ 0 |
+
+
+ tightly_coupled_data_master_3_paddr_size |
+ 0 |
+
+
+ instruction_master_high_performance_paddr_base |
+ 0 |
+
+
+ instruction_master_high_performance_paddr_size |
+ 0 |
+
+
+ data_master_high_performance_paddr_base |
+ 0 |
+
+
+ data_master_high_performance_paddr_size |
+ 0 |
+
+
+ resetAbsoluteAddr |
+ 131072 |
+
+
+ exceptionAbsoluteAddr |
+ 131104 |
+
+
+ breakAbsoluteAddr |
+ 264224 |
+
+
+ mmu_TLBMissExcAbsAddr |
+ 0 |
+
+
+ dcache_bursts_derived |
+ false |
+
+
+ dcache_size_derived |
+ 2048 |
+
+
+ breakSlave_derived |
+ nios2_gen2.debug_mem_slave |
+
+
+ dcache_lineSize_derived |
+ 32 |
+
+
+ setting_ioregionBypassDCache |
+ false |
+
+
+ setting_bit31BypassDCache |
+ true |
+
+
+ translate_on |
+ "synthesis translate_on" |
+
+
+ translate_off |
+ "synthesis translate_off" |
+
+
+ debug_onchiptrace |
+ false |
+
+
+ debug_offchiptrace |
+ false |
+
+
+ debug_insttrace |
+ false |
+
+
+ debug_datatrace |
+ false |
+
+
+ instAddrWidth |
+ 19 |
+
+
+ faAddrWidth |
+ 1 |
+
+
+ dataAddrWidth |
+ 19 |
+
+
+ tightlyCoupledDataMaster0AddrWidth |
+ 1 |
+
+
+ tightlyCoupledDataMaster1AddrWidth |
+ 1 |
+
+
+ tightlyCoupledDataMaster2AddrWidth |
+ 1 |
+
+
+ tightlyCoupledDataMaster3AddrWidth |
+ 1 |
+
+
+ tightlyCoupledInstructionMaster0AddrWidth |
+ 1 |
+
+
+ tightlyCoupledInstructionMaster1AddrWidth |
+ 1 |
+
+
+ tightlyCoupledInstructionMaster2AddrWidth |
+ 1 |
+
+
+ tightlyCoupledInstructionMaster3AddrWidth |
+ 1 |
+
+
+ dataMasterHighPerformanceAddrWidth |
+ 1 |
+
+
+ instructionMasterHighPerformanceAddrWidth |
+ 1 |
+
+
+ instSlaveMapParam |
+ <address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /></address-map> |
+
+
+ faSlaveMapParam |
+ |
+
+
+ dataSlaveMapParam |
+ <address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /><slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /><slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /><slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /><slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /><slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /><slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /><slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /><slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /><slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map> |
+
+
+ tightlyCoupledDataMaster0MapParam |
+ |
+
+
+ tightlyCoupledDataMaster1MapParam |
+ |
+
+
+ tightlyCoupledDataMaster2MapParam |
+ |
+
+
+ tightlyCoupledDataMaster3MapParam |
+ |
+
+
+ tightlyCoupledInstructionMaster0MapParam |
+ |
+
+
+ tightlyCoupledInstructionMaster1MapParam |
+ |
+
+
+ tightlyCoupledInstructionMaster2MapParam |
+ |
+
+
+ tightlyCoupledInstructionMaster3MapParam |
+ |
+
+
+ dataMasterHighPerformanceMapParam |
+ |
+
+
+ instructionMasterHighPerformanceMapParam |
+ |
+
+
+ clockFrequency |
+ 50000000 |
+
+
+ deviceFamilyName |
+ MAX10FPGA |
+
+
+ internalIrqMaskSystemInfo |
+ 15 |
+
+
+ customInstSlavesSystemInfo |
+ <info/> |
+
+
+ customInstSlavesSystemInfo_nios_a |
+ <info/> |
+
+
+ customInstSlavesSystemInfo_nios_b |
+ <info/> |
+
+
+ customInstSlavesSystemInfo_nios_c |
+ <info/> |
+
+
+ deviceFeaturesSystemInfo |
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 |
+
+
+ AUTO_DEVICE |
+ 10M50DAF484C7G |
+
+
+ AUTO_DEVICE_SPEEDGRADE |
+ 7 |
+
+
+ AUTO_CLK_CLOCK_DOMAIN |
+ 1 |
+
+
+ AUTO_CLK_RESET_DOMAIN |
+ 1 |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ BIG_ENDIAN |
+ 0 |
+
+
+ BREAK_ADDR |
+ 0x00040820 |
+
+
+ CPU_ARCH_NIOS2_R1 |
+ |
+
+
+ CPU_FREQ |
+ 50000000u |
+
+
+ CPU_ID_SIZE |
+ 1 |
+
+
+ CPU_ID_VALUE |
+ 0x00000000 |
+
+
+ CPU_IMPLEMENTATION |
+ "fast" |
+
+
+ DATA_ADDR_WIDTH |
+ 19 |
+
+
+ DCACHE_BYPASS_MASK |
+ 0x80000000 |
+
+
+ DCACHE_LINE_SIZE |
+ 32 |
+
+
+ DCACHE_LINE_SIZE_LOG2 |
+ 5 |
+
+
+ DCACHE_SIZE |
+ 2048 |
+
+
+ EXCEPTION_ADDR |
+ 0x00020020 |
+
+
+ FLASH_ACCELERATOR_LINES |
+ 0 |
+
+
+ FLASH_ACCELERATOR_LINE_SIZE |
+ 0 |
+
+
+ FLUSHDA_SUPPORTED |
+ |
+
+
+ HARDWARE_DIVIDE_PRESENT |
+ 0 |
+
+
+ HARDWARE_MULTIPLY_PRESENT |
+ 1 |
+
+
+ HARDWARE_MULX_PRESENT |
+ 0 |
+
+
+ HAS_DEBUG_CORE |
+ 1 |
+
+
+ HAS_DEBUG_STUB |
+ |
+
+
+ HAS_EXTRA_EXCEPTION_INFO |
+ |
+
+
+ HAS_ILLEGAL_INSTRUCTION_EXCEPTION |
+ |
+
+
+ HAS_JMPI_INSTRUCTION |
+ |
+
+
+ ICACHE_LINE_SIZE |
+ 32 |
+
+
+ ICACHE_LINE_SIZE_LOG2 |
+ 5 |
+
+
+ ICACHE_SIZE |
+ 4096 |
+
+
+ INITDA_SUPPORTED |
+ |
+
+
+ INST_ADDR_WIDTH |
+ 19 |
+
+
+ NUM_OF_SHADOW_REG_SETS |
+ 0 |
+
+
+ OCI_VERSION |
+ 1 |
+
+
+ RESET_ADDR |
+ 0x00020000 |
+
+
+ |
+
+
+
+
+
+
+
onchip_memory2_0
altera_avalon_onchip_memory2 v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ onchip_memory2_0 |
+
+
+ s1 |
+
+
+ instruction_master |
+
+
+ s1 |
+
+
+ debug_reset_request |
+
+
+ reset1 |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk1 |
+
+
+ clk_reset |
+
+
+ reset1 |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ allowInSystemMemoryContentEditor |
+ false |
+
+
+ blockType |
+ AUTO |
+
+
+ dataWidth |
+ 32 |
+
+
+ dataWidth2 |
+ 32 |
+
+
+ dualPort |
+ false |
+
+
+ enableDiffWidth |
+ false |
+
+
+ initMemContent |
+ false |
+
+
+ initializationFileName |
+ onchip_mem.hex |
+
+
+ instanceID |
+ NONE |
+
+
+ memorySize |
+ 100000 |
+
+
+ readDuringWriteMode |
+ DONT_CARE |
+
+
+ simAllowMRAMContentsFile |
+ false |
+
+
+ simMemInitOnlyFilename |
+ 0 |
+
+
+ singleClockOperation |
+ false |
+
+
+ slave1Latency |
+ 1 |
+
+
+ slave2Latency |
+ 1 |
+
+
+ useNonDefaultInitFile |
+ false |
+
+
+ copyInitFile |
+ false |
+
+
+ useShallowMemBlocks |
+ false |
+
+
+ writable |
+ true |
+
+
+ ecc_enabled |
+ false |
+
+
+ resetrequest_enabled |
+ true |
+
+
+ autoInitializationFileName |
+ Qsys_onchip_memory2_0 |
+
+
+ deviceFamily |
+ MAX10FPGA |
+
+
+ deviceFeatures |
+ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 |
+
+
+ derived_set_addr_width |
+ 15 |
+
+
+ derived_set_addr_width2 |
+ 15 |
+
+
+ derived_set_data_width |
+ 32 |
+
+
+ derived_set_data_width2 |
+ 32 |
+
+
+ derived_gui_ram_block_type |
+ Automatic |
+
+
+ derived_is_hardcopy |
+ false |
+
+
+ derived_init_file_name |
+ Qsys_onchip_memory2_0.hex |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR |
+ 0 |
+
+
+ ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE |
+ 0 |
+
+
+ CONTENTS_INFO |
+ "" |
+
+
+ DUAL_PORT |
+ 0 |
+
+
+ GUI_RAM_BLOCK_TYPE |
+ AUTO |
+
+
+ INIT_CONTENTS_FILE |
+ Qsys_onchip_memory2_0 |
+
+
+ INIT_MEM_CONTENT |
+ 0 |
+
+
+ INSTANCE_ID |
+ NONE |
+
+
+ NON_DEFAULT_INIT_FILE_ENABLED |
+ 0 |
+
+
+ RAM_BLOCK_TYPE |
+ AUTO |
+
+
+ READ_DURING_WRITE_MODE |
+ DONT_CARE |
+
+
+ SINGLE_CLOCK_OP |
+ 0 |
+
+
+ SIZE_MULTIPLE |
+ 1 |
+
+
+ SIZE_VALUE |
+ 100000 |
+
+
+ WRITABLE |
+ 1 |
+
+
+ |
+
+
+
+
+
+
+
sdram
altera_avalon_new_sdram_controller v16.0
+
+
+
+
+
+ alt_vip_vfb_0
+ |
+ read_master |
+ sdram |
+
+
+ s1 |
+
+
+ write_master |
+
+
+ s1 |
+
+
+ |
+
+
+
+ altpll_0
+ |
+ c2 |
+
+
+ clk |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk_reset |
+
+
+ reset |
+
+
+ |
+
+
+
+ nios2_gen2
+ |
+ debug_reset_request |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ TAC |
+ 5.5 |
+
+
+ TRCD |
+ 20.0 |
+
+
+ TRFC |
+ 70.0 |
+
+
+ TRP |
+ 20.0 |
+
+
+ TWR |
+ 14.0 |
+
+
+ casLatency |
+ 3 |
+
+
+ columnWidth |
+ 10 |
+
+
+ dataWidth |
+ 16 |
+
+
+ generateSimulationModel |
+ true |
+
+
+ initRefreshCommands |
+ 2 |
+
+
+ model |
+ single_Micron_MT48LC4M32B2_7_chip |
+
+
+ numberOfBanks |
+ 4 |
+
+
+ numberOfChipSelects |
+ 1 |
+
+
+ pinsSharedViaTriState |
+ false |
+
+
+ powerUpDelay |
+ 100.0 |
+
+
+ refreshPeriod |
+ 15.625 |
+
+
+ rowWidth |
+ 13 |
+
+
+ masteredTristateBridgeSlave |
+ 0 |
+
+
+ TMRD |
+ 3 |
+
+
+ initNOPDelay |
+ 0.0 |
+
+
+ registerDataIn |
+ true |
+
+
+ clockRate |
+ 100000000 |
+
+
+ componentName |
+ Qsys_sdram |
+
+
+ size |
+ 67108864 |
+
+
+ addressWidth |
+ 25 |
+
+
+ bankWidth |
+ 2 |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ CAS_LATENCY |
+ 3 |
+
+
+ CONTENTS_INFO |
+ |
+
+
+ INIT_NOP_DELAY |
+ 0.0 |
+
+
+ INIT_REFRESH_COMMANDS |
+ 2 |
+
+
+ IS_INITIALIZED |
+ 1 |
+
+
+ POWERUP_DELAY |
+ 100.0 |
+
+
+ REFRESH_PERIOD |
+ 15.625 |
+
+
+ REGISTER_DATA_IN |
+ 1 |
+
+
+ SDRAM_ADDR_WIDTH |
+ 25 |
+
+
+ SDRAM_BANK_WIDTH |
+ 2 |
+
+
+ SDRAM_COL_WIDTH |
+ 10 |
+
+
+ SDRAM_DATA_WIDTH |
+ 16 |
+
+
+ SDRAM_NUM_BANKS |
+ 4 |
+
+
+ SDRAM_NUM_CHIPSELECTS |
+ 1 |
+
+
+ SDRAM_ROW_WIDTH |
+ 13 |
+
+
+ SHARED_DATA |
+ 0 |
+
+
+ SIM_MODEL_BASE |
+ 1 |
+
+
+ STARVATION_INDICATOR |
+ 0 |
+
+
+ TRISTATE_BRIDGE_SLAVE |
+ "" |
+
+
+ T_AC |
+ 5.5 |
+
+
+ T_MRD |
+ 3 |
+
+
+ T_RCD |
+ 20.0 |
+
+
+ T_RFC |
+ 70.0 |
+
+
+ T_RP |
+ 20.0 |
+
+
+ T_WR |
+ 14.0 |
+
+
+ |
+
+
+
+
+
+
+
sw
altera_avalon_pio v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ sw |
+
+
+ s1 |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ bitClearingEdgeCapReg |
+ false |
+
+
+ bitModifyingOutReg |
+ false |
+
+
+ captureEdge |
+ false |
+
+
+ direction |
+ Input |
+
+
+ edgeType |
+ RISING |
+
+
+ generateIRQ |
+ false |
+
+
+ irqType |
+ LEVEL |
+
+
+ resetValue |
+ 0 |
+
+
+ simDoTestBenchWiring |
+ false |
+
+
+ simDrivenValue |
+ 0 |
+
+
+ width |
+ 10 |
+
+
+ clockRate |
+ 50000000 |
+
+
+ derived_has_tri |
+ false |
+
+
+ derived_has_out |
+ false |
+
+
+ derived_has_in |
+ true |
+
+
+ derived_do_test_bench_wiring |
+ false |
+
+
+ derived_capture |
+ false |
+
+
+ derived_edge_type |
+ NONE |
+
+
+ derived_irq_type |
+ NONE |
+
+
+ derived_has_irq |
+ false |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ BIT_CLEARING_EDGE_REGISTER |
+ 0 |
+
+
+ BIT_MODIFYING_OUTPUT_REGISTER |
+ 0 |
+
+
+ CAPTURE |
+ 0 |
+
+
+ DATA_WIDTH |
+ 10 |
+
+
+ DO_TEST_BENCH_WIRING |
+ 0 |
+
+
+ DRIVEN_SIM_VALUE |
+ 0 |
+
+
+ EDGE_TYPE |
+ NONE |
+
+
+ FREQ |
+ 50000000 |
+
+
+ HAS_IN |
+ 1 |
+
+
+ HAS_OUT |
+ 0 |
+
+
+ HAS_TRI |
+ 0 |
+
+
+ IRQ_TYPE |
+ NONE |
+
+
+ RESET_VALUE |
+ 0 |
+
+
+ |
+
+
+
+
+
+
+
sysid_qsys
altera_avalon_sysid_qsys v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ sysid_qsys |
+
+
+ control_slave |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ id |
+ 0 |
+
+
+ timestamp |
+ 1617092314 |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ ID |
+ 0 |
+
+
+ TIMESTAMP |
+ 1617092314 |
+
+
+ |
+
+
+
+
+
+
+
timer
altera_avalon_timer v16.0
+
+
+
+
+
+ nios2_gen2
+ |
+ data_master |
+ timer |
+
+
+ s1 |
+
+
+ irq |
+
+
+ irq |
+
+
+ debug_reset_request |
+
+
+ reset |
+
+
+ |
+
+
+
+ clk_50
+ |
+ clk |
+
+
+ clk |
+
+
+ clk_reset |
+
+
+ reset |
+
+
+
+
+
+
+
+
+ Parameters
+
+
+ alwaysRun |
+ false |
+
+
+ counterSize |
+ 32 |
+
+
+ fixedPeriod |
+ false |
+
+
+ period |
+ 1 |
+
+
+ periodUnits |
+ MSEC |
+
+
+ resetOutput |
+ false |
+
+
+ snapshot |
+ true |
+
+
+ timeoutPulseOutput |
+ false |
+
+
+ systemFrequency |
+ 50000000 |
+
+
+ watchdogPulse |
+ 2 |
+
+
+ timerPreset |
+ FULL_FEATURED |
+
+
+ periodUnitsString |
+ ms |
+
+
+ valueInSecond |
+ 0.001 |
+
+
+ loadValue |
+ 49999 |
+
+
+ mult |
+ 0.001 |
+
+
+ ticksPerSec |
+ 1000.0 |
+
+
+ slave_address_width |
+ 3 |
+
+
+ deviceFamily |
+ UNKNOWN |
+
+
+ generateLegacySim |
+ false |
+
+
+ |
+
+
+
+
+
+ Software Assignments
+
+
+ ALWAYS_RUN |
+ 0 |
+
+
+ COUNTER_SIZE |
+ 32 |
+
+
+ FIXED_PERIOD |
+ 0 |
+
+
+ FREQ |
+ 50000000 |
+
+
+ LOAD_VALUE |
+ 49999 |
+
+
+ MULT |
+ 0.001 |
+
+
+ PERIOD |
+ 1 |
+
+
+ PERIOD_UNITS |
+ ms |
+
+
+ RESET_OUTPUT |
+ 0 |
+
+
+ SNAPSHOT |
+ 1 |
+
+
+ TICKS_PER_SEC |
+ 1000 |
+
+
+ TIMEOUT_PULSE_OUTPUT |
+ 0 |
+
+
+ |
+
+
+
+
+
+ generation took 0.00 seconds |
+ rendering took 0.04 seconds |
+
+
+
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml
new file mode 100644
index 0000000..b2467f4
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml
@@ -0,0 +1,5410 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+ queue size: 0 starting:Qsys "Qsys"
+
+
+
+ Transform: CustomInstructionTransform
+ No custom instruction connections, skipping transform
+ 19 modules, 78 connections]]>
+ Transform: MMTransform
+ Transform: InitialInterconnectTransform
+ 15 modules, 57 connections]]>
+ Transform: TerminalIdAssignmentUpdateTransform
+ Transform: DefaultSlaveTransform
+ Transform: TranslatorTransform
+
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+ 31 modules, 120 connections]]>
+ Transform: IDPadTransform
+ Transform: DomainTransform
+ Transform merlin_domain_transform not run on matched interfaces nios2_gen2.data_master and nios2_gen2_data_master_translator.avalon_anti_master_0
+ Transform merlin_domain_transform not run on matched interfaces nios2_gen2.instruction_master and nios2_gen2_instruction_master_translator.avalon_anti_master_0
+
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+
+ Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave
+ Transform merlin_domain_transform not run on matched interfaces i2c_opencores_mipi_avalon_slave_0_translator.avalon_anti_slave_0 and i2c_opencores_mipi.avalon_slave_0
+ Transform merlin_domain_transform not run on matched interfaces i2c_opencores_camera_avalon_slave_0_translator.avalon_anti_slave_0 and i2c_opencores_camera.avalon_slave_0
+ Transform merlin_domain_transform not run on matched interfaces sysid_qsys_control_slave_translator.avalon_anti_slave_0 and sysid_qsys.control_slave
+ Transform merlin_domain_transform not run on matched interfaces nios2_gen2_debug_mem_slave_translator.avalon_anti_slave_0 and nios2_gen2.debug_mem_slave
+ Transform merlin_domain_transform not run on matched interfaces TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.avalon_anti_slave_0 and TERASIC_AUTO_FOCUS_0.mm_ctrl
+ Transform merlin_domain_transform not run on matched interfaces altpll_0_pll_slave_translator.avalon_anti_slave_0 and altpll_0.pll_slave
+ Transform merlin_domain_transform not run on matched interfaces onchip_memory2_0_s1_translator.avalon_anti_slave_0 and onchip_memory2_0.s1
+ Transform merlin_domain_transform not run on matched interfaces timer_s1_translator.avalon_anti_slave_0 and timer.s1
+ Transform merlin_domain_transform not run on matched interfaces led_s1_translator.avalon_anti_slave_0 and led.s1
+ Transform merlin_domain_transform not run on matched interfaces sw_s1_translator.avalon_anti_slave_0 and sw.s1
+ Transform merlin_domain_transform not run on matched interfaces key_s1_translator.avalon_anti_slave_0 and key.s1
+ Transform merlin_domain_transform not run on matched interfaces mipi_reset_n_s1_translator.avalon_anti_slave_0 and mipi_reset_n.s1
+ Transform merlin_domain_transform not run on matched interfaces mipi_pwdn_n_s1_translator.avalon_anti_slave_0 and mipi_pwdn_n.s1
+ 63 modules, 333 connections]]>
+ Transform: RouterTransform
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ 79 modules, 396 connections]]>
+ Transform: TrafficLimiterTransform
+
+
+
+
+
+
+ 81 modules, 406 connections]]>
+ Transform: BurstTransform
+ Transform: TreeTransform
+ Transform: NetworkToSwitchTransform
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ 112 modules, 485 connections]]>
+ Transform: WidthTransform
+ Transform: RouterTableTransform
+ Transform: ThreadIDMappingTableTransform
+ Transform: ClockCrossingTransform
+ Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
+
+
+
+ Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
+
+
+
+ 114 modules, 499 connections]]>
+ Transform: PipelineTransform
+ Transform: SpotPipelineTransform
+ Transform: PerformanceMonitorTransform
+ Transform: TrafficLimiterUpdateTransform
+ 114 modules, 501 connections]]>
+ Transform: InsertClockAndResetBridgesTransform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 119 modules, 621 connections]]>
+ Transform: InterconnectConnectionsTagger
+ Transform: HierarchyTransform
+
+
+
+ 20 modules, 85 connections]]>
+ Transform: InitialInterconnectTransform
+ 5 modules, 8 connections]]>
+ Transform: TerminalIdAssignmentUpdateTransform
+ Transform: DefaultSlaveTransform
+ Transform: TranslatorTransform
+
+
+
+
+
+
+
+
+
+ 8 modules, 20 connections]]>
+ Transform: IDPadTransform
+ Transform: DomainTransform
+ Transform merlin_domain_transform not run on matched interfaces alt_vip_vfb_0.read_master and alt_vip_vfb_0_read_master_translator.avalon_anti_master_0
+ Transform merlin_domain_transform not run on matched interfaces alt_vip_vfb_0.write_master and alt_vip_vfb_0_write_master_translator.avalon_anti_master_0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Transform merlin_domain_transform not run on matched interfaces sdram_s1_translator.avalon_anti_slave_0 and sdram.s1
+ 14 modules, 55 connections]]>
+ Transform: RouterTransform
+
+
+
+
+
+
+
+
+
+ 17 modules, 67 connections]]>
+ Transform: TrafficLimiterTransform
+ Transform: BurstTransform
+
+
+
+ 18 modules, 71 connections]]>
+ Transform: TreeTransform
+ Transform: NetworkToSwitchTransform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 23 modules, 84 connections]]>
+ Transform: WidthTransform
+
+
+
+
+
+
+ 25 modules, 92 connections]]>
+ Transform: RouterTableTransform
+ Transform: ThreadIDMappingTableTransform
+ Transform: ClockCrossingTransform
+ Transform: PipelineTransform
+ Transform: SpotPipelineTransform
+ Transform: PerformanceMonitorTransform
+ Transform: TrafficLimiterUpdateTransform
+ Transform: InsertClockAndResetBridgesTransform
+
+
+
+
+
+
+ 27 modules, 116 connections]]>
+ Transform: InterconnectConnectionsTagger
+ Transform: HierarchyTransform
+
+
+
+ 21 modules, 89 connections]]>
+ 21 modules, 89 connections]]>
+ Transform: InterruptMapperTransform
+
+
+
+ 22 modules, 93 connections]]>
+ Transform: InterruptSyncTransform
+ Transform: InterruptFanoutTransform
+ Transform: AvalonStreamingTransform
+ Transform: ResetAdaptation
+
+
+
+
+
+
+
+
+
+
+
+
+ 26 modules, 93 connections]]>
+ Qsys" reuses TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS"]]>
+ Qsys" reuses TERASIC_CAMERA "submodules/TERASIC_CAMERA"]]>
+ Qsys" reuses alt_vip_itc "submodules/alt_vipitc131_IS2Vid"]]>
+ Qsys" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]>
+ Qsys" reuses altpll "submodules/Qsys_altpll_0"]]>
+ Qsys" reuses i2c_opencores "submodules/i2c_opencores"]]>
+ Qsys" reuses i2c_opencores "submodules/i2c_opencores"]]>
+ Qsys" reuses altera_avalon_jtag_uart "submodules/Qsys_jtag_uart"]]>
+ Qsys" reuses altera_avalon_pio "submodules/Qsys_key"]]>
+ Qsys" reuses altera_avalon_pio "submodules/Qsys_led"]]>
+ Qsys" reuses altera_avalon_pio "submodules/Qsys_mipi_pwdn_n"]]>
+ Qsys" reuses altera_avalon_pio "submodules/Qsys_mipi_pwdn_n"]]>
+ Qsys" reuses altera_nios2_gen2 "submodules/Qsys_nios2_gen2"]]>
+ Qsys" reuses altera_avalon_onchip_memory2 "submodules/Qsys_onchip_memory2_0"]]>
+ Qsys" reuses altera_avalon_new_sdram_controller "submodules/Qsys_sdram"]]>
+ Qsys" reuses altera_avalon_pio "submodules/Qsys_sw"]]>
+ Qsys" reuses altera_avalon_sysid_qsys "submodules/Qsys_sysid_qsys"]]>
+ Qsys" reuses altera_avalon_timer "submodules/Qsys_timer"]]>
+ Qsys" reuses altera_mm_interconnect "submodules/Qsys_mm_interconnect_0"]]>
+ Qsys" reuses altera_mm_interconnect "submodules/Qsys_mm_interconnect_1"]]>
+ Qsys" reuses altera_irq_mapper "submodules/Qsys_irq_mapper"]]>
+ Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]>
+ Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]>
+ Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]>
+ queue size: 23 starting:TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS"
+ Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"]]>
+ queue size: 22 starting:TERASIC_CAMERA "submodules/TERASIC_CAMERA"
+ set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/not_a_project_setup.tcl
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
+ Command took 0.601s
+ Command took 0.919s
+ Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"]]>
+ queue size: 21 starting:alt_vip_itc "submodules/alt_vipitc131_IS2Vid"
+ set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/not_a_project_setup.tcl
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/altera_lite/16.0/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
+ Command took 0.544s
+ Command took 0.880s
+ Qsys" instantiated alt_vip_itc "alt_vip_itc_0"]]>
+ queue size: 20 starting:alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp160_avalon_st_input"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp160_avalon_st_output"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp160_pulling_width_adapter"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp160_pushing_width_adapter"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp160_clock_reset"]]>
+ dut" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]>
+ Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"]]>
+ queue size: 218 starting:altpll "submodules/Qsys_altpll_0"
+
+
+ set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --source=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0018_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
+ Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing
+ Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
+ Peak virtual memory: 1399 megabytes
+ Processing ended: Tue Mar 30 09:18:43 2021
+ Elapsed time: 00:00:01
+ Total CPU time (on all processors): 00:00:00
+ Command took 0.958s
+ Analyser output file not present: Qsys_altpll_0.v.xml
+ /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0]]>
+ /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory)
+ Qsys" instantiated altpll "altpll_0"]]>
+
+
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+
+ queue size: 23 starting:TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS"
+ Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"]]>
+
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+ queue size: 22 starting:TERASIC_CAMERA "submodules/TERASIC_CAMERA"
+ set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/not_a_project_setup.tcl
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
+ Command took 0.601s
+ Command took 0.919s
+ Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"]]>
+
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+ queue size: 21 starting:alt_vip_itc "submodules/alt_vipitc131_IS2Vid"
+ set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/not_a_project_setup.tcl
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/altera_lite/16.0/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
+ Command took 0.544s
+ Command took 0.880s
+ Qsys" instantiated alt_vip_itc "alt_vip_itc_0"]]>
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ queue size: 20 starting:alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp160_avalon_st_input"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp160_avalon_st_output"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp160_pulling_width_adapter"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp160_pushing_width_adapter"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]>
+ alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]>
+ alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]>
+ dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp160_clock_reset"]]>
+ dut" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]>
+ Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"]]>
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+ queue size: 218 starting:altpll "submodules/Qsys_altpll_0"
+
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+ set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files
+ Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --source=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0018_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on
+ Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing
+ Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
+ Peak virtual memory: 1399 megabytes
+ Processing ended: Tue Mar 30 09:18:43 2021
+ Elapsed time: 00:00:01
+ Total CPU time (on all processors): 00:00:00
+ Command took 0.958s
+ Analyser output file not present: Qsys_altpll_0.v.xml
+ /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0]]>
+ /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory)
+ Qsys" instantiated altpll "altpll_0"]]>
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diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v
new file mode 100644
index 0000000..d41fc44
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_bb.v
@@ -0,0 +1,88 @@
+
+module Qsys (
+ alt_vip_itc_0_clocked_video_vid_clk,
+ alt_vip_itc_0_clocked_video_vid_data,
+ alt_vip_itc_0_clocked_video_underflow,
+ alt_vip_itc_0_clocked_video_vid_datavalid,
+ alt_vip_itc_0_clocked_video_vid_v_sync,
+ alt_vip_itc_0_clocked_video_vid_h_sync,
+ alt_vip_itc_0_clocked_video_vid_f,
+ alt_vip_itc_0_clocked_video_vid_h,
+ alt_vip_itc_0_clocked_video_vid_v,
+ altpll_0_areset_conduit_export,
+ altpll_0_locked_conduit_export,
+ clk_clk,
+ clk_sdram_clk,
+ clk_vga_clk,
+ d8m_xclkin_clk,
+ eee_imgproc_0_conduit_mode_new_signal,
+ i2c_opencores_camera_export_scl_pad_io,
+ i2c_opencores_camera_export_sda_pad_io,
+ i2c_opencores_mipi_export_scl_pad_io,
+ i2c_opencores_mipi_export_sda_pad_io,
+ key_external_connection_export,
+ led_external_connection_export,
+ mipi_pwdn_n_external_connection_export,
+ mipi_reset_n_external_connection_export,
+ reset_reset_n,
+ sdram_wire_addr,
+ sdram_wire_ba,
+ sdram_wire_cas_n,
+ sdram_wire_cke,
+ sdram_wire_cs_n,
+ sdram_wire_dq,
+ sdram_wire_dqm,
+ sdram_wire_ras_n,
+ sdram_wire_we_n,
+ sw_external_connection_export,
+ terasic_auto_focus_0_conduit_vcm_i2c_sda,
+ terasic_auto_focus_0_conduit_clk50,
+ terasic_auto_focus_0_conduit_vcm_i2c_scl,
+ terasic_camera_0_conduit_end_D,
+ terasic_camera_0_conduit_end_FVAL,
+ terasic_camera_0_conduit_end_LVAL,
+ terasic_camera_0_conduit_end_PIXCLK);
+
+ input alt_vip_itc_0_clocked_video_vid_clk;
+ output [23:0] alt_vip_itc_0_clocked_video_vid_data;
+ output alt_vip_itc_0_clocked_video_underflow;
+ output alt_vip_itc_0_clocked_video_vid_datavalid;
+ output alt_vip_itc_0_clocked_video_vid_v_sync;
+ output alt_vip_itc_0_clocked_video_vid_h_sync;
+ output alt_vip_itc_0_clocked_video_vid_f;
+ output alt_vip_itc_0_clocked_video_vid_h;
+ output alt_vip_itc_0_clocked_video_vid_v;
+ input altpll_0_areset_conduit_export;
+ output altpll_0_locked_conduit_export;
+ input clk_clk;
+ output clk_sdram_clk;
+ output clk_vga_clk;
+ output d8m_xclkin_clk;
+ input eee_imgproc_0_conduit_mode_new_signal;
+ inout i2c_opencores_camera_export_scl_pad_io;
+ inout i2c_opencores_camera_export_sda_pad_io;
+ inout i2c_opencores_mipi_export_scl_pad_io;
+ inout i2c_opencores_mipi_export_sda_pad_io;
+ input [1:0] key_external_connection_export;
+ output [9:0] led_external_connection_export;
+ output mipi_pwdn_n_external_connection_export;
+ output mipi_reset_n_external_connection_export;
+ input reset_reset_n;
+ output [12:0] sdram_wire_addr;
+ output [1:0] sdram_wire_ba;
+ output sdram_wire_cas_n;
+ output sdram_wire_cke;
+ output sdram_wire_cs_n;
+ inout [15:0] sdram_wire_dq;
+ output [1:0] sdram_wire_dqm;
+ output sdram_wire_ras_n;
+ output sdram_wire_we_n;
+ input [9:0] sw_external_connection_export;
+ inout terasic_auto_focus_0_conduit_vcm_i2c_sda;
+ input terasic_auto_focus_0_conduit_clk50;
+ inout terasic_auto_focus_0_conduit_vcm_i2c_scl;
+ input [11:0] terasic_camera_0_conduit_end_D;
+ input terasic_camera_0_conduit_end_FVAL;
+ input terasic_camera_0_conduit_end_LVAL;
+ input terasic_camera_0_conduit_end_PIXCLK;
+endmodule
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt
new file mode 100644
index 0000000..6db46bd
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt
@@ -0,0 +1,129 @@
+Info: Starting: Create block symbol file (.bsf)
+Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G
+Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
+Progress: Reading input file
+Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
+Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
+Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
+Progress: Parameterizing module TERASIC_CAMERA_0
+Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
+Progress: Parameterizing module alt_vip_itc_0
+Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
+Progress: Parameterizing module alt_vip_vfb_0
+Progress: Adding altpll_0 [altpll 16.0]
+Progress: Parameterizing module altpll_0
+Progress: Adding clk_50 [clock_source 16.0]
+Progress: Parameterizing module clk_50
+Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_camera
+Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_mipi
+Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
+Progress: Parameterizing module jtag_uart
+Progress: Adding key [altera_avalon_pio 16.0]
+Progress: Parameterizing module key
+Progress: Adding led [altera_avalon_pio 16.0]
+Progress: Parameterizing module led
+Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_pwdn_n
+Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_reset_n
+Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
+Progress: Parameterizing module nios2_gen2
+Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
+Progress: Parameterizing module onchip_memory2_0
+Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
+Progress: Parameterizing module sdram
+Progress: Adding sw [altera_avalon_pio 16.0]
+Progress: Parameterizing module sw
+Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
+Progress: Parameterizing module sysid_qsys
+Progress: Adding timer [altera_avalon_timer 16.0]
+Progress: Parameterizing module timer
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
+Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
+Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
+Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
+Info: qsys-generate succeeded.
+Info: Finished: Create block symbol file (.bsf)
+Info:
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G
+Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
+Progress: Reading input file
+Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
+Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
+Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
+Progress: Parameterizing module TERASIC_CAMERA_0
+Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
+Progress: Parameterizing module alt_vip_itc_0
+Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
+Progress: Parameterizing module alt_vip_vfb_0
+Progress: Adding altpll_0 [altpll 16.0]
+Progress: Parameterizing module altpll_0
+Progress: Adding clk_50 [clock_source 16.0]
+Progress: Parameterizing module clk_50
+Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_camera
+Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_mipi
+Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
+Progress: Parameterizing module jtag_uart
+Progress: Adding key [altera_avalon_pio 16.0]
+Progress: Parameterizing module key
+Progress: Adding led [altera_avalon_pio 16.0]
+Progress: Parameterizing module led
+Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_pwdn_n
+Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_reset_n
+Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
+Progress: Parameterizing module nios2_gen2
+Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
+Progress: Parameterizing module onchip_memory2_0
+Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
+Progress: Parameterizing module sdram
+Progress: Adding sw [altera_avalon_pio 16.0]
+Progress: Parameterizing module sw
+Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
+Progress: Parameterizing module sysid_qsys
+Progress: Adding timer [altera_avalon_timer 16.0]
+Progress: Parameterizing module timer
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
+Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
+Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
+Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
+Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
+Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
+Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
+Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
+Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
+Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
+Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
+Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
+Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092322619640" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
+Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing
+Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
+Error: Peak virtual memory: 1399 megabytes
+Error: Processing ended: Tue Mar 30 09:18:43 2021
+Error: Elapsed time: 00:00:01
+Error: Total CPU time (on all processors): 00:00:00
+Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
+Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory)
+Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
+Error: Generation stopped, 218 or more modules remaining
+Info: Qsys: Done "Qsys" with 33 modules, 34 files
+Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning
+Info: Finished: Create HDL design files for synthesis
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt
new file mode 100644
index 0000000..3a37812
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt
@@ -0,0 +1,129 @@
+Info: Starting: Create block symbol file (.bsf)
+Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G
+Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
+Progress: Reading input file
+Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
+Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
+Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
+Progress: Parameterizing module TERASIC_CAMERA_0
+Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
+Progress: Parameterizing module alt_vip_itc_0
+Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
+Progress: Parameterizing module alt_vip_vfb_0
+Progress: Adding altpll_0 [altpll 16.0]
+Progress: Parameterizing module altpll_0
+Progress: Adding clk_50 [clock_source 16.0]
+Progress: Parameterizing module clk_50
+Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_camera
+Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_mipi
+Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
+Progress: Parameterizing module jtag_uart
+Progress: Adding key [altera_avalon_pio 16.0]
+Progress: Parameterizing module key
+Progress: Adding led [altera_avalon_pio 16.0]
+Progress: Parameterizing module led
+Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_pwdn_n
+Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_reset_n
+Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
+Progress: Parameterizing module nios2_gen2
+Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
+Progress: Parameterizing module onchip_memory2_0
+Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
+Progress: Parameterizing module sdram
+Progress: Adding sw [altera_avalon_pio 16.0]
+Progress: Parameterizing module sw
+Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
+Progress: Parameterizing module sysid_qsys
+Progress: Adding timer [altera_avalon_timer 16.0]
+Progress: Parameterizing module timer
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
+Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
+Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
+Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
+Info: qsys-generate succeeded.
+Info: Finished: Create block symbol file (.bsf)
+Info:
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G
+Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
+Progress: Reading input file
+Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
+Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
+Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
+Progress: Parameterizing module TERASIC_CAMERA_0
+Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
+Progress: Parameterizing module alt_vip_itc_0
+Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
+Progress: Parameterizing module alt_vip_vfb_0
+Progress: Adding altpll_0 [altpll 16.0]
+Progress: Parameterizing module altpll_0
+Progress: Adding clk_50 [clock_source 16.0]
+Progress: Parameterizing module clk_50
+Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_camera
+Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
+Progress: Parameterizing module i2c_opencores_mipi
+Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0]
+Progress: Parameterizing module jtag_uart
+Progress: Adding key [altera_avalon_pio 16.0]
+Progress: Parameterizing module key
+Progress: Adding led [altera_avalon_pio 16.0]
+Progress: Parameterizing module led
+Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_pwdn_n
+Progress: Adding mipi_reset_n [altera_avalon_pio 16.0]
+Progress: Parameterizing module mipi_reset_n
+Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0]
+Progress: Parameterizing module nios2_gen2
+Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0]
+Progress: Parameterizing module onchip_memory2_0
+Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0]
+Progress: Parameterizing module sdram
+Progress: Adding sw [altera_avalon_pio 16.0]
+Progress: Parameterizing module sw
+Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0]
+Progress: Parameterizing module sysid_qsys
+Progress: Adding timer [altera_avalon_timer 16.0]
+Progress: Parameterizing module timer
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
+Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
+Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
+Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
+Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
+Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
+Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
+Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
+Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
+Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
+Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
+Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
+Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
+Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092145442977" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
+Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v is missing
+Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
+Error: Peak virtual memory: 1399 megabytes
+Error: Processing ended: Tue Mar 30 09:15:46 2021
+Error: Elapsed time: 00:00:00
+Error: Total CPU time (on all processors): 00:00:00
+Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
+Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v (No such file or directory)
+Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
+Error: Generation stopped, 218 or more modules remaining
+Info: Qsys: Done "Qsys" with 33 modules, 34 files
+Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning
+Info: Finished: Create HDL design files for synthesis
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v
new file mode 100644
index 0000000..053ca64
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.v
@@ -0,0 +1,45 @@
+ Qsys u0 (
+ .alt_vip_itc_0_clocked_video_vid_clk (), // alt_vip_itc_0_clocked_video.vid_clk
+ .alt_vip_itc_0_clocked_video_vid_data (), // .vid_data
+ .alt_vip_itc_0_clocked_video_underflow (), // .underflow
+ .alt_vip_itc_0_clocked_video_vid_datavalid (), // .vid_datavalid
+ .alt_vip_itc_0_clocked_video_vid_v_sync (), // .vid_v_sync
+ .alt_vip_itc_0_clocked_video_vid_h_sync (), // .vid_h_sync
+ .alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
+ .alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
+ .alt_vip_itc_0_clocked_video_vid_v (), // .vid_v
+ .altpll_0_areset_conduit_export (), // altpll_0_areset_conduit.export
+ .altpll_0_locked_conduit_export (), // altpll_0_locked_conduit.export
+ .clk_clk (), // clk.clk
+ .clk_sdram_clk (), // clk_sdram.clk
+ .clk_vga_clk (), // clk_vga.clk
+ .d8m_xclkin_clk (), // d8m_xclkin.clk
+ .eee_imgproc_0_conduit_mode_new_signal (), // eee_imgproc_0_conduit_mode.new_signal
+ .i2c_opencores_camera_export_scl_pad_io (), // i2c_opencores_camera_export.scl_pad_io
+ .i2c_opencores_camera_export_sda_pad_io (), // .sda_pad_io
+ .i2c_opencores_mipi_export_scl_pad_io (), // i2c_opencores_mipi_export.scl_pad_io
+ .i2c_opencores_mipi_export_sda_pad_io (), // .sda_pad_io
+ .key_external_connection_export (), // key_external_connection.export
+ .led_external_connection_export (), // led_external_connection.export
+ .mipi_pwdn_n_external_connection_export (), // mipi_pwdn_n_external_connection.export
+ .mipi_reset_n_external_connection_export (), // mipi_reset_n_external_connection.export
+ .reset_reset_n (), // reset.reset_n
+ .sdram_wire_addr (), // sdram_wire.addr
+ .sdram_wire_ba (), // .ba
+ .sdram_wire_cas_n (), // .cas_n
+ .sdram_wire_cke (), // .cke
+ .sdram_wire_cs_n (), // .cs_n
+ .sdram_wire_dq (), // .dq
+ .sdram_wire_dqm (), // .dqm
+ .sdram_wire_ras_n (), // .ras_n
+ .sdram_wire_we_n (), // .we_n
+ .sw_external_connection_export (), // sw_external_connection.export
+ .terasic_auto_focus_0_conduit_vcm_i2c_sda (), // terasic_auto_focus_0_conduit.vcm_i2c_sda
+ .terasic_auto_focus_0_conduit_clk50 (), // .clk50
+ .terasic_auto_focus_0_conduit_vcm_i2c_scl (), // .vcm_i2c_scl
+ .terasic_camera_0_conduit_end_D (), // terasic_camera_0_conduit_end.D
+ .terasic_camera_0_conduit_end_FVAL (), // .FVAL
+ .terasic_camera_0_conduit_end_LVAL (), // .LVAL
+ .terasic_camera_0_conduit_end_PIXCLK () // .PIXCLK
+ );
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd
new file mode 100644
index 0000000..9a4f759
--- /dev/null
+++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_inst.vhd
@@ -0,0 +1,93 @@
+ component Qsys is
+ port (
+ alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
+ alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(23 downto 0); -- vid_data
+ alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
+ alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
+ alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
+ alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
+ alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
+ alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
+ alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
+ altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
+ altpll_0_locked_conduit_export : out std_logic; -- export
+ clk_clk : in std_logic := 'X'; -- clk
+ clk_sdram_clk : out std_logic; -- clk
+ clk_vga_clk : out std_logic; -- clk
+ d8m_xclkin_clk : out std_logic; -- clk
+ eee_imgproc_0_conduit_mode_new_signal : in std_logic := 'X'; -- new_signal
+ i2c_opencores_camera_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
+ i2c_opencores_camera_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
+ i2c_opencores_mipi_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
+ i2c_opencores_mipi_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
+ key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
+ led_external_connection_export : out std_logic_vector(9 downto 0); -- export
+ mipi_pwdn_n_external_connection_export : out std_logic; -- export
+ mipi_reset_n_external_connection_export : out std_logic; -- export
+ reset_reset_n : in std_logic := 'X'; -- reset_n
+ sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
+ sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
+ sdram_wire_cas_n : out std_logic; -- cas_n
+ sdram_wire_cke : out std_logic; -- cke
+ sdram_wire_cs_n : out std_logic; -- cs_n
+ sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
+ sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
+ sdram_wire_ras_n : out std_logic; -- ras_n
+ sdram_wire_we_n : out std_logic; -- we_n
+ sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
+ terasic_auto_focus_0_conduit_vcm_i2c_sda : inout std_logic := 'X'; -- vcm_i2c_sda
+ terasic_auto_focus_0_conduit_clk50 : in std_logic := 'X'; -- clk50
+ terasic_auto_focus_0_conduit_vcm_i2c_scl : inout std_logic := 'X'; -- vcm_i2c_scl
+ terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
+ terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
+ terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
+ terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X' -- PIXCLK
+ );
+ end component Qsys;
+
+ u0 : component Qsys
+ port map (
+ alt_vip_itc_0_clocked_video_vid_clk => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_clk, -- alt_vip_itc_0_clocked_video.vid_clk
+ alt_vip_itc_0_clocked_video_vid_data => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_data, -- .vid_data
+ alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_alt_vip_itc_0_clocked_video_underflow, -- .underflow
+ alt_vip_itc_0_clocked_video_vid_datavalid => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_datavalid, -- .vid_datavalid
+ alt_vip_itc_0_clocked_video_vid_v_sync => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_v_sync, -- .vid_v_sync
+ alt_vip_itc_0_clocked_video_vid_h_sync => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_h_sync, -- .vid_h_sync
+ alt_vip_itc_0_clocked_video_vid_f => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_f, -- .vid_f
+ alt_vip_itc_0_clocked_video_vid_h => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_h, -- .vid_h
+ alt_vip_itc_0_clocked_video_vid_v => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_v, -- .vid_v
+ altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
+ altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
+ clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
+ clk_sdram_clk => CONNECTED_TO_clk_sdram_clk, -- clk_sdram.clk
+ clk_vga_clk => CONNECTED_TO_clk_vga_clk, -- clk_vga.clk
+ d8m_xclkin_clk => CONNECTED_TO_d8m_xclkin_clk, -- d8m_xclkin.clk
+ eee_imgproc_0_conduit_mode_new_signal => CONNECTED_TO_eee_imgproc_0_conduit_mode_new_signal, -- eee_imgproc_0_conduit_mode.new_signal
+ i2c_opencores_camera_export_scl_pad_io => CONNECTED_TO_i2c_opencores_camera_export_scl_pad_io, -- i2c_opencores_camera_export.scl_pad_io
+ i2c_opencores_camera_export_sda_pad_io => CONNECTED_TO_i2c_opencores_camera_export_sda_pad_io, -- .sda_pad_io
+ i2c_opencores_mipi_export_scl_pad_io => CONNECTED_TO_i2c_opencores_mipi_export_scl_pad_io, -- i2c_opencores_mipi_export.scl_pad_io
+ i2c_opencores_mipi_export_sda_pad_io => CONNECTED_TO_i2c_opencores_mipi_export_sda_pad_io, -- .sda_pad_io
+ key_external_connection_export => CONNECTED_TO_key_external_connection_export, -- key_external_connection.export
+ led_external_connection_export => CONNECTED_TO_led_external_connection_export, -- led_external_connection.export
+ mipi_pwdn_n_external_connection_export => CONNECTED_TO_mipi_pwdn_n_external_connection_export, -- mipi_pwdn_n_external_connection.export
+ mipi_reset_n_external_connection_export => CONNECTED_TO_mipi_reset_n_external_connection_export, -- mipi_reset_n_external_connection.export
+ reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
+ sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
+ sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
+ sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
+ sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
+ sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
+ sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
+ sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
+ sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
+ sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
+ sw_external_connection_export => CONNECTED_TO_sw_external_connection_export, -- sw_external_connection.export
+ terasic_auto_focus_0_conduit_vcm_i2c_sda => CONNECTED_TO_terasic_auto_focus_0_conduit_vcm_i2c_sda, -- terasic_auto_focus_0_conduit.vcm_i2c_sda
+ terasic_auto_focus_0_conduit_clk50 => CONNECTED_TO_terasic_auto_focus_0_conduit_clk50, -- .clk50
+ terasic_auto_focus_0_conduit_vcm_i2c_scl => CONNECTED_TO_terasic_auto_focus_0_conduit_vcm_i2c_scl, -- .vcm_i2c_scl
+ terasic_camera_0_conduit_end_D => CONNECTED_TO_terasic_camera_0_conduit_end_D, -- terasic_camera_0_conduit_end.D
+ terasic_camera_0_conduit_end_FVAL => CONNECTED_TO_terasic_camera_0_conduit_end_FVAL, -- .FVAL
+ terasic_camera_0_conduit_end_LVAL => CONNECTED_TO_terasic_camera_0_conduit_end_LVAL, -- .LVAL
+ terasic_camera_0_conduit_end_PIXCLK => CONNECTED_TO_terasic_camera_0_conduit_end_PIXCLK -- .PIXCLK
+ );
+
diff --git a/Vision/DE10_LITE_D8M_VIP_16/demo_batch/D8M_Camera_Test.elf b/Vision/DE10_LITE_D8M_VIP_16/demo_batch/D8M_Camera_Test.elf
new file mode 100644
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