Merge branch 'main' of https://github.com/supleed2/EE2Rover into main

This commit is contained in:
jc4419 2021-05-29 00:28:03 +04:00
commit 29d1ace16b
15 changed files with 8407 additions and 2293 deletions

View file

@ -827,7 +827,7 @@
<fullscreen-action>false</fullscreen-action> <fullscreen-action>false</fullscreen-action>
<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004"> <node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054"> <node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
<leaf id="1" nodeId="1375985003630"> <leaf id="2" nodeId="1375985003630">
<placeholders> <placeholders>
<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder> <placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
<placeholder>dock.single.IP\ Catalog</placeholder> <placeholder>dock.single.IP\ Catalog</placeholder>
@ -853,7 +853,7 @@
</entry> </entry>
</placeholder-map> </placeholder-map>
</leaf> </leaf>
<leaf id="2" nodeId="1375985011087"> <leaf id="1" nodeId="1375985011087">
<placeholders> <placeholders>
<placeholder>dock.single.Hierarchy</placeholder> <placeholder>dock.single.Hierarchy</placeholder>
</placeholders> </placeholders>
@ -880,7 +880,7 @@
<node nodeId="1372710005725" orientation="VERTICAL" divider="0.8051001821493625"> <node nodeId="1372710005725" orientation="VERTICAL" divider="0.8051001821493625">
<node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.8413566475001963"> <node nodeId="1372710005727" orientation="HORIZONTAL" divider="0.8413566475001963">
<node nodeId="1372710005733" orientation="VERTICAL" divider="0.75"> <node nodeId="1372710005733" orientation="VERTICAL" divider="0.75">
<leaf id="4" nodeId="1372710005735"> <leaf id="3" nodeId="1372710005735">
<placeholders> <placeholders>
<placeholder>dock.single.Connections</placeholder> <placeholder>dock.single.Connections</placeholder>
<placeholder>dock.single.System\ Contents</placeholder> <placeholder>dock.single.System\ Contents</placeholder>
@ -897,18 +897,12 @@
<placeholder>dock.single.Interconnect\ Requirements</placeholder> <placeholder>dock.single.Interconnect\ Requirements</placeholder>
<placeholder>dock.single.Instrumentation</placeholder> <placeholder>dock.single.Instrumentation</placeholder>
<placeholder>dock.single.Instance\ Parameters</placeholder> <placeholder>dock.single.Instance\ Parameters</placeholder>
<placeholder>dock.single.Address\ Map</placeholder>
<placeholder>dock.single.Domains</placeholder> <placeholder>dock.single.Domains</placeholder>
</placeholders> </placeholders>
<placeholder-map> <placeholder-map>
<version>0</version> <version>0</version>
<format>dock.PlaceholderList</format> <format>dock.PlaceholderList</format>
<entry>
<key shared="false">
<placeholder>dock.single.System\ Contents</placeholder>
</key>
<item key="convert" type="b">true</item>
<item key="convert-keys" type="a"/>
</entry>
<entry> <entry>
<key shared="false"> <key shared="false">
<placeholder>dock.single.Address\ Map</placeholder> <placeholder>dock.single.Address\ Map</placeholder>
@ -932,7 +926,7 @@
</leaf> </leaf>
</node> </node>
<node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162"> <node nodeId="1389812802503" orientation="VERTICAL" divider="0.6704331450094162">
<leaf id="3" nodeId="1389812800464"> <leaf id="4" nodeId="1389812800464">
<placeholders> <placeholders>
<placeholder>dock.single.Parameters</placeholder> <placeholder>dock.single.Parameters</placeholder>
<placeholder>dock.single.Details</placeholder> <placeholder>dock.single.Details</placeholder>
@ -1012,16 +1006,6 @@
</layout> </layout>
<children ignore="false"/> <children ignore="false"/>
</child> </child>
<child>
<layout factory="predefined" placeholder="dock.single.IP\ Catalog">
<replacement id="dockablesingle IP Catalog"/>
<delegate id="delegate_ccontrol backup factory id">
<id>IP Catalog</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
<child> <child>
<layout factory="delegate_StackDockStationFactory"> <layout factory="delegate_StackDockStationFactory">
<selected>0</selected> <selected>0</selected>
@ -1082,10 +1066,10 @@
</children> </children>
</child> </child>
<child> <child>
<layout factory="predefined" placeholder="dock.single.Parameters"> <layout factory="predefined" placeholder="dock.single.IP\ Catalog">
<replacement id="dockablesingle Parameters"/> <replacement id="dockablesingle IP Catalog"/>
<delegate id="delegate_ccontrol backup factory id"> <delegate id="delegate_ccontrol backup factory id">
<id>Parameters</id> <id>IP Catalog</id>
<area/> <area/>
</delegate> </delegate>
</layout> </layout>
@ -1093,7 +1077,7 @@
</child> </child>
<child> <child>
<layout factory="delegate_StackDockStationFactory"> <layout factory="delegate_StackDockStationFactory">
<selected>1</selected> <selected>0</selected>
<placeholders> <placeholders>
<version>0</version> <version>0</version>
<format>dock.PlaceholderList</format> <format>dock.PlaceholderList</format>
@ -1199,6 +1183,16 @@
</child> </child>
</children> </children>
</child> </child>
<child>
<layout factory="predefined" placeholder="dock.single.Parameters">
<replacement id="dockablesingle Parameters"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Parameters</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
</children> </children>
</root> </root>
<root name="ccontrol west"> <root name="ccontrol west">
@ -1617,9 +1611,21 @@
</entry> </entry>
<entry id="single Address Map" current="dock.mode.normal"> <entry id="single Address Map" current="dock.mode.normal">
<history> <history>
<mode>dock.mode.maximized</mode>
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
</history> </history>
<properties> <properties>
<property id="dock.mode.maximized">
<mode>dock.mode.maximized</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockFullScreenPropertyFactory"/>
<property factory="StackDockPropertyFactory">
<index>1</index>
<placeholder>dock.single.Address\ Map</placeholder>
</property>
</location>
</property>
<property id="dock.mode.normal"> <property id="dock.mode.normal">
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
<root>ccontrol center</root> <root>ccontrol center</root>
@ -1627,10 +1633,9 @@
<property factory="SplitDockPlaceholderProperty"> <property factory="SplitDockPlaceholderProperty">
<placeholder>dock.single.Address\ Map</placeholder> <placeholder>dock.single.Address\ Map</placeholder>
<backup-path> <backup-path>
<node location="RIGHT" size="0.8" id="1372710005721"/> <node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
<node location="TOP" size="0.75" id="1372710005725"/> <node location="TOP" size="0.8051001821493625" id="1372710005725"/>
<node location="LEFT" size="0.75" id="1372710005727"/> <node location="LEFT" size="0.8413566475001963" id="1372710005727"/>
<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
<node location="TOP" size="0.75" id="1372710005733"/> <node location="TOP" size="0.75" id="1372710005733"/>
<leaf id="1372710005735"/> <leaf id="1372710005735"/>
</backup-path> </backup-path>
@ -1847,9 +1852,21 @@
</entry> </entry>
<entry id="single System Contents" current="dock.mode.normal"> <entry id="single System Contents" current="dock.mode.normal">
<history> <history>
<mode>dock.mode.maximized</mode>
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
</history> </history>
<properties> <properties>
<property id="dock.mode.maximized">
<mode>dock.mode.maximized</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockFullScreenPropertyFactory"/>
<property factory="StackDockPropertyFactory">
<index>0</index>
<placeholder>dock.single.System\ Contents</placeholder>
</property>
</location>
</property>
<property id="dock.mode.normal"> <property id="dock.mode.normal">
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
<root>ccontrol center</root> <root>ccontrol center</root>
@ -1857,10 +1874,9 @@
<property factory="SplitDockPlaceholderProperty"> <property factory="SplitDockPlaceholderProperty">
<placeholder>dock.single.System\ Contents</placeholder> <placeholder>dock.single.System\ Contents</placeholder>
<backup-path> <backup-path>
<node location="RIGHT" size="0.8" id="1372710005721"/> <node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
<node location="TOP" size="0.75" id="1372710005725"/> <node location="TOP" size="0.8051001821493625" id="1372710005725"/>
<node location="LEFT" size="0.75" id="1372710005727"/> <node location="LEFT" size="0.8413566475001963" id="1372710005727"/>
<node location="RIGHT" size="0.6666666666666667" id="1372710005729"/>
<node location="TOP" size="0.75" id="1372710005733"/> <node location="TOP" size="0.75" id="1372710005733"/>
<leaf id="1372710005735"/> <leaf id="1372710005735"/>
</backup-path> </backup-path>
@ -1876,9 +1892,21 @@
<entry id="single Interconnect Requirements" current="dock.mode.normal"> <entry id="single Interconnect Requirements" current="dock.mode.normal">
<history> <history>
<mode>dock.mode.minimized</mode> <mode>dock.mode.minimized</mode>
<mode>dock.mode.maximized</mode>
<mode>dock.mode.normal</mode> <mode>dock.mode.normal</mode>
</history> </history>
<properties> <properties>
<property id="dock.mode.maximized">
<mode>dock.mode.maximized</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockFullScreenPropertyFactory"/>
<property factory="StackDockPropertyFactory">
<index>2</index>
<placeholder>dock.single.Interconnect\ Requirements</placeholder>
</property>
</location>
</property>
<property id="dock.mode.minimized"> <property id="dock.mode.minimized">
<mode>dock.mode.minimized</mode> <mode>dock.mode.minimized</mode>
<root>ccontrol north</root> <root>ccontrol north</root>
@ -1899,8 +1927,8 @@
<placeholder>dock.single.Interconnect\ Requirements</placeholder> <placeholder>dock.single.Interconnect\ Requirements</placeholder>
<backup-path> <backup-path>
<node location="RIGHT" size="0.7781885397412199" id="1372710005721"/> <node location="RIGHT" size="0.7781885397412199" id="1372710005721"/>
<node location="TOP" size="0.75" id="1372710005725"/> <node location="TOP" size="0.8051001821493625" id="1372710005725"/>
<node location="LEFT" size="0.6183193900785428" id="1372710005727"/> <node location="LEFT" size="0.8413566475001963" id="1372710005727"/>
<node location="TOP" size="0.75" id="1372710005733"/> <node location="TOP" size="0.75" id="1372710005733"/>
<leaf id="1372710005735"/> <leaf id="1372710005735"/>
</backup-path> </backup-path>
@ -2140,24 +2168,7 @@
</entry> </entry>
</dockables> </dockables>
<modes> <modes>
<entry id="dock.mode.maximized"> <entry id="dock.mode.maximized"/>
<maximized>
<item id="ccontrol center">
<mode>dock.mode.normal</mode>
<location>
<mode>dock.mode.normal</mode>
<root>ccontrol center</root>
<location>
<property factory="SplitDockPathProperty">
<node location="LEFT" size="0.22181146025878004" id="1372710005721"/>
<node location="TOP" size="0.504054054054054" id="1375985011088"/>
<leaf id="1375985003630"/>
</property>
</location>
</location>
</item>
</maximized>
</entry>
</modes> </modes>
</modes> </modes>
</current> </current>

View file

@ -2,53 +2,58 @@
# #
preplace inst Qsys.nios2_gen2.clock_bridge -pg 1 preplace inst Qsys.nios2_gen2.clock_bridge -pg 1
preplace inst Qsys.altpll_0 -pg 1 -lvl 3 -y 250 preplace inst Qsys.altpll_0 -pg 1 -lvl 3 -y 250
preplace inst Qsys.i2c_opencores_camera -pg 1 -lvl 7 -y 30 preplace inst Qsys.i2c_opencores_camera -pg 1 -lvl 8 -y 30
preplace inst Qsys.alt_vip_itc_0 -pg 1 -lvl 7 -y 810 preplace inst Qsys.alt_vip_itc_0 -pg 1 -lvl 8 -y 810
preplace inst Qsys.onchip_memory2_0 -pg 1 -lvl 7 -y 540 preplace inst Qsys.onchip_memory2_0 -pg 1 -lvl 8 -y 540
preplace inst Qsys.led -pg 1 -lvl 7 -y 1390 preplace inst Qsys.led -pg 1 -lvl 8 -y 1390
preplace inst Qsys.clk_50 -pg 1 -lvl 1 -y 720 preplace inst Qsys.clk_50 -pg 1 -lvl 1 -y 720
preplace inst Qsys.sysid_qsys -pg 1 -lvl 7 -y 1010 preplace inst Qsys.sysid_qsys -pg 1 -lvl 8 -y 1010
preplace inst Qsys.sdram -pg 1 -lvl 7 -y 910 preplace inst Qsys.sdram -pg 1 -lvl 8 -y 910
preplace inst Qsys.nios2_gen2.reset_bridge -pg 1 preplace inst Qsys.nios2_gen2.reset_bridge -pg 1
preplace inst Qsys.jtag_uart -pg 1 -lvl 7 -y 330 preplace inst Qsys.jtag_uart -pg 1 -lvl 8 -y 330
preplace inst Qsys.TERASIC_CAMERA_0 -pg 1 -lvl 4 -y 740 preplace inst Qsys.TERASIC_CAMERA_0 -pg 1 -lvl 4 -y 740
preplace inst Qsys.mipi_reset_n -pg 1 -lvl 7 -y 1190 preplace inst Qsys.mipi_reset_n -pg 1 -lvl 8 -y 1190
preplace inst Qsys.alt_vip_vfb_0 -pg 1 -lvl 5 -y 620 preplace inst Qsys.alt_vip_vfb_0 -pg 1 -lvl 5 -y 620
preplace inst Qsys -pg 1 -lvl 1 -y 40 -regy -20 preplace inst Qsys -pg 1 -lvl 1 -y 40 -regy -20
preplace inst Qsys.timer -pg 1 -lvl 7 -y 440 preplace inst Qsys.uart_interface_0 -pg 1 -lvl 2 -y 330
preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 7 -y 1090 preplace inst Qsys.EEE_IMGPROC_0 -pg 1 -lvl 7 -y 600
preplace inst Qsys.key -pg 1 -lvl 7 -y 620 preplace inst Qsys.timer -pg 1 -lvl 8 -y 440
preplace inst Qsys.sw -pg 1 -lvl 7 -y 1290 preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 8 -y 1090
preplace inst Qsys.key -pg 1 -lvl 8 -y 620
preplace inst Qsys.sw -pg 1 -lvl 8 -y 1290
preplace inst Qsys.TERASIC_AUTO_FOCUS_0 -pg 1 -lvl 6 -y 560 preplace inst Qsys.TERASIC_AUTO_FOCUS_0 -pg 1 -lvl 6 -y 560
preplace inst Qsys.nios2_gen2.cpu -pg 1 preplace inst Qsys.nios2_gen2.cpu -pg 1
preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 470 preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 520
preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 7 -y 170 preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 8 -y 170
preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)sdram.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)led.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)mipi_pwdn_n.reset,(MASTER)clk_50.clk_reset,(SLAVE)mipi_reset_n.reset,(SLAVE)sysid_qsys.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)sw.reset,(SLAVE)key.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)nios2_gen2.reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)jtag_uart.reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(SLAVE)timer.reset) 1 1 6 430 670 870 530 1170 730 1650 730 1890 800 2230 preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)altpll_0.c1,(MASTER)Qsys.clk_sdram) 1 3 6 NJ 280 NJ 280 NJ 280 NJ 280 NJ 300 NJ
preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)alt_vip_itc_0.din,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 2190 preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)sysid_qsys.control_slave,(SLAVE)timer.s1,(MASTER)nios2_gen2.instruction_master,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)altpll_0.pll_slave,(SLAVE)nios2_gen2.debug_mem_slave,(SLAVE)led.s1,(SLAVE)EEE_IMGPROC_0.s1,(SLAVE)mipi_pwdn_n.s1,(SLAVE)i2c_opencores_mipi.avalon_slave_0,(MASTER)nios2_gen2.data_master,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(SLAVE)sw.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)onchip_memory2_0.s1,(SLAVE)mipi_reset_n.s1,(SLAVE)key.s1) 1 1 7 450 420 850 810 NJ 710 NJ 710 1910 730 2190 770 2580
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)clk_50.clk_in_reset,(SLAVE)Qsys.reset) 1 0 1 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 8 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 7 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)led.external_connection,(SLAVE)Qsys.led_external_connection) 1 0 8 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)sdram.wire,(SLAVE)Qsys.sdram_wire) 1 0 7 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.eee_imgproc_0_conduit_mode,(SLAVE)EEE_IMGPROC_0.conduit_mode) 1 0 7 NJ 300 NJ 300 NJ 410 NJ 410 NJ 410 NJ 410 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)led.external_connection,(SLAVE)Qsys.led_external_connection) 1 0 7 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.altpll_0_locked_conduit,(SLAVE)altpll_0.locked_conduit) 1 0 3 NJ 280 NJ 280 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.clk_sdram,(MASTER)altpll_0.c1) 1 3 5 NJ 210 NJ 210 NJ 210 NJ 160 NJ preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)mipi_pwdn_n.clk,(SLAVE)i2c_opencores_camera.clock,(SLAVE)key.clk,(SLAVE)onchip_memory2_0.clk1,(MASTER)clk_50.clk,(SLAVE)jtag_uart.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)nios2_gen2.clk,(SLAVE)sysid_qsys.clk,(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)led.clk,(SLAVE)sw.clk,(SLAVE)timer.clk,(SLAVE)uart_interface_0.clock) 1 1 7 410 320 950 380 NJ 340 NJ 300 NJ 300 NJ 300 2640
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.altpll_0_locked_conduit,(SLAVE)altpll_0.locked_conduit) 1 0 3 NJ 410 NJ 410 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.sdram_wire,(SLAVE)sdram.wire) 1 0 8 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit,(SLAVE)Qsys.terasic_auto_focus_0_conduit) 1 0 6 NJ 630 NJ 630 NJ 570 NJ 570 NJ 570 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)mipi_pwdn_n.external_connection,(SLAVE)Qsys.mipi_pwdn_n_external_connection) 1 0 8 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)altpll_0.areset_conduit,(SLAVE)Qsys.altpll_0_areset_conduit) 1 0 3 NJ 260 NJ 260 NJ preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)sdram.clk,(SLAVE)alt_vip_itc_0.is_clk_rst,(MASTER)altpll_0.c2,(SLAVE)TERASIC_CAMERA_0.clock_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)EEE_IMGPROC_0.clock,(SLAVE)alt_vip_vfb_0.clock) 1 3 5 1250 300 1670 730 1870 690 2150 860 2600
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)mipi_reset_n.external_connection,(SLAVE)Qsys.mipi_reset_n_external_connection) 1 0 7 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.uart_interface_0_conduit_end,(SLAVE)uart_interface_0.conduit_end) 1 0 2 NJ 360 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.sw_external_connection,(SLAVE)sw.external_connection) 1 0 7 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(MASTER)EEE_IMGPROC_0.avalon_streaming_source,(SLAVE)alt_vip_itc_0.din) 1 7 1 2600
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.mipi_pwdn_n_external_connection,(SLAVE)mipi_pwdn_n.external_connection) 1 0 7 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.terasic_auto_focus_0_conduit,(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit) 1 0 6 NJ 460 NJ 460 NJ 570 NJ 570 NJ 570 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.clk_vga,(MASTER)altpll_0.c3) 1 3 5 NJ 360 NJ 360 NJ 360 NJ 320 NJ preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)i2c_opencores_camera.interrupt_sender,(SLAVE)jtag_uart.irq,(MASTER)nios2_gen2.irq,(SLAVE)timer.irq) 1 2 6 NJ 870 NJ 870 NJ 790 NJ 790 NJ 790 2620
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)key.external_connection,(SLAVE)Qsys.key_external_connection) 1 0 7 NJ 650 NJ 650 NJ 650 NJ 650 NJ 750 NJ 750 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)key.external_connection,(SLAVE)Qsys.key_external_connection) 1 0 8 NJ 710 NJ 710 NJ 830 NJ 730 NJ 770 NJ 750 NJ 750 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 7 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 8 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.alt_vip_itc_0_clocked_video,(SLAVE)alt_vip_itc_0.clocked_video) 1 0 7 NJ 830 NJ 830 NJ 830 NJ 830 NJ 820 NJ 820 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.alt_vip_itc_0_clocked_video,(SLAVE)alt_vip_itc_0.clocked_video) 1 0 8 NJ 890 NJ 890 NJ 890 NJ 890 NJ 820 NJ 820 NJ 820 NJ
preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)sdram.clk,(SLAVE)alt_vip_itc_0.is_clk_rst,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)alt_vip_vfb_0.clock,(SLAVE)TERASIC_CAMERA_0.clock_reset,(MASTER)altpll_0.c2) 1 3 4 1190 340 1630 710 1870 780 2150 preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)TERASIC_AUTO_FOCUS_0.din,(MASTER)alt_vip_vfb_0.dout) 1 5 1 1890
preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)TERASIC_AUTO_FOCUS_0.din,(MASTER)alt_vip_vfb_0.dout) 1 5 1 1830 preplace netloc FAN_IN<net_container>Qsys</net_container>(SLAVE)sdram.s1,(MASTER)alt_vip_vfb_0.write_master,(MASTER)alt_vip_vfb_0.read_master) 1 5 3 1890 960 NJ 960 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)clk_50.clk_in,(SLAVE)Qsys.clk) 1 0 1 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)clk_50.clk_in,(SLAVE)Qsys.clk) 1 0 1 NJ
preplace netloc FAN_IN<net_container>Qsys</net_container>(MASTER)alt_vip_vfb_0.read_master,(MASTER)alt_vip_vfb_0.write_master,(SLAVE)sdram.s1) 1 5 2 1830 960 NJ preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)EEE_IMGPROC_0.avalon_streaming_sink,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 N
preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)jtag_uart.irq,(SLAVE)timer.irq,(MASTER)nios2_gen2.irq,(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)i2c_opencores_camera.interrupt_sender) 1 2 5 NJ 550 NJ 550 NJ 550 NJ 550 2170 preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(SLAVE)alt_vip_vfb_0.din,(MASTER)TERASIC_CAMERA_0.avalon_streaming_source) 1 4 1 1630
preplace netloc POINT_TO_POINT<net_container>Qsys</net_container>(MASTER)TERASIC_CAMERA_0.avalon_streaming_source,(SLAVE)alt_vip_vfb_0.din) 1 4 1 1610 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)sw.external_connection,(SLAVE)Qsys.sw_external_connection) 1 0 8 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.d8m_xclkin,(MASTER)altpll_0.c4) 1 3 5 NJ 380 NJ 380 NJ 380 NJ 300 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.mipi_reset_n_external_connection,(SLAVE)mipi_reset_n.external_connection) 1 0 8 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ
preplace netloc FAN_OUT<net_container>Qsys</net_container>(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_camera.clock,(SLAVE)led.clk,(SLAVE)onchip_memory2_0.clk1,(SLAVE)timer.clk,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)sw.clk,(SLAVE)sysid_qsys.clk,(SLAVE)mipi_pwdn_n.clk,(SLAVE)nios2_gen2.clk,(SLAVE)jtag_uart.clk,(MASTER)clk_50.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)key.clk) 1 1 6 410 430 850 400 NJ 400 NJ 400 NJ 400 2210 preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)altpll_0.c3,(MASTER)Qsys.clk_vga) 1 3 6 NJ 320 NJ 320 NJ 320 NJ 320 NJ 320 NJ
preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)altpll_0.pll_slave,(SLAVE)led.s1,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)i2c_opencores_mipi.avalon_slave_0,(SLAVE)mipi_reset_n.s1,(MASTER)nios2_gen2.data_master,(SLAVE)sysid_qsys.control_slave,(SLAVE)timer.s1,(SLAVE)sw.s1,(SLAVE)onchip_memory2_0.s1,(SLAVE)key.s1,(SLAVE)mipi_pwdn_n.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(MASTER)nios2_gen2.instruction_master,(SLAVE)nios2_gen2.debug_mem_slave) 1 1 6 450 610 890 510 NJ 510 NJ 510 1850 690 2130 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.altpll_0_areset_conduit,(SLAVE)altpll_0.areset_conduit) 1 0 3 NJ 260 NJ 260 NJ
preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.terasic_camera_0_conduit_end,(SLAVE)TERASIC_CAMERA_0.conduit_end) 1 0 4 NJ 790 NJ 790 NJ 790 NJ preplace netloc EXPORT<net_container>Qsys</net_container>(MASTER)Qsys.d8m_xclkin,(MASTER)altpll_0.c4) 1 3 6 NJ 220 NJ 220 NJ 220 NJ 220 NJ 160 NJ
levelinfo -pg 1 0 200 2570 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.terasic_camera_0_conduit_end,(SLAVE)TERASIC_CAMERA_0.conduit_end) 1 0 4 NJ 480 NJ 480 NJ 790 NJ
levelinfo -hier Qsys 210 240 590 980 1300 1680 1980 2320 2470 preplace netloc EXPORT<net_container>Qsys</net_container>(SLAVE)Qsys.reset,(SLAVE)clk_50.clk_in_reset) 1 0 1 NJ
preplace netloc INTERCONNECT<net_container>Qsys</net_container>(SLAVE)sw.reset,(SLAVE)timer.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)key.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)uart_interface_0.reset,(SLAVE)mipi_pwdn_n.reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)led.reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(MASTER)clk_50.clk_reset,(SLAVE)jtag_uart.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)EEE_IMGPROC_0.reset,(SLAVE)sysid_qsys.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)sdram.reset,(SLAVE)nios2_gen2.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)mipi_reset_n.reset) 1 1 7 430 440 910 850 1290 690 1690 750 1930 710 2170 880 2680
levelinfo -pg 1 0 200 3000
levelinfo -hier Qsys 210 240 590 1020 1340 1720 2020 2320 2750 2900

View file

@ -9,6 +9,6 @@
<export preferredWidth="267" /> <export preferredWidth="267" />
</columns> </columns>
</systemtable> </systemtable>
<library expandedCategories="Project,Library" /> <library expandedCategories="Library,Project" />
<window width="1971" height="1159" x="8" y="31" /> <window width="1694" height="929" x="136" y="110" />
</preferences> </preferences>

View file

@ -176,8 +176,17 @@ Qsys u0 (
.altpll_0_locked_conduit_export (), // altpll_0_locked_conduit.export .altpll_0_locked_conduit_export (), // altpll_0_locked_conduit.export
.altpll_0_phasedone_conduit_export (), // altpll_0_phasedone_conduit.export .altpll_0_phasedone_conduit_export (), // altpll_0_phasedone_conduit.export
.eee_imgproc_0_conduit_mode_new_signal (SW[0]) .eee_imgproc_0_conduit_mode_new_signal (SW[0]),
);
// .uart_interface_0_conduit_end_rx (ARDUINO_IO[13]), // input from ESP32 RX2pin
// .uart_interface_0_conduit_end_rx_data (), // output [7:0]
// .uart_interface_0_conduit_end_rx_valid (), // output
//
// .uart_interface_0_conduit_end_tx (ARDUINO_IO[12]), // output to ESP32 TX2pin
// .uart_interface_0_conduit_end_tx_data (), // input [7:0]
// .uart_interface_0_conduit_end_tx_transmit (), // input
// .uart_interface_0_conduit_end_tx_ready () // output
);
FpsMonitor uFps( FpsMonitor uFps(
.clk50(MAX10_CLK2_50), .clk50(MAX10_CLK2_50),

File diff suppressed because one or more lines are too long

View file

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="Qsys" kind="Qsys" version="1.0" fabric="QSYS"> <EnsembleReport name="Qsys" kind="Qsys" version="1.0" fabric="QSYS">
<!-- Format version 16.1 196 (Future versions may contain additional information.) --> <!-- Format version 16.1 196 (Future versions may contain additional information.) -->
<!-- 2021.05.14.17:00:07 --> <!-- 2021.05.27.19:53:21 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1621008007</value> <value>1622141601</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -17573,7 +17573,7 @@ the requested settings for a module instance. -->
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.TIMESTAMP</name> <name>embeddedsw.CMacro.TIMESTAMP</name>
<value>1621008007</value> <value>1622141601</value>
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.dts.compatible</name> <name>embeddedsw.dts.compatible</name>
@ -17593,7 +17593,7 @@ the requested settings for a module instance. -->
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.dts.params.timestamp</name> <name>embeddedsw.dts.params.timestamp</name>
<value>1621008007</value> <value>1622141601</value>
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.dts.vendor</name> <name>embeddedsw.dts.vendor</name>
@ -17609,7 +17609,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="timestamp"> <parameter name="timestamp">
<type>int</type> <type>int</type>
<value>1621008007</value> <value>1622141601</value>
<derived>true</derived> <derived>true</derived>
<enabled>false</enabled> <enabled>false</enabled>
<visible>false</visible> <visible>false</visible>

View file

@ -4,18 +4,18 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur. the Block Editor! File corruption is VERY likely to occur.
*/ */
/* /*
Copyright (C) 1991-2016 Altera Corporation. All rights reserved. Copyright (C) 2016 Intel Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing functions, and any output files from any of the foregoing
(including device programming or simulation files), and any (including device programming or simulation files), and any
associated documentation or information are expressly subject associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License to the terms and conditions of the Intel Program License
Subscription Agreement, the Altera Quartus Prime License Agreement, Subscription Agreement, the Intel Quartus Prime License Agreement,
the Altera MegaCore Function License Agreement, or other the Intel MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation, applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its devices manufactured by Intel and sold by Intel or its
authorized distributors. Please refer to the applicable authorized distributors. Please refer to the applicable
agreement for further details. agreement for further details.
*/ */
@ -380,7 +380,7 @@ agreement for further details.
(text "FVAL" (rect 245 1003 514 2016)(font "Arial" (color 0 0 0))) (text "FVAL" (rect 245 1003 514 2016)(font "Arial" (color 0 0 0)))
(text "LVAL" (rect 245 1019 514 2048)(font "Arial" (color 0 0 0))) (text "LVAL" (rect 245 1019 514 2048)(font "Arial" (color 0 0 0)))
(text "PIXCLK" (rect 245 1035 526 2080)(font "Arial" (color 0 0 0))) (text "PIXCLK" (rect 245 1035 526 2080)(font "Arial" (color 0 0 0)))
(text " system " (rect 541 1056 1130 2122)(font "Arial" )) (text " Qsys " (rect 550 1056 1136 2122)(font "Arial" ))
(line (pt 240 32)(pt 336 32)(line_width 1)) (line (pt 240 32)(pt 336 32)(line_width 1))
(line (pt 336 32)(pt 336 1056)(line_width 1)) (line (pt 336 32)(pt 336 1056)(line_width 1))
(line (pt 240 1056)(pt 336 1056)(line_width 1)) (line (pt 240 1056)(pt 336 1056)(line_width 1))

File diff suppressed because one or more lines are too long

File diff suppressed because one or more lines are too long

View file

@ -1,7 +1,9 @@
Info: Starting: Create block symbol file (.bsf) Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --block-symbol-file --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys" --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -10,35 +12,35 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.0] Progress: Adding altpll_0 [altpll 16.1]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.0] Progress: Adding clk_50 [clock_source 16.1]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.0] Progress: Adding key [altera_avalon_pio 16.1]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.0] Progress: Adding led [altera_avalon_pio 16.1]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] Progress: Adding mipi_reset_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.0] Progress: Adding sw [altera_avalon_pio 16.1]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.0] Progress: Adding timer [altera_avalon_timer 16.1]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
@ -47,6 +49,7 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
@ -54,9 +57,11 @@ Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf) Info: Finished: Create block symbol file (.bsf)
Info: Info:
Info: Starting: Create HDL design files for synthesis Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --synthesis=VERILOG --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys\synthesis" --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -65,35 +70,35 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.0] Progress: Adding altpll_0 [altpll 16.1]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.0] Progress: Adding clk_50 [clock_source 16.1]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.0] Progress: Adding key [altera_avalon_pio 16.1]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.0] Progress: Adding led [altera_avalon_pio 16.1]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] Progress: Adding mipi_reset_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.0] Progress: Adding sw [altera_avalon_pio 16.1]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.0] Progress: Adding timer [altera_avalon_timer 16.1]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
@ -102,28 +107,167 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0 Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
Info: Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
Info: Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14
Info: EEE_IMGPROC_0: "Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"
Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0" Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0" Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0" Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0" Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092322619640" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing
Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 1399 megabytes
Error: Processing ended: Tue Mar 30 09:18:43 2021
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:00
Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory)
Info: altpll_0: "Qsys" instantiated altpll "altpll_0" Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
Error: Generation stopped, 218 or more modules remaining Info: i2c_opencores_camera: "Qsys" instantiated i2c_opencores "i2c_opencores_camera"
Info: Qsys: Done "Qsys" with 33 modules, 34 files Info: jtag_uart: Starting RTL generation for module 'Qsys_jtag_uart'
Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning Info: jtag_uart: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ]
Info: jtag_uart: Done RTL generation for module 'Qsys_jtag_uart'
Info: jtag_uart: "Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: key: Starting RTL generation for module 'Qsys_key'
Info: key: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ]
Info: key: Done RTL generation for module 'Qsys_key'
Info: key: "Qsys" instantiated altera_avalon_pio "key"
Info: led: Starting RTL generation for module 'Qsys_led'
Info: led: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ]
Info: led: Done RTL generation for module 'Qsys_led'
Info: led: "Qsys" instantiated altera_avalon_pio "led"
Info: mipi_pwdn_n: Starting RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ]
Info: mipi_pwdn_n: Done RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: "Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"
Info: nios2_gen2: "Qsys" instantiated altera_nios2_gen2 "nios2_gen2"
Info: onchip_memory2_0: Starting RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ]
Info: onchip_memory2_0: Done RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: "Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: sdram: Starting RTL generation for module 'Qsys_sdram'
Info: sdram: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ]
Info: sdram: Done RTL generation for module 'Qsys_sdram'
Info: sdram: "Qsys" instantiated altera_avalon_new_sdram_controller "sdram"
Info: sw: Starting RTL generation for module 'Qsys_sw'
Info: sw: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ]
Info: sw: Done RTL generation for module 'Qsys_sw'
Info: sw: "Qsys" instantiated altera_avalon_pio "sw"
Info: sysid_qsys: "Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"
Info: timer: Starting RTL generation for module 'Qsys_timer'
Info: timer: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ]
Info: timer: Done RTL generation for module 'Qsys_timer'
Info: timer: "Qsys" instantiated altera_avalon_timer "timer"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: irq_mapper: "Qsys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "Qsys" instantiated altera_reset_controller "rst_controller"
Info: vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"
Info: vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"
Info: vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"
Info: din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: fu_id_4494_line325_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: cpu: Starting RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ]
Info: cpu: # 2021.05.27 17:51:00 (*) Starting Nios II generation
Info: cpu: # 2021.05.27 17:51:00 (*) Checking for plaintext license.
Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:51:01 (*) Plaintext license not found.
Info: cpu: # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation).
Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF)
Info: cpu: # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings
Info: cpu: # 2021.05.27 17:51:01 (*) Creating all objects for CPU
Info: cpu: # 2021.05.27 17:51:01 (*) Testbench
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decoding
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction fields
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decodes
Info: cpu: # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms
Info: cpu: # 2021.05.27 17:51:02 (*) Instruction controls
Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline frontend
Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline backend
Info: cpu: # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects
Info: cpu: # 2021.05.27 17:51:06 (*) Creating encrypted RTL
Info: cpu: # 2021.05.27 17:51:07 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: "nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_gen2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"
Info: jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"
Info: nios2_gen2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"
Info: jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"
Info: jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_006: "mm_interconnect_0" instantiated altera_merlin_router "router_006"
Info: nios2_gen2_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_004: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"
Info: rsp_demux_005: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
Info: sdram_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: sdram_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: Qsys: Done "Qsys" with 67 modules, 142 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis Info: Finished: Create HDL design files for synthesis

View file

@ -1,7 +1,9 @@
Info: Starting: Create block symbol file (.bsf) Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --block-symbol-file --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys" --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -10,36 +12,38 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.0] Progress: Adding altpll_0 [altpll 16.1]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.0] Progress: Adding clk_50 [clock_source 16.1]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.0] Progress: Adding key [altera_avalon_pio 16.1]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.0] Progress: Adding led [altera_avalon_pio 16.1]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] Progress: Adding mipi_reset_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.0] Progress: Adding sw [altera_avalon_pio 16.1]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.0] Progress: Adding timer [altera_avalon_timer 16.1]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Adding uart_interface_0 [uart_interface 1.0]
Progress: Parameterizing module uart_interface_0
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
Progress: Validating Progress: Validating
@ -47,6 +51,7 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
@ -54,9 +59,11 @@ Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf) Info: Finished: Create block symbol file (.bsf)
Info: Info:
Info: Starting: Create HDL design files for synthesis Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --synthesis=VERILOG --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys\synthesis" --family="MAX 10" --part=10M50DAF484C7G
Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys
Progress: Reading input file Progress: Reading input file
Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0]
Progress: Parameterizing module EEE_IMGPROC_0
Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0]
Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Parameterizing module TERASIC_AUTO_FOCUS_0
Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0]
@ -65,36 +72,38 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0]
Progress: Parameterizing module alt_vip_itc_0 Progress: Parameterizing module alt_vip_itc_0
Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1]
Progress: Parameterizing module alt_vip_vfb_0 Progress: Parameterizing module alt_vip_vfb_0
Progress: Adding altpll_0 [altpll 16.0] Progress: Adding altpll_0 [altpll 16.1]
Progress: Parameterizing module altpll_0 Progress: Parameterizing module altpll_0
Progress: Adding clk_50 [clock_source 16.0] Progress: Adding clk_50 [clock_source 16.1]
Progress: Parameterizing module clk_50 Progress: Parameterizing module clk_50
Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Adding i2c_opencores_camera [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_camera Progress: Parameterizing module i2c_opencores_camera
Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0]
Progress: Parameterizing module i2c_opencores_mipi Progress: Parameterizing module i2c_opencores_mipi
Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1]
Progress: Parameterizing module jtag_uart Progress: Parameterizing module jtag_uart
Progress: Adding key [altera_avalon_pio 16.0] Progress: Adding key [altera_avalon_pio 16.1]
Progress: Parameterizing module key Progress: Parameterizing module key
Progress: Adding led [altera_avalon_pio 16.0] Progress: Adding led [altera_avalon_pio 16.1]
Progress: Parameterizing module led Progress: Parameterizing module led
Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_pwdn_n Progress: Parameterizing module mipi_pwdn_n
Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] Progress: Adding mipi_reset_n [altera_avalon_pio 16.1]
Progress: Parameterizing module mipi_reset_n Progress: Parameterizing module mipi_reset_n
Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1]
Progress: Parameterizing module nios2_gen2 Progress: Parameterizing module nios2_gen2
Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1]
Progress: Parameterizing module onchip_memory2_0 Progress: Parameterizing module onchip_memory2_0
Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1]
Progress: Parameterizing module sdram Progress: Parameterizing module sdram
Progress: Adding sw [altera_avalon_pio 16.0] Progress: Adding sw [altera_avalon_pio 16.1]
Progress: Parameterizing module sw Progress: Parameterizing module sw
Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1]
Progress: Parameterizing module sysid_qsys Progress: Parameterizing module sysid_qsys
Progress: Adding timer [altera_avalon_timer 16.0] Progress: Adding timer [altera_avalon_timer 16.1]
Progress: Parameterizing module timer Progress: Parameterizing module timer
Progress: Adding uart_interface_0 [uart_interface 1.0]
Progress: Parameterizing module uart_interface_0
Progress: Building connections Progress: Building connections
Progress: Parameterizing connections Progress: Parameterizing connections
Progress: Validating Progress: Validating
@ -102,28 +111,168 @@ Progress: Done reading input file
Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II.
Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated.
Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH
Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0 Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0
Info: Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0
Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5
Info: Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14
Info: EEE_IMGPROC_0: "Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"
Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0" Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"
Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0" Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"
Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0" Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0"
Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0" Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"
Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally
Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092145442977" ("eval" body line 1) invoked from within "eval exec $cbx_cmd "
Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v is missing
Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 1399 megabytes
Error: Processing ended: Tue Mar 30 09:15:46 2021
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:00
Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0
Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v (No such file or directory)
Info: altpll_0: "Qsys" instantiated altpll "altpll_0" Info: altpll_0: "Qsys" instantiated altpll "altpll_0"
Error: Generation stopped, 218 or more modules remaining Info: i2c_opencores_camera: "Qsys" instantiated i2c_opencores "i2c_opencores_camera"
Info: Qsys: Done "Qsys" with 33 modules, 34 files Info: jtag_uart: Starting RTL generation for module 'Qsys_jtag_uart'
Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning Info: jtag_uart: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0012_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0012_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ]
Info: jtag_uart: Done RTL generation for module 'Qsys_jtag_uart'
Info: jtag_uart: "Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"
Info: key: Starting RTL generation for module 'Qsys_key'
Info: key: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0013_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0013_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ]
Info: key: Done RTL generation for module 'Qsys_key'
Info: key: "Qsys" instantiated altera_avalon_pio "key"
Info: led: Starting RTL generation for module 'Qsys_led'
Info: led: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0014_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0014_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ]
Info: led: Done RTL generation for module 'Qsys_led'
Info: led: "Qsys" instantiated altera_avalon_pio "led"
Info: mipi_pwdn_n: Starting RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0015_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0015_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ]
Info: mipi_pwdn_n: Done RTL generation for module 'Qsys_mipi_pwdn_n'
Info: mipi_pwdn_n: "Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"
Info: nios2_gen2: "Qsys" instantiated altera_nios2_gen2 "nios2_gen2"
Info: onchip_memory2_0: Starting RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0016_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0016_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ]
Info: onchip_memory2_0: Done RTL generation for module 'Qsys_onchip_memory2_0'
Info: onchip_memory2_0: "Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"
Info: sdram: Starting RTL generation for module 'Qsys_sdram'
Info: sdram: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0017_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0017_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ]
Info: sdram: Done RTL generation for module 'Qsys_sdram'
Info: sdram: "Qsys" instantiated altera_avalon_new_sdram_controller "sdram"
Info: sw: Starting RTL generation for module 'Qsys_sw'
Info: sw: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0018_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0018_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ]
Info: sw: Done RTL generation for module 'Qsys_sw'
Info: sw: "Qsys" instantiated altera_avalon_pio "sw"
Info: sysid_qsys: "Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"
Info: timer: Starting RTL generation for module 'Qsys_timer'
Info: timer: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0020_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0020_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ]
Info: timer: Done RTL generation for module 'Qsys_timer'
Info: timer: "Qsys" instantiated altera_avalon_timer "timer"
Info: uart_interface_0: "Qsys" instantiated uart_interface "uart_interface_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_1: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"
Info: irq_mapper: "Qsys" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "Qsys" instantiated altera_reset_controller "rst_controller"
Info: vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"
Info: vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"
Info: vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"
Info: din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: fu_id_4494_line325_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd
Info: cpu: Starting RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0024_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0024_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ]
Info: cpu: # 2021.05.27 17:14:55 (*) Starting Nios II generation
Info: cpu: # 2021.05.27 17:14:55 (*) Checking for plaintext license.
Info: cpu: # 2021.05.27 17:14:55 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:14:55 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:14:55 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:14:55 (*) Plaintext license not found.
Info: cpu: # 2021.05.27 17:14:55 (*) Checking for encrypted license (non-evaluation).
Info: cpu: # 2021.05.27 17:14:56 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/
Info: cpu: # 2021.05.27 17:14:56 (*) Defaulting to contents of LM_LICENSE_FILE environment variable
Info: cpu: # 2021.05.27 17:14:56 (*) LM_LICENSE_FILE environment variable is empty
Info: cpu: # 2021.05.27 17:14:56 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF)
Info: cpu: # 2021.05.27 17:14:56 (*) Elaborating CPU configuration settings
Info: cpu: # 2021.05.27 17:14:56 (*) Creating all objects for CPU
Info: cpu: # 2021.05.27 17:14:56 (*) Testbench
Info: cpu: # 2021.05.27 17:14:56 (*) Instruction decoding
Info: cpu: # 2021.05.27 17:14:56 (*) Instruction fields
Info: cpu: # 2021.05.27 17:14:56 (*) Instruction decodes
Info: cpu: # 2021.05.27 17:14:57 (*) Signals for RTL simulation waveforms
Info: cpu: # 2021.05.27 17:14:57 (*) Instruction controls
Info: cpu: # 2021.05.27 17:14:57 (*) Pipeline frontend
Info: cpu: # 2021.05.27 17:14:57 (*) Pipeline backend
Info: cpu: # 2021.05.27 17:14:59 (*) Generating RTL from CPU objects
Info: cpu: # 2021.05.27 17:15:00 (*) Creating encrypted RTL
Info: cpu: # 2021.05.27 17:15:01 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'Qsys_nios2_gen2_cpu'
Info: cpu: "nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_gen2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"
Info: jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"
Info: nios2_gen2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"
Info: jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"
Info: jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_006: "mm_interconnect_0" instantiated altera_merlin_router "router_006"
Info: nios2_gen2_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_004: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"
Info: rsp_demux_005: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router"
Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002"
Info: sdram_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v
Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv
Info: sdram_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv
Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: Qsys: Done "Qsys" with 68 modules, 143 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis Info: Finished: Create HDL design files for synthesis

View file

@ -72,13 +72,25 @@ parameter BB_COL_DEFAULT = 24'h00ff00;
wire [7:0] red, green, blue, grey; wire [7:0] red, green, blue, grey;
wire [7:0] red_out, green_out, blue_out; wire [7:0] red_out, green_out, blue_out;
wire [8:0] hue;
wire [7:0] saturation, value;
wire sop, eop, in_valid, out_ready; wire sop, eop, in_valid, out_ready;
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
// RGB --> HSV Conversion
wire [7:0] min, max, delta;
assign min = (red < green) ? ((red < blue) ? red : blue) : ((green < blue) ? green : blue);
assign max = (red > green) ? ((red > blue) ? red : blue) : ((green > blue) ? green : blue);
assign delta = max - min;
assign hue = (red == max) ? (green - blue)/delta : ((green == max) ? 8'h55+((blue - red)/delta) : 8'haa+((red - green)/delta));
assign saturation = (max == 8'h00) ? 8'h00 : delta / max;
assign value = max;
// Detect red areas // Detect red areas
wire red_detect; wire red_detect;
assign red_detect = red[7] & ~green[7] & ~blue[7]; //assign red_detect = red[7] & ~green[7] & ~blue[7];
assign red_detect = blue[7];
// Find boundary of cursor box // Find boundary of cursor box

View file

@ -0,0 +1,273 @@
/*
Source: https://github.com/hildebrandmw/de10lite-hdl/blob/master/components/uart/hdl/uart.v
Description: Very simple UART tx/rx module. Requires a streaming interface,
provides no buffering for input or output data.
*/
module uart
#( parameter CLK_FREQ = 50_000_000,
parameter BAUD = 115_200
)
( input clk,
input reset,
// Receiving
input rx, // Received serial stream
output reg [7:0] rx_data, // Deserialized byte.
output rx_valid, // Asserted when rx_data is valid
// Transmitting
output reg tx, // Transmitted serial stream
input [7:0] tx_data, // Deserialized byte to transmit.
input tx_transmit, // Start Signal. No effect if tx_ready = 0
output reg tx_ready // Asserted when ready to accept data
);
///////////////////////////////
// Functionality Description //
///////////////////////////////
/*
RECEIVING: Module receives a serial stream through the port rx.
When a byte has been successfully received, the received data will be
available on the output port rx_data and the output port rx_valid will be
asserted for 1 clock cycle.
Validity of output data is not guaranteed if rx_valid is not 1. If this
is important for you, you may modify this design to register the output.
TRANSMITTING: When input port tx_transmit is 1 (asserted), module will
store the data on the input port tx_data and serialize through the output
port tx.
Module will only save and transmit the data at tx_data if the signal
tx_ready is asserted when tx_transmit is asserted. This module will not
buffer input data. While transmitting, tx_ready is deasserted and the
input port tx_transmit will have no effect.
Once tx_ready is deasserted, data at port tx_data is not used and need
not be stable.
*/
/////////////////////////
// Signal Declarations //
/////////////////////////
// ---------------------- //
// -- Local Parameters -- //
// ---------------------- //
// Number of synchronization stages to avoid metastability
localparam SYNC_STAGES = 2;
// Over Sampling Factor
localparam OSF = 16;
// Compute count to generate local clock enable
localparam CLK_DIV_COUNT = CLK_FREQ / (OSF * BAUD);
// ---------------------------- //
// -- Clock Dividing Counter -- //
// ---------------------------- //
reg [15:0] count;
reg enable; // Local Clock Enable
// -- RX Synchronizer --
reg [SYNC_STAGES-1:0] rx_sync;
reg rx_internal;
// ---------------- //
// -- RX Signals -- //
// ---------------- //
// State Machine Assignments
localparam RX_WAIT = 0;
localparam RX_CHECK_START = 1;
localparam RX_RECEIVING = 2;
localparam RX_WAIT_FOR_STOP = 3;
localparam RX_INITIAL_STATE = RX_WAIT;
reg [1:0] rx_state = RX_INITIAL_STATE;
reg [4:0] rx_count; // Counts Over-sampling clock enables
reg [2:0] rx_sampleCount; // Counts number of bits received
// These last two signals are used to make sure the "rx_valid" signal
// is only asserted for one clock cycle.
reg rx_validInternal, rx_validLast;
// -----------------//
// -- TX Signals -- //
// -----------------//
// State Machine Assignments
localparam TX_WAIT = 0;
localparam TX_TRANSMITTING = 1;
localparam TX_INITIAL_STATE = TX_WAIT;
reg tx_state = TX_INITIAL_STATE;
reg [9:0] tx_dataBuffer; // Capture Register for transmitted data
reg [4:0] tx_count; // Counts over-sampling clock
reg [3:0] tx_sampleCount; // Number of Bits Sent
/////////////////////
// Implementations //
/////////////////////
// ---------------------------- //
// -- Misc Synchronous Logic -- //
// ---------------------------- //
always @(posedge clk) begin
// Clock Divider
if (reset) begin
count <= 0;
enable <= 0;
end else if (count == CLK_DIV_COUNT - 1) begin
count <= 0;
enable <= 1;
end else begin
count <= count + 1;
enable <= 0;
end
// RX Synchronizer
if (enable) begin
{rx_sync,rx_internal} <= {rx, rx_sync};
end
// Pulse Shortener for rx_valid signal
rx_validLast <= rx_validInternal;
end
// Pulse Shortner for rx_valid signal
assign rx_valid = rx_validInternal & ~rx_validLast;
// ---------------------- //
// -- RX State Machine -- //
// ---------------------- //
always @(posedge clk) begin
if (reset) begin
rx_state <= RX_INITIAL_STATE;
rx_validInternal <= 0;
end else if (enable) begin
case (rx_state)
// Wait for the start bit. (RX = 0)
RX_WAIT: begin
rx_validInternal <= 0;
if (rx_internal == 0) begin
rx_state <= RX_CHECK_START;
rx_count <= 1;
end
end
// Aligh with center of transmitted bit
RX_CHECK_START: begin
// Check if RX is still 0
if (rx_count == (OSF >> 1) - 1 && rx_internal == 0) begin
rx_state <= RX_RECEIVING;
rx_count <= 0;
rx_sampleCount <= 0;
// Faulty Start Bit
end else if (rx_count == (OSF >> 1) - 1 && rx_internal == 1) begin
rx_state <= RX_WAIT;
// Default Option: Count local clocks
end else begin
rx_count <= rx_count + 1;
end
end
// Sample in middle of received bit. Shift data into rx_data
RX_RECEIVING: begin
if (rx_count == OSF - 1) begin
rx_count <= 0;
rx_data <= {rx_internal, rx_data[7:1]};
rx_sampleCount <= rx_sampleCount + 1;
// Check if this is the last bit of data
if (rx_sampleCount == 7) begin
rx_state <= RX_WAIT_FOR_STOP;
end
end else begin
rx_count <= rx_count + 1;
end
end
// Wait until stop bit is received
// Not the best logic in the world, but it works.
RX_WAIT_FOR_STOP: begin
if (rx_internal == 1'b1) begin
rx_state <= RX_WAIT;
rx_validInternal <= 1;
end
end
// In case something goes horribly wrong.
default: begin
rx_state <= RX_INITIAL_STATE;
end
endcase
end
end
// ---------------------- //
// -- TX State Machine -- //
// ---------------------- //
always @(posedge clk) begin
if (reset) begin
tx_state <= TX_INITIAL_STATE;
tx <= 1;
end else begin
case (tx_state)
// Wait for start signal.
// Register transmitted data and deassert ready.
TX_WAIT: begin
tx <= 1;
if (tx_transmit) begin
tx_dataBuffer <= {1'b1, tx_data, 1'b0};
tx_count <= 0;
tx_sampleCount <= 0;
tx_ready <= 0;
tx_state <= TX_TRANSMITTING;
end else begin
tx_ready <= 1;
end
end
// Shift Out Data
TX_TRANSMITTING: begin
if (enable) begin
if (tx_count == OSF - 1) begin
tx_count <= 0;
tx_sampleCount <= tx_sampleCount + 1;
tx <= tx_dataBuffer[0];
tx_dataBuffer <= {1'b1, tx_dataBuffer[9:1]};
if (tx_sampleCount == 9) begin
tx_state <= TX_WAIT;
end
end else begin
tx_count <= tx_count + 1;
end
end
end
default: begin
tx_state <= TX_WAIT;
end
endcase
end
end
endmodule

View file

@ -0,0 +1,115 @@
# TCL File Generated by Component Editor 16.1
# Thu May 27 17:12:45 BST 2021
# DO NOT MODIFY
#
# uart_interface "uart_interface" v1.0
# 2021.05.27.17:12:45
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module uart_interface
#
set_module_property DESCRIPTION ""
set_module_property NAME uart_interface
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME uart_interface
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL uart
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file uart.v VERILOG PATH ip/de10lite-hdl/uart.v TOP_LEVEL_FILE
#
# parameters
#
add_parameter CLK_FREQ INTEGER 50000000
set_parameter_property CLK_FREQ DEFAULT_VALUE 50000000
set_parameter_property CLK_FREQ DISPLAY_NAME CLK_FREQ
set_parameter_property CLK_FREQ TYPE INTEGER
set_parameter_property CLK_FREQ UNITS None
set_parameter_property CLK_FREQ HDL_PARAMETER true
add_parameter BAUD INTEGER 115200
set_parameter_property BAUD DEFAULT_VALUE 115200
set_parameter_property BAUD DISPLAY_NAME BAUD
set_parameter_property BAUD TYPE INTEGER
set_parameter_property BAUD UNITS None
set_parameter_property BAUD HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock clock
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end rx rx Input 1
add_interface_port conduit_end rx_data rx_data Output 8
add_interface_port conduit_end rx_valid rx_valid Output 1
add_interface_port conduit_end tx tx Output 1
add_interface_port conduit_end tx_data tx_data Input 8
add_interface_port conduit_end tx_transmit tx_transmit Input 1
add_interface_port conduit_end tx_ready tx_ready Output 1