From d178e7bee0e1327e3ec1e58cfef82e1cbc7387cb Mon Sep 17 00:00:00 2001 From: Aadi Desai <21363892+supleed2@users.noreply.github.com> Date: Thu, 27 May 2021 17:09:15 +0100 Subject: [PATCH 1/2] Add UART interface IP Tp be tested --- .../ip/de10lite-hdl/uart.v | 273 ++++++++++++++++++ 1 file changed, 273 insertions(+) create mode 100644 Vision/DE10_LITE_D8M_VIP_16/ip/de10lite-hdl/uart.v diff --git a/Vision/DE10_LITE_D8M_VIP_16/ip/de10lite-hdl/uart.v b/Vision/DE10_LITE_D8M_VIP_16/ip/de10lite-hdl/uart.v new file mode 100644 index 0000000..df3820e --- /dev/null +++ b/Vision/DE10_LITE_D8M_VIP_16/ip/de10lite-hdl/uart.v @@ -0,0 +1,273 @@ +/* +Source: https://github.com/hildebrandmw/de10lite-hdl/blob/master/components/uart/hdl/uart.v +Description: Very simple UART tx/rx module. Requires a streaming interface, +provides no buffering for input or output data. +*/ + +module uart +#( parameter CLK_FREQ = 50_000_000, + parameter BAUD = 115_200 +) +( input clk, + input reset, + + // Receiving + input rx, // Received serial stream + output reg [7:0] rx_data, // Deserialized byte. + output rx_valid, // Asserted when rx_data is valid + + // Transmitting + output reg tx, // Transmitted serial stream + input [7:0] tx_data, // Deserialized byte to transmit. + input tx_transmit, // Start Signal. No effect if tx_ready = 0 + output reg tx_ready // Asserted when ready to accept data + ); + + /////////////////////////////// + // Functionality Description // + /////////////////////////////// + + /* + RECEIVING: Module receives a serial stream through the port rx. + When a byte has been successfully received, the received data will be + available on the output port rx_data and the output port rx_valid will be + asserted for 1 clock cycle. + + Validity of output data is not guaranteed if rx_valid is not 1. If this + is important for you, you may modify this design to register the output. + + TRANSMITTING: When input port tx_transmit is 1 (asserted), module will + store the data on the input port tx_data and serialize through the output + port tx. + + Module will only save and transmit the data at tx_data if the signal + tx_ready is asserted when tx_transmit is asserted. This module will not + buffer input data. While transmitting, tx_ready is deasserted and the + input port tx_transmit will have no effect. + + Once tx_ready is deasserted, data at port tx_data is not used and need + not be stable. + */ + + ///////////////////////// + // Signal Declarations // + ///////////////////////// + + // ---------------------- // + // -- Local Parameters -- // + // ---------------------- // + + // Number of synchronization stages to avoid metastability + localparam SYNC_STAGES = 2; + + // Over Sampling Factor + localparam OSF = 16; + + // Compute count to generate local clock enable + localparam CLK_DIV_COUNT = CLK_FREQ / (OSF * BAUD); + + // ---------------------------- // + // -- Clock Dividing Counter -- // + // ---------------------------- // + + reg [15:0] count; + reg enable; // Local Clock Enable + + // -- RX Synchronizer -- + reg [SYNC_STAGES-1:0] rx_sync; + reg rx_internal; + + // ---------------- // + // -- RX Signals -- // + // ---------------- // + + // State Machine Assignments + localparam RX_WAIT = 0; + localparam RX_CHECK_START = 1; + localparam RX_RECEIVING = 2; + localparam RX_WAIT_FOR_STOP = 3; + + localparam RX_INITIAL_STATE = RX_WAIT; + reg [1:0] rx_state = RX_INITIAL_STATE; + + reg [4:0] rx_count; // Counts Over-sampling clock enables + reg [2:0] rx_sampleCount; // Counts number of bits received + + // These last two signals are used to make sure the "rx_valid" signal + // is only asserted for one clock cycle. + + reg rx_validInternal, rx_validLast; + + // -----------------// + // -- TX Signals -- // + // -----------------// + + // State Machine Assignments + localparam TX_WAIT = 0; + localparam TX_TRANSMITTING = 1; + + localparam TX_INITIAL_STATE = TX_WAIT; + reg tx_state = TX_INITIAL_STATE; + + reg [9:0] tx_dataBuffer; // Capture Register for transmitted data + reg [4:0] tx_count; // Counts over-sampling clock + reg [3:0] tx_sampleCount; // Number of Bits Sent + + ///////////////////// + // Implementations // + ///////////////////// + + // ---------------------------- // + // -- Misc Synchronous Logic -- // + // ---------------------------- // + + always @(posedge clk) begin + + // Clock Divider + if (reset) begin + count <= 0; + enable <= 0; + end else if (count == CLK_DIV_COUNT - 1) begin + count <= 0; + enable <= 1; + end else begin + count <= count + 1; + enable <= 0; + end + + // RX Synchronizer + if (enable) begin + {rx_sync,rx_internal} <= {rx, rx_sync}; + end + + // Pulse Shortener for rx_valid signal + rx_validLast <= rx_validInternal; + end + + // Pulse Shortner for rx_valid signal + assign rx_valid = rx_validInternal & ~rx_validLast; + + + // ---------------------- // + // -- RX State Machine -- // + // ---------------------- // + + always @(posedge clk) begin + if (reset) begin + rx_state <= RX_INITIAL_STATE; + rx_validInternal <= 0; + end else if (enable) begin + case (rx_state) + + // Wait for the start bit. (RX = 0) + + RX_WAIT: begin + rx_validInternal <= 0; + if (rx_internal == 0) begin + rx_state <= RX_CHECK_START; + rx_count <= 1; + end + end + + // Aligh with center of transmitted bit + + RX_CHECK_START: begin + + // Check if RX is still 0 + if (rx_count == (OSF >> 1) - 1 && rx_internal == 0) begin + rx_state <= RX_RECEIVING; + rx_count <= 0; + rx_sampleCount <= 0; + + // Faulty Start Bit + end else if (rx_count == (OSF >> 1) - 1 && rx_internal == 1) begin + rx_state <= RX_WAIT; + + // Default Option: Count local clocks + end else begin + rx_count <= rx_count + 1; + end + end + + // Sample in middle of received bit. Shift data into rx_data + RX_RECEIVING: begin + if (rx_count == OSF - 1) begin + rx_count <= 0; + rx_data <= {rx_internal, rx_data[7:1]}; + rx_sampleCount <= rx_sampleCount + 1; + + // Check if this is the last bit of data + if (rx_sampleCount == 7) begin + rx_state <= RX_WAIT_FOR_STOP; + end + end else begin + rx_count <= rx_count + 1; + end + end + + // Wait until stop bit is received + // Not the best logic in the world, but it works. + RX_WAIT_FOR_STOP: begin + if (rx_internal == 1'b1) begin + rx_state <= RX_WAIT; + rx_validInternal <= 1; + end + end + + // In case something goes horribly wrong. + default: begin + rx_state <= RX_INITIAL_STATE; + end + endcase + end + end + + // ---------------------- // + // -- TX State Machine -- // + // ---------------------- // + + always @(posedge clk) begin + if (reset) begin + tx_state <= TX_INITIAL_STATE; + tx <= 1; + end else begin + case (tx_state) + // Wait for start signal. + // Register transmitted data and deassert ready. + TX_WAIT: begin + tx <= 1; + if (tx_transmit) begin + tx_dataBuffer <= {1'b1, tx_data, 1'b0}; + tx_count <= 0; + tx_sampleCount <= 0; + tx_ready <= 0; + tx_state <= TX_TRANSMITTING; + end else begin + tx_ready <= 1; + end + end + + // Shift Out Data + TX_TRANSMITTING: begin + if (enable) begin + if (tx_count == OSF - 1) begin + tx_count <= 0; + tx_sampleCount <= tx_sampleCount + 1; + tx <= tx_dataBuffer[0]; + tx_dataBuffer <= {1'b1, tx_dataBuffer[9:1]}; + if (tx_sampleCount == 9) begin + tx_state <= TX_WAIT; + end + end else begin + tx_count <= tx_count + 1; + end + end + end + + default: begin + tx_state <= TX_WAIT; + end + endcase + end + end +endmodule \ No newline at end of file From d0619cd9cd80031e684186d820b3bc5748fa64b9 Mon Sep 17 00:00:00 2001 From: anishghanekar Date: Fri, 28 May 2021 00:40:25 +0100 Subject: [PATCH 2/2] Changed Colour recognition code --- .../DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml | 117 +- .../.qsys_edit/Qsys_schematic.nlv | 89 +- .../.qsys_edit/preferences.xml | 4 +- .../DE10_LITE_D8M_VIP.qws | Bin 679 -> 2514 bytes .../DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.v | 13 +- Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys | 198 +- Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo | 10 +- Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf | 14 +- Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html | 258 +- Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml | 9138 +++++++++++++---- .../Qsys/Qsys_generation.rpt | 226 +- .../Qsys/Qsys_generation_previous.rpt | 231 +- .../ip/EEE_IMGPROC/EEE_IMGPROC.v | 14 +- .../uart_interface_hw.tcl | 115 + 14 files changed, 8134 insertions(+), 2293 deletions(-) create mode 100644 Vision/DE10_LITE_D8M_VIP_16/uart_interface_hw.tcl diff --git a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml index 2319421..9fb466d 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml +++ b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys.xml @@ -827,7 +827,7 @@ false - + dock.single.Clock\ Domains\ \-\ Beta dock.single.IP\ Catalog @@ -853,7 +853,7 @@ - + dock.single.Hierarchy @@ -880,7 +880,7 @@ - + dock.single.Connections dock.single.System\ Contents @@ -897,18 +897,12 @@ dock.single.Interconnect\ Requirements dock.single.Instrumentation dock.single.Instance\ Parameters + dock.single.Address\ Map dock.single.Domains 0 dock.PlaceholderList - - - dock.single.System\ Contents - - true - - dock.single.Address\ Map @@ -932,7 +926,7 @@ - + dock.single.Parameters dock.single.Details @@ -1012,16 +1006,6 @@ - - - - - IP Catalog - - - - - 0 @@ -1082,10 +1066,10 @@ - - + + - Parameters + IP Catalog @@ -1093,7 +1077,7 @@ - 1 + 0 0 dock.PlaceholderList @@ -1199,6 +1183,16 @@ + + + + + Parameters + + + + + @@ -1617,9 +1611,21 @@ + dock.mode.maximized dock.mode.normal + + dock.mode.maximized + ccontrol center + + + + 1 + dock.single.Address\ Map + + + dock.mode.normal ccontrol center @@ -1627,10 +1633,9 @@ dock.single.Address\ Map - - - - + + + @@ -1847,9 +1852,21 @@ + dock.mode.maximized dock.mode.normal + + dock.mode.maximized + ccontrol center + + + + 0 + dock.single.System\ Contents + + + dock.mode.normal ccontrol center @@ -1857,10 +1874,9 @@ dock.single.System\ Contents - - - - + + + @@ -1876,9 +1892,21 @@ dock.mode.minimized + dock.mode.maximized dock.mode.normal + + dock.mode.maximized + ccontrol center + + + + 2 + dock.single.Interconnect\ Requirements + + + dock.mode.minimized ccontrol north @@ -1899,8 +1927,8 @@ dock.single.Interconnect\ Requirements - - + + @@ -2140,24 +2168,7 @@ - - - - dock.mode.normal - - dock.mode.normal - ccontrol center - - - - - - - - - - - + diff --git a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv index 8cf3162..2179962 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv +++ b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/Qsys_schematic.nlv @@ -2,53 +2,58 @@ # preplace inst Qsys.nios2_gen2.clock_bridge -pg 1 preplace inst Qsys.altpll_0 -pg 1 -lvl 3 -y 250 -preplace inst Qsys.i2c_opencores_camera -pg 1 -lvl 7 -y 30 -preplace inst Qsys.alt_vip_itc_0 -pg 1 -lvl 7 -y 810 -preplace inst Qsys.onchip_memory2_0 -pg 1 -lvl 7 -y 540 -preplace inst Qsys.led -pg 1 -lvl 7 -y 1390 +preplace inst Qsys.i2c_opencores_camera -pg 1 -lvl 8 -y 30 +preplace inst Qsys.alt_vip_itc_0 -pg 1 -lvl 8 -y 810 +preplace inst Qsys.onchip_memory2_0 -pg 1 -lvl 8 -y 540 +preplace inst Qsys.led -pg 1 -lvl 8 -y 1390 preplace inst Qsys.clk_50 -pg 1 -lvl 1 -y 720 -preplace inst Qsys.sysid_qsys -pg 1 -lvl 7 -y 1010 -preplace inst Qsys.sdram -pg 1 -lvl 7 -y 910 +preplace inst Qsys.sysid_qsys -pg 1 -lvl 8 -y 1010 +preplace inst Qsys.sdram -pg 1 -lvl 8 -y 910 preplace inst Qsys.nios2_gen2.reset_bridge -pg 1 -preplace inst Qsys.jtag_uart -pg 1 -lvl 7 -y 330 +preplace inst Qsys.jtag_uart -pg 1 -lvl 8 -y 330 preplace inst Qsys.TERASIC_CAMERA_0 -pg 1 -lvl 4 -y 740 -preplace inst Qsys.mipi_reset_n -pg 1 -lvl 7 -y 1190 +preplace inst Qsys.mipi_reset_n -pg 1 -lvl 8 -y 1190 preplace inst Qsys.alt_vip_vfb_0 -pg 1 -lvl 5 -y 620 preplace inst Qsys -pg 1 -lvl 1 -y 40 -regy -20 -preplace inst Qsys.timer -pg 1 -lvl 7 -y 440 -preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 7 -y 1090 -preplace inst Qsys.key -pg 1 -lvl 7 -y 620 -preplace inst Qsys.sw -pg 1 -lvl 7 -y 1290 +preplace inst Qsys.uart_interface_0 -pg 1 -lvl 2 -y 330 +preplace inst Qsys.EEE_IMGPROC_0 -pg 1 -lvl 7 -y 600 +preplace inst Qsys.timer -pg 1 -lvl 8 -y 440 +preplace inst Qsys.mipi_pwdn_n -pg 1 -lvl 8 -y 1090 +preplace inst Qsys.key -pg 1 -lvl 8 -y 620 +preplace inst Qsys.sw -pg 1 -lvl 8 -y 1290 preplace inst Qsys.TERASIC_AUTO_FOCUS_0 -pg 1 -lvl 6 -y 560 preplace inst Qsys.nios2_gen2.cpu -pg 1 -preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 470 -preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 7 -y 170 -preplace netloc INTERCONNECTQsys(SLAVE)sdram.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)led.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)mipi_pwdn_n.reset,(MASTER)clk_50.clk_reset,(SLAVE)mipi_reset_n.reset,(SLAVE)sysid_qsys.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)sw.reset,(SLAVE)key.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)nios2_gen2.reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)jtag_uart.reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(SLAVE)timer.reset) 1 1 6 430 670 870 530 1170 730 1650 730 1890 800 2230 -preplace netloc POINT_TO_POINTQsys(SLAVE)alt_vip_itc_0.din,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 2190 -preplace netloc EXPORTQsys(SLAVE)clk_50.clk_in_reset,(SLAVE)Qsys.reset) 1 0 1 NJ -preplace netloc EXPORTQsys(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 7 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ -preplace netloc EXPORTQsys(SLAVE)sdram.wire,(SLAVE)Qsys.sdram_wire) 1 0 7 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ -preplace netloc EXPORTQsys(SLAVE)led.external_connection,(SLAVE)Qsys.led_external_connection) 1 0 7 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ -preplace netloc EXPORTQsys(MASTER)Qsys.clk_sdram,(MASTER)altpll_0.c1) 1 3 5 NJ 210 NJ 210 NJ 210 NJ 160 NJ -preplace netloc EXPORTQsys(SLAVE)Qsys.altpll_0_locked_conduit,(SLAVE)altpll_0.locked_conduit) 1 0 3 NJ 410 NJ 410 NJ -preplace netloc EXPORTQsys(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit,(SLAVE)Qsys.terasic_auto_focus_0_conduit) 1 0 6 NJ 630 NJ 630 NJ 570 NJ 570 NJ 570 NJ -preplace netloc EXPORTQsys(SLAVE)altpll_0.areset_conduit,(SLAVE)Qsys.altpll_0_areset_conduit) 1 0 3 NJ 260 NJ 260 NJ -preplace netloc EXPORTQsys(SLAVE)mipi_reset_n.external_connection,(SLAVE)Qsys.mipi_reset_n_external_connection) 1 0 7 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ -preplace netloc EXPORTQsys(SLAVE)Qsys.sw_external_connection,(SLAVE)sw.external_connection) 1 0 7 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ -preplace netloc EXPORTQsys(SLAVE)Qsys.mipi_pwdn_n_external_connection,(SLAVE)mipi_pwdn_n.external_connection) 1 0 7 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ -preplace netloc EXPORTQsys(MASTER)Qsys.clk_vga,(MASTER)altpll_0.c3) 1 3 5 NJ 360 NJ 360 NJ 360 NJ 320 NJ -preplace netloc EXPORTQsys(SLAVE)key.external_connection,(SLAVE)Qsys.key_external_connection) 1 0 7 NJ 650 NJ 650 NJ 650 NJ 650 NJ 750 NJ 750 NJ -preplace netloc EXPORTQsys(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 7 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ -preplace netloc EXPORTQsys(SLAVE)Qsys.alt_vip_itc_0_clocked_video,(SLAVE)alt_vip_itc_0.clocked_video) 1 0 7 NJ 830 NJ 830 NJ 830 NJ 830 NJ 820 NJ 820 NJ -preplace netloc FAN_OUTQsys(SLAVE)sdram.clk,(SLAVE)alt_vip_itc_0.is_clk_rst,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)alt_vip_vfb_0.clock,(SLAVE)TERASIC_CAMERA_0.clock_reset,(MASTER)altpll_0.c2) 1 3 4 1190 340 1630 710 1870 780 2150 -preplace netloc POINT_TO_POINTQsys(SLAVE)TERASIC_AUTO_FOCUS_0.din,(MASTER)alt_vip_vfb_0.dout) 1 5 1 1830 +preplace inst Qsys.nios2_gen2 -pg 1 -lvl 2 -y 520 +preplace inst Qsys.i2c_opencores_mipi -pg 1 -lvl 8 -y 170 +preplace netloc EXPORTQsys(MASTER)altpll_0.c1,(MASTER)Qsys.clk_sdram) 1 3 6 NJ 280 NJ 280 NJ 280 NJ 280 NJ 300 NJ +preplace netloc INTERCONNECTQsys(SLAVE)sysid_qsys.control_slave,(SLAVE)timer.s1,(MASTER)nios2_gen2.instruction_master,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)altpll_0.pll_slave,(SLAVE)nios2_gen2.debug_mem_slave,(SLAVE)led.s1,(SLAVE)EEE_IMGPROC_0.s1,(SLAVE)mipi_pwdn_n.s1,(SLAVE)i2c_opencores_mipi.avalon_slave_0,(MASTER)nios2_gen2.data_master,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(SLAVE)sw.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)onchip_memory2_0.s1,(SLAVE)mipi_reset_n.s1,(SLAVE)key.s1) 1 1 7 450 420 850 810 NJ 710 NJ 710 1910 730 2190 770 2580 +preplace netloc EXPORTQsys(SLAVE)i2c_opencores_camera.export,(SLAVE)Qsys.i2c_opencores_camera_export) 1 0 8 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ 100 NJ +preplace netloc EXPORTQsys(SLAVE)led.external_connection,(SLAVE)Qsys.led_external_connection) 1 0 8 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ 1420 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.eee_imgproc_0_conduit_mode,(SLAVE)EEE_IMGPROC_0.conduit_mode) 1 0 7 NJ 300 NJ 300 NJ 410 NJ 410 NJ 410 NJ 410 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.altpll_0_locked_conduit,(SLAVE)altpll_0.locked_conduit) 1 0 3 NJ 280 NJ 280 NJ +preplace netloc FAN_OUTQsys(SLAVE)mipi_pwdn_n.clk,(SLAVE)i2c_opencores_camera.clock,(SLAVE)key.clk,(SLAVE)onchip_memory2_0.clk1,(MASTER)clk_50.clk,(SLAVE)jtag_uart.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)nios2_gen2.clk,(SLAVE)sysid_qsys.clk,(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)led.clk,(SLAVE)sw.clk,(SLAVE)timer.clk,(SLAVE)uart_interface_0.clock) 1 1 7 410 320 950 380 NJ 340 NJ 300 NJ 300 NJ 300 2640 +preplace netloc EXPORTQsys(SLAVE)Qsys.sdram_wire,(SLAVE)sdram.wire) 1 0 8 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ 980 NJ +preplace netloc EXPORTQsys(SLAVE)mipi_pwdn_n.external_connection,(SLAVE)Qsys.mipi_pwdn_n_external_connection) 1 0 8 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ 1120 NJ +preplace netloc FAN_OUTQsys(SLAVE)sdram.clk,(SLAVE)alt_vip_itc_0.is_clk_rst,(MASTER)altpll_0.c2,(SLAVE)TERASIC_CAMERA_0.clock_reset,(SLAVE)TERASIC_AUTO_FOCUS_0.clock,(SLAVE)EEE_IMGPROC_0.clock,(SLAVE)alt_vip_vfb_0.clock) 1 3 5 1250 300 1670 730 1870 690 2150 860 2600 +preplace netloc EXPORTQsys(SLAVE)Qsys.uart_interface_0_conduit_end,(SLAVE)uart_interface_0.conduit_end) 1 0 2 NJ 360 NJ +preplace netloc POINT_TO_POINTQsys(MASTER)EEE_IMGPROC_0.avalon_streaming_source,(SLAVE)alt_vip_itc_0.din) 1 7 1 2600 +preplace netloc EXPORTQsys(SLAVE)Qsys.terasic_auto_focus_0_conduit,(SLAVE)TERASIC_AUTO_FOCUS_0.Conduit) 1 0 6 NJ 460 NJ 460 NJ 570 NJ 570 NJ 570 NJ +preplace netloc FAN_OUTQsys(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)i2c_opencores_camera.interrupt_sender,(SLAVE)jtag_uart.irq,(MASTER)nios2_gen2.irq,(SLAVE)timer.irq) 1 2 6 NJ 870 NJ 870 NJ 790 NJ 790 NJ 790 2620 +preplace netloc EXPORTQsys(SLAVE)key.external_connection,(SLAVE)Qsys.key_external_connection) 1 0 8 NJ 710 NJ 710 NJ 830 NJ 730 NJ 770 NJ 750 NJ 750 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.i2c_opencores_mipi_export,(SLAVE)i2c_opencores_mipi.export) 1 0 8 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ 240 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.alt_vip_itc_0_clocked_video,(SLAVE)alt_vip_itc_0.clocked_video) 1 0 8 NJ 890 NJ 890 NJ 890 NJ 890 NJ 820 NJ 820 NJ 820 NJ +preplace netloc POINT_TO_POINTQsys(SLAVE)TERASIC_AUTO_FOCUS_0.din,(MASTER)alt_vip_vfb_0.dout) 1 5 1 1890 +preplace netloc FAN_INQsys(SLAVE)sdram.s1,(MASTER)alt_vip_vfb_0.write_master,(MASTER)alt_vip_vfb_0.read_master) 1 5 3 1890 960 NJ 960 NJ preplace netloc EXPORTQsys(SLAVE)clk_50.clk_in,(SLAVE)Qsys.clk) 1 0 1 NJ -preplace netloc FAN_INQsys(MASTER)alt_vip_vfb_0.read_master,(MASTER)alt_vip_vfb_0.write_master,(SLAVE)sdram.s1) 1 5 2 1830 960 NJ -preplace netloc FAN_OUTQsys(SLAVE)jtag_uart.irq,(SLAVE)timer.irq,(MASTER)nios2_gen2.irq,(SLAVE)i2c_opencores_mipi.interrupt_sender,(SLAVE)i2c_opencores_camera.interrupt_sender) 1 2 5 NJ 550 NJ 550 NJ 550 NJ 550 2170 -preplace netloc POINT_TO_POINTQsys(MASTER)TERASIC_CAMERA_0.avalon_streaming_source,(SLAVE)alt_vip_vfb_0.din) 1 4 1 1610 -preplace netloc EXPORTQsys(MASTER)Qsys.d8m_xclkin,(MASTER)altpll_0.c4) 1 3 5 NJ 380 NJ 380 NJ 380 NJ 300 NJ -preplace netloc FAN_OUTQsys(SLAVE)altpll_0.inclk_interface,(SLAVE)i2c_opencores_camera.clock,(SLAVE)led.clk,(SLAVE)onchip_memory2_0.clk1,(SLAVE)timer.clk,(SLAVE)i2c_opencores_mipi.clock,(SLAVE)sw.clk,(SLAVE)sysid_qsys.clk,(SLAVE)mipi_pwdn_n.clk,(SLAVE)nios2_gen2.clk,(SLAVE)jtag_uart.clk,(MASTER)clk_50.clk,(SLAVE)mipi_reset_n.clk,(SLAVE)key.clk) 1 1 6 410 430 850 400 NJ 400 NJ 400 NJ 400 2210 -preplace netloc INTERCONNECTQsys(SLAVE)altpll_0.pll_slave,(SLAVE)led.s1,(SLAVE)jtag_uart.avalon_jtag_slave,(SLAVE)i2c_opencores_mipi.avalon_slave_0,(SLAVE)mipi_reset_n.s1,(MASTER)nios2_gen2.data_master,(SLAVE)sysid_qsys.control_slave,(SLAVE)timer.s1,(SLAVE)sw.s1,(SLAVE)onchip_memory2_0.s1,(SLAVE)key.s1,(SLAVE)mipi_pwdn_n.s1,(SLAVE)i2c_opencores_camera.avalon_slave_0,(SLAVE)TERASIC_AUTO_FOCUS_0.mm_ctrl,(MASTER)nios2_gen2.instruction_master,(SLAVE)nios2_gen2.debug_mem_slave) 1 1 6 450 610 890 510 NJ 510 NJ 510 1850 690 2130 -preplace netloc EXPORTQsys(SLAVE)Qsys.terasic_camera_0_conduit_end,(SLAVE)TERASIC_CAMERA_0.conduit_end) 1 0 4 NJ 790 NJ 790 NJ 790 NJ -levelinfo -pg 1 0 200 2570 -levelinfo -hier Qsys 210 240 590 980 1300 1680 1980 2320 2470 +preplace netloc POINT_TO_POINTQsys(SLAVE)EEE_IMGPROC_0.avalon_streaming_sink,(MASTER)TERASIC_AUTO_FOCUS_0.dout) 1 6 1 N +preplace netloc POINT_TO_POINTQsys(SLAVE)alt_vip_vfb_0.din,(MASTER)TERASIC_CAMERA_0.avalon_streaming_source) 1 4 1 1630 +preplace netloc EXPORTQsys(SLAVE)sw.external_connection,(SLAVE)Qsys.sw_external_connection) 1 0 8 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ 1320 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.mipi_reset_n_external_connection,(SLAVE)mipi_reset_n.external_connection) 1 0 8 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ 1220 NJ +preplace netloc EXPORTQsys(MASTER)altpll_0.c3,(MASTER)Qsys.clk_vga) 1 3 6 NJ 320 NJ 320 NJ 320 NJ 320 NJ 320 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.altpll_0_areset_conduit,(SLAVE)altpll_0.areset_conduit) 1 0 3 NJ 260 NJ 260 NJ +preplace netloc EXPORTQsys(MASTER)Qsys.d8m_xclkin,(MASTER)altpll_0.c4) 1 3 6 NJ 220 NJ 220 NJ 220 NJ 220 NJ 160 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.terasic_camera_0_conduit_end,(SLAVE)TERASIC_CAMERA_0.conduit_end) 1 0 4 NJ 480 NJ 480 NJ 790 NJ +preplace netloc EXPORTQsys(SLAVE)Qsys.reset,(SLAVE)clk_50.clk_in_reset) 1 0 1 NJ +preplace netloc INTERCONNECTQsys(SLAVE)sw.reset,(SLAVE)timer.reset,(SLAVE)onchip_memory2_0.reset1,(SLAVE)key.reset,(SLAVE)alt_vip_vfb_0.reset,(SLAVE)uart_interface_0.reset,(SLAVE)mipi_pwdn_n.reset,(SLAVE)i2c_opencores_camera.clock_reset,(SLAVE)led.reset,(SLAVE)TERASIC_AUTO_FOCUS_0.reset,(SLAVE)TERASIC_CAMERA_0.clock_reset_reset,(MASTER)clk_50.clk_reset,(SLAVE)jtag_uart.reset,(MASTER)nios2_gen2.debug_reset_request,(SLAVE)EEE_IMGPROC_0.reset,(SLAVE)sysid_qsys.reset,(SLAVE)alt_vip_itc_0.is_clk_rst_reset,(SLAVE)sdram.reset,(SLAVE)nios2_gen2.reset,(SLAVE)i2c_opencores_mipi.clock_reset,(SLAVE)altpll_0.inclk_interface_reset,(SLAVE)mipi_reset_n.reset) 1 1 7 430 440 910 850 1290 690 1690 750 1930 710 2170 880 2680 +levelinfo -pg 1 0 200 3000 +levelinfo -hier Qsys 210 240 590 1020 1340 1720 2020 2320 2750 2900 diff --git a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml index d057998..f64d299 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml +++ b/Vision/DE10_LITE_D8M_VIP_16/.qsys_edit/preferences.xml @@ -9,6 +9,6 @@ - - + + diff --git a/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws b/Vision/DE10_LITE_D8M_VIP_16/DE10_LITE_D8M_VIP.qws index f6db59227603d7375e9c185ab18dd462d5a9b694..870428930ae16021944c4181aae9fa2f41c64a34 100644 GIT binary patch literal 2514 zcmds&L2DCH5Xb*7M(`Mrdh#G5B?yVxHQMziY89bHk>bU}nq;>cVw*IsR*>S|v*5=N zyxW^6FM`ozBe;(=Kp3dS2Y?Z^++u}R;F0%>T9ST z(g0mYDT|Ik*Lda?sKJ^A-P96Nj4sk5{4Sc?@JwB;uqVc%&AMn(C8}d7(K2>s_hF~5 zr>uIB>jGXa74G8WZ zp|WmIsD?E&aF&hz;*2Z*Z>H|PeEi@IsqzkU-=&$aAh{z|-s6ER&wNI{SGddJ5~-<+ zngeS29*$MQI=)i7d*6550`xc-OlP>@)`$3xlPGeQ63IJ z7$_zN#0ij;>X`@QJoT`aLW{Dz?S}dEv13kblv@Wq10Zn_& zH{U*Jjqz^0$84Q!C0ylH*=YYJo9ZaHsG s{x3Dnwlncx)6%!65tW80U)d=NI@o`v1Kx-}(S%+=Zz+b2ahdY{0^ie+$N&HU delta 65 zcmca4yqtA{HY4L?Jw^`}1_lPkiTBnrF)M8DWsG4|5h?| MyFrameBuffer640480813falsetrue0true0000000032false1024410244110000false]]> - + @@ -648,7 +648,7 @@ - + @@ -667,7 +667,7 @@ @@ -683,7 +683,7 @@ - + @@ -697,7 +697,7 @@ - + @@ -714,7 +714,7 @@ @@ -732,7 +732,7 @@ @@ -747,7 +747,7 @@ - + @@ -789,7 +789,7 @@ - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 @@ -840,6 +840,7 @@ + @@ -927,7 +928,7 @@ $${FILENAME}_onchip_memory2_0 @@ -936,9 +937,10 @@ - ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + @@ -958,7 +960,7 @@ @@ -984,7 +986,7 @@ - + @@ -1001,11 +1003,11 @@ - + @@ -1019,7 +1021,7 @@ @@ -1028,7 +1030,7 @@ @@ -1037,7 +1039,7 @@ @@ -1046,7 +1048,7 @@ @@ -1055,7 +1057,7 @@ @@ -1064,7 +1066,7 @@ @@ -1073,7 +1075,7 @@ @@ -1082,7 +1084,7 @@ @@ -1091,7 +1093,7 @@ @@ -1100,7 +1102,7 @@ @@ -1109,7 +1111,7 @@ @@ -1118,7 +1120,7 @@ @@ -1127,7 +1129,7 @@ @@ -1136,7 +1138,7 @@ @@ -1145,7 +1147,7 @@ @@ -1154,7 +1156,7 @@ @@ -1163,7 +1165,7 @@ @@ -1172,7 +1174,7 @@ @@ -1181,7 +1183,7 @@ @@ -1190,278 +1192,278 @@ - + - - - - - - - - - + + + + + + + + + - - + + - + diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo b/Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo index c3b5fca..865b02c 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo +++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1621008007 + 1622141601 false true false @@ -17573,7 +17573,7 @@ the requested settings for a module instance. --> embeddedsw.CMacro.TIMESTAMP - 1621008007 + 1622141601 embeddedsw.dts.compatible @@ -17593,7 +17593,7 @@ the requested settings for a module instance. --> embeddedsw.dts.params.timestamp - 1621008007 + 1622141601 embeddedsw.dts.vendor @@ -17609,7 +17609,7 @@ the requested settings for a module instance. --> int - 1621008007 + 1622141601 true false false diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf index 9a0cbd5..a76fee8 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf +++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.bsf @@ -4,18 +4,18 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2016 Altera Corporation. All rights reserved. -Your use of Altera Corporation's design tools, logic functions +Copyright (C) 2016 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, the Altera Quartus Prime License Agreement, -the Altera MegaCore Function License Agreement, or other +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic -devices manufactured by Altera and sold by Altera or its +devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. */ @@ -380,7 +380,7 @@ agreement for further details. (text "FVAL" (rect 245 1003 514 2016)(font "Arial" (color 0 0 0))) (text "LVAL" (rect 245 1019 514 2048)(font "Arial" (color 0 0 0))) (text "PIXCLK" (rect 245 1035 526 2080)(font "Arial" (color 0 0 0))) - (text " system " (rect 541 1056 1130 2122)(font "Arial" )) + (text " Qsys " (rect 550 1056 1136 2122)(font "Arial" )) (line (pt 240 32)(pt 336 32)(line_width 1)) (line (pt 336 32)(pt 336 1056)(line_width 1)) (line (pt 240 1056)(pt 336 1056)(line_width 1)) diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html index d039e8c..a8ca9c1 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html +++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2021.03.30.09:18:342021.05.27.17:50:16 Datasheet
@@ -88,14 +88,17 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
Processor
   nios2_gen2 - Nios II 16.0 + Nios II 16.1
All Components
   + EEE_IMGPROC_0 + EEE_IMGPROC 1.0 +
   TERASIC_AUTO_FOCUS_0 TERASIC_AUTO_FOCUS 1.0
   altpll_0 - altpll 16.0 + altpll 16.1
   i2c_opencores_camera i2c_opencores 12.0 @@ -104,37 +107,37 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord i2c_opencores 12.0
   jtag_uart - altera_avalon_jtag_uart 16.0 + altera_avalon_jtag_uart 16.1
   key - altera_avalon_pio 16.0 + altera_avalon_pio 16.1
   led - altera_avalon_pio 16.0 + altera_avalon_pio 16.1
   mipi_pwdn_n - altera_avalon_pio 16.0 + altera_avalon_pio 16.1
   mipi_reset_n - altera_avalon_pio 16.0 + altera_avalon_pio 16.1
   nios2_gen2 - altera_nios2_gen2 16.0 + altera_nios2_gen2 16.1
   onchip_memory2_0 - altera_avalon_onchip_memory2 16.0 + altera_avalon_onchip_memory2 16.1
   sdram - altera_avalon_new_sdram_controller 16.0 + altera_avalon_new_sdram_controller 16.1
   sw - altera_avalon_pio 16.0 + altera_avalon_pio 16.1
   sysid_qsys - altera_avalon_sysid_qsys 16.0 + altera_avalon_sysid_qsys 16.1
   timer - altera_avalon_timer 16.0 + altera_avalon_timer 16.1
@@ -157,6 +160,23 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord  data_master  instruction_master + +   + EEE_IMGPROC_0 + + + + + + + + + s1  + + + 0x00042000 + +   TERASIC_AUTO_FOCUS_0 @@ -413,6 +433,106 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + +
+
+

EEE_IMGPROC_0

EEE_IMGPROC v1.0 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ nios2_gen2 + data_master  EEE_IMGPROC_0
  s1
debug_reset_request  
  reset
+ TERASIC_AUTO_FOCUS_0 + dout  
  avalon_streaming_sink
+ altpll_0 + c2  
  clock
+ clk_50 + clk_reset  
  reset
avalon_streaming_source   + alt_vip_itc_0 +
  din
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + +
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
@@ -477,13 +597,13 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord dout   - alt_vip_itc_0 + EEE_IMGPROC_0 -   din +   avalon_streaming_sink
@@ -620,9 +740,9 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -999,7 +1119,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

altpll_0

altpll v16.0 +

altpll_0

altpll v16.1
- TERASIC_AUTO_FOCUS_0 + EEE_IMGPROC_0 dout  avalon_streaming_source   alt_vip_itc_0
@@ -1008,7 +1128,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord nios2_gen2 - + @@ -1079,6 +1199,22 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + + + + + + + + + + + + + + @@ -1799,7 +1935,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

clk_50

clock_source v16.0 +

clk_50

clock_source v16.1


@@ -1996,7 +2132,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

jtag_uart

altera_avalon_jtag_uart v16.0 +

jtag_uart

altera_avalon_jtag_uart v16.1
data_master  altpll_0altpll_0
  pll_slave
c2   + EEE_IMGPROC_0 +
  clock
@@ -2154,7 +2290,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

key

altera_avalon_pio v16.0 +

key

altera_avalon_pio v16.1
@@ -2358,7 +2494,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

led

altera_avalon_pio v16.0 +

led

altera_avalon_pio v16.1
@@ -2562,7 +2698,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

mipi_pwdn_n

altera_avalon_pio v16.0 +

mipi_pwdn_n

altera_avalon_pio v16.1
@@ -2766,7 +2902,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

mipi_reset_n

altera_avalon_pio v16.0 +

mipi_reset_n

altera_avalon_pio v16.1
@@ -2970,7 +3106,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

nios2_gen2

altera_nios2_gen2 v16.0 +

nios2_gen2

altera_nios2_gen2 v16.1
@@ -2979,7 +3115,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord clk_50 - + @@ -3368,6 +3504,32 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + + + + + + + + + + + + + + + + + + + + + + + + @@ -3482,6 +3644,10 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + + + + @@ -4124,7 +4290,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -4196,7 +4362,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -4367,7 +4533,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

onchip_memory2_0

altera_avalon_onchip_memory2 v16.0 +

onchip_memory2_0

altera_avalon_onchip_memory2 v16.1
clk  nios2_gen2nios2_gen2
  clk
data_master   + EEE_IMGPROC_0 +
  s1
debug_reset_request  
  reset
setting_asic_enabled false
register_file_porfalse
setting_asic_synopsys_translate_on_off false
dataSlaveMapParam<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /><slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /><slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /><slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /><slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /><slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /><slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /><slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /><slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /><slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map><address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /><slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /><slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /><slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /><slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /><slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /><slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /><slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /><slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /><slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='EEE_IMGPROC_0.s1' start='0x42000' end='0x42020' type='EEE_IMGPROC.s1' /></address-map>
tightlyCoupledDataMaster0MapParam
deviceFeaturesSystemInfoADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
AUTO_DEVICE
@@ -4444,6 +4610,10 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + + + + @@ -4452,6 +4622,10 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + + + + @@ -4476,6 +4650,10 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord + + + + @@ -4518,7 +4696,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -4629,7 +4807,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

sdram

altera_avalon_new_sdram_controller v16.0 +

sdram

altera_avalon_new_sdram_controller v16.1
enableDiffWidth false
derived_enableDiffWidthfalse
initMemContent falseinitializationFileName onchip_mem.hex
enPRInitModefalse
instanceID NONEsingleClockOperation false
derived_singleClockOperationfalse
slave1Latency 1
deviceFeaturesADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1
derived_set_addr_width
@@ -4923,7 +5101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

sw

altera_avalon_pio v16.0 +

sw

altera_avalon_pio v16.1
@@ -5127,7 +5305,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

sysid_qsys

altera_avalon_sysid_qsys v16.0 +

sysid_qsys

altera_avalon_sysid_qsys v16.1
@@ -5180,7 +5358,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - + @@ -5205,7 +5383,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
timestamp16170923141622134216
deviceFamily
TIMESTAMP16170923141622134216
@@ -5215,7 +5393,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
-

timer

altera_avalon_timer v16.0 +

timer

altera_avalon_timer v16.1
@@ -5408,8 +5586,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
- - + +
generation took 0.00 secondsrendering took 0.04 secondsgeneration took 0.01 secondsrendering took 0.08 seconds
diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml index b2467f4..dc8c9a7 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml +++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys.xml @@ -1,7 +1,7 @@ + date="2021.05.27.17:51:08" + outputDirectory="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/"> - - - - - @@ -127,42 +118,6 @@ role="export" width="1" /> - - - - - - - - - - - - - - - - - - - - @@ -193,6 +148,15 @@ + + + + + @@ -330,13 +294,13 @@ - + @@ -345,1225 +309,1770 @@ - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/EEE_IMGPROC_hw.tcl" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/TERASIC_AUTO_FOCUS_hw.tcl" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA_hw.tcl" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_RGB.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_Bayer.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer2RGB.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer_LineBuffer.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/alt_vip_itc_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_sync_compare.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_calculate_mode.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_control.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_mode_banks.sv" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_statemachine.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_fifo.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_generic_count.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_to_binary.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_sync.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_trigger_sync.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_sync_generation.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_frame_counter.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_sample_counter.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/alt_vipitc131_cvo.sdc" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/alt_vip_vfb.cpp" /> + + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_constants.h" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_elementclass_info.h" /> - + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_vfb_hwfast.hpp" /> + + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cdfg_types.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cusp_synth.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_exception.h" /> - + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_lib_types.h" /> + + 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path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_rv.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_rv_ports.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bit.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bit_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bit_proxies.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bv.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bv_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_logic.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_lv.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_lv_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_proxy.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/fx.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_context.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fix.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fixed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fx_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxcast_switch.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxdefs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxnum.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxnum_observer.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxtype_params.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxval.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxval_observer.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_ufix.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_ufixed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_ieee.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_mant.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_other_defs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_params.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_rep.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_utils.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_bigint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_biguint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_length_param.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbdefs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbexterns.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbutils.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_signed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_uint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_uint_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_unsigned.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/misc/sc_concatref.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/misc/sc_value_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_attribute.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_cmnhdr.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_constants.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_event.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_externs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_kernel_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_defs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_exps.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_friends.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_macros.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_module.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_module_name.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_object.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process_b.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process_host.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_sensitive.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_simcontext.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_time.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_ver.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_wait.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_wait_cthread.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_vcd_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_wif_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_hash.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_iostream.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_list.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_mempool.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_pq.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report_handler.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_temporary.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_vector.h" /> + + + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/frame_buffer.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/forms_rt.jar" /> - + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/jdom.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/launcher.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowbase.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowmanager.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/util/jptf.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/lib/com.altera.megawizard2.jar" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/alt_vip_vfb.cpp" /> + + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_constants.h" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_elementclass_info.h" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_vfb_hwfast.hpp" /> + + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cdfg_types.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cusp_synth.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_exception.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_lib_types.h" /> + - + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_au.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_eb.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_mm.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_st.h" /> - + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_cmp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fifo.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fifo_paged.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fp_au.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fp_cmp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fp_mult.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_gpio.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_immed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_mac.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_mem.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_mult.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_multadd.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_reg.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_shift.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_tapped_delay.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_bus.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_eb_channel.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_st_channel.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_debug.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_exit.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_overlay.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_pc.h" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cassert" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cctype" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/climits" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/config/stl_confix.h" /> - - + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/config/stl_cusp.h" /> - - - - - - - - - - - - - - - - - - - - - - - - - - - - + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/config/stlcomp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstddef" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstdio" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstdlib" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstring" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/ctype.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/exception" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/fstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/iosfwd" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/iostream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/math.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/memory" /> + + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/pthread.h" /> + + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/sstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stdarg.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stddef.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stdexcept" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stdio.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stdlib.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_algobase.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_algobase.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_alloc.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_alloc.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_auto_ptr.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_bvector.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_config.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_config_compat.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_config_compat_post.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_construct.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_ctraits_fns.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_ctype.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_cwchar.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_epilog.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_function.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_function_adaptors.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_function_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_hash_fun.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_iterator.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_iterator_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_locale.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_new.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_pair.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_prolog.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_range_errors.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_raw_storage_iter.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_relops_cont.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_set.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_site_config.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_fwd.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_fwd.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_hash.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_io.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_io.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_tempbuf.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_tempbuf.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_threads.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_threads.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_tree.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_tree.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_uninitialized.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_vector.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_vector.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/c_locale.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/type_traits.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl_user_config.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/string" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/typeinfo" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/using/cstring" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/using/fstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/using/iosfwd" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/using/iostream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/using/istream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/using/ostream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/using/sstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/vector" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/wrap_std/fstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/wrap_std/iosfwd" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/wrap_std/iostream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/wrap_std/sstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_buffer.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_clock.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_clock_ports.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_communication_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_event_finder.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_event_queue.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_export.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_fifo.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_fifo_ifs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_fifo_ports.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_interface.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_mutex.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_mutex_if.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_port.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_prim_channel.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_semaphore.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_semaphore_if.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_ifs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_ports.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_resolved.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_resolved_ports.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_rv.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/communication/sc_signal_rv_ports.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bit.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bit_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bit_proxies.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bv.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_bv_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_logic.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_lv.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_lv_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/bit/sc_proxy.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/fx.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_context.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fix.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fixed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fx_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxcast_switch.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxdefs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxnum.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxnum_observer.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxtype_params.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxval.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_fxval_observer.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_ufix.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/sc_ufixed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_ieee.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_mant.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_other_defs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_params.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_rep.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_utils.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_bigint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_biguint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_length_param.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbdefs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbexterns.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbutils.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_signed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_uint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_uint_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_unsigned.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/misc/sc_concatref.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/misc/sc_value_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_attribute.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_cmnhdr.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_constants.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_event.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_externs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_kernel_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_defs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_exps.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_friends.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_macros.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_module.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_module_name.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_object.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process_b.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process_host.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_sensitive.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_simcontext.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_time.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_ver.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_wait.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_wait_cthread.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_vcd_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_wif_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_hash.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_iostream.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_list.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_mempool.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_pq.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report_handler.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_temporary.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_vector.h" /> + + + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/frame_buffer.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/forms_rt.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/jdom.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/launcher.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowbase.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowmanager.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/util/jptf.jar" /> - + path="C:/intelFPGA_lite/16.1/ip/altera/common/lib/com.altera.megawizard2.jar" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/i2c_opencores_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_master_translator/altera_merlin_master_translator_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_master_agent/altera_merlin_master_agent_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_merlin_traffic_limiter/altera_merlin_traffic_limiter_hw.tcl" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 0 starting:Qsys "Qsys" @@ -1572,10 +2081,10 @@ Transform: CustomInstructionTransform No custom instruction connections, skipping transform - 19 modules, 78 connections]]> + 20 modules, 83 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform - 15 modules, 57 connections]]> + 16 modules, 61 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform @@ -1627,7 +2136,10 @@ - 31 modules, 120 connections]]> + + + + 33 modules, 128 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces nios2_gen2.data_master and nios2_gen2_data_master_translator.avalon_anti_master_0 @@ -1764,6 +2276,15 @@ + + + + + + + + + Transform merlin_domain_transform not run on matched interfaces jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0 and jtag_uart.avalon_jtag_slave Transform merlin_domain_transform not run on matched interfaces i2c_opencores_mipi_avalon_slave_0_translator.avalon_anti_slave_0 and i2c_opencores_mipi.avalon_slave_0 Transform merlin_domain_transform not run on matched interfaces i2c_opencores_camera_avalon_slave_0_translator.avalon_anti_slave_0 and i2c_opencores_camera.avalon_slave_0 @@ -1778,7 +2299,8 @@ Transform merlin_domain_transform not run on matched interfaces key_s1_translator.avalon_anti_slave_0 and key.s1 Transform merlin_domain_transform not run on matched interfaces mipi_reset_n_s1_translator.avalon_anti_slave_0 and mipi_reset_n.s1 Transform merlin_domain_transform not run on matched interfaces mipi_pwdn_n_s1_translator.avalon_anti_slave_0 and mipi_pwdn_n.s1 - 63 modules, 333 connections]]> + Transform merlin_domain_transform not run on matched interfaces EEE_IMGPROC_0_s1_translator.avalon_anti_slave_0 and EEE_IMGPROC_0.s1 + 68 modules, 359 connections]]> Transform: RouterTransform @@ -1828,7 +2350,10 @@ - 79 modules, 396 connections]]> + + + + 85 modules, 426 connections]]> Transform: TrafficLimiterTransform @@ -1836,7 +2361,7 @@ - 81 modules, 406 connections]]> + 87 modules, 436 connections]]> Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform @@ -1936,7 +2461,13 @@ - 112 modules, 485 connections]]> + + + + + + + 120 modules, 520 connections]]> Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform @@ -1945,18 +2476,26 @@ + Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0 + + + Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 + Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14 + + + 114 modules, 499 connections]]> + culprit="com_altera_sopcmodel_transforms_avalon_ClockCrossingTransform">124 modules, 548 connections]]> Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform - 114 modules, 501 connections]]> + 124 modules, 550 connections]]> Transform: InsertClockAndResetBridgesTransform @@ -1973,13 +2512,13 @@ - 119 modules, 621 connections]]> + 129 modules, 682 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform - 20 modules, 85 connections]]> + 21 modules, 90 connections]]> Transform: InitialInterconnectTransform 5 modules, 8 connections]]> Transform: TerminalIdAssignmentUpdateTransform @@ -2082,13 +2621,13 @@ - 21 modules, 89 connections]]> - 21 modules, 89 connections]]> + 22 modules, 94 connections]]> + 22 modules, 94 connections]]> Transform: InterruptMapperTransform - 22 modules, 93 connections]]> + 23 modules, 98 connections]]> Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform @@ -2105,7 +2644,8 @@ - 26 modules, 93 connections]]> + 27 modules, 97 connections]]> + Qsys" reuses EEE_IMGPROC "submodules/EEE_IMGPROC"]]> Qsys" reuses TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS"]]> Qsys" reuses TERASIC_CAMERA "submodules/TERASIC_CAMERA"]]> Qsys" reuses alt_vip_itc "submodules/alt_vipitc131_IS2Vid"]]> @@ -2130,254 +2670,1306 @@ Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> Qsys" reuses altera_reset_controller "submodules/altera_reset_controller"]]> + queue size: 24 starting:EEE_IMGPROC "submodules/EEE_IMGPROC" + Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"]]> queue size: 23 starting:TERASIC_AUTO_FOCUS "submodules/TERASIC_AUTO_FOCUS" Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0"]]> queue size: 22 starting:TERASIC_CAMERA "submodules/TERASIC_CAMERA" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/not_a_project_setup.tcl - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on - Command took 0.601s - Command took 0.919s + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.625s + Command took 0.719s + set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\ip\TERASIC_CAMERA\TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=TERASIC_CAMERA "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=VIDEO_W=D\"640\";VIDEO_H=D\"480\";" --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.614s + Command took 0.704s Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"]]> queue size: 21 starting:alt_vip_itc "submodules/alt_vipitc131_IS2Vid" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/not_a_project_setup.tcl - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/altera_lite/16.0/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on - Command took 0.544s - Command took 0.880s + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.616s + Command took 0.718s + set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\intelfpga_lite\16.1\ip\altera\clocked_video_output\src_hdl\alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=alt_vipitc131_IS2Vid "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=NUMBER_OF_COLOUR_PLANES=D\"3\";COLOUR_PLANES_ARE_IN_PARALLEL=D\"1\";BPS=D\"8\";INTERLACED=D\"0\";H_ACTIVE_PIXELS=D\"640\";V_ACTIVE_LINES=D\"480\";ACCEPT_COLOURS_IN_SEQ=D\"0\";FIFO_DEPTH=D\"640\";CLOCKS_ARE_SAME=D\"0\";USE_CONTROL=D\"0\";NO_OF_MODES=D\"1\";THRESHOLD=D\"639\";STD_WIDTH=D\"1\";GENERATE_SYNC=D\"0\";USE_EMBEDDED_SYNCS=D\"0\";AP_LINE=D\"0\";V_BLANK=D\"0\";H_BLANK=D\"0\";H_SYNC_LENGTH=D\"96\";H_FRONT_PORCH=D\"16\";H_BACK_PORCH=D\"48\";V_SYNC_LENGTH=D\"2\";V_FRONT_PORCH=D\"10\";V_BACK_PORCH=D\"33\";F_RISING_EDGE=D\"0\";F_FALLING_EDGE=D\"0\";FIELD0_V_RISING_EDGE=D\"0\";FIELD0_V_BLANK=D\"0\";FIELD0_V_SYNC_LENGTH=D\"0\";FIELD0_V_FRONT_PORCH=D\"0\";FIELD0_V_BACK_PORCH=D\"0\";ANC_LINE=D\"0\";FIELD0_ANC_LINE=D\"0\";" --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.588s + Command took 0.750s Qsys" instantiated alt_vip_itc "alt_vip_itc_0"]]> queue size: 20 starting:alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0" - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp160_avalon_st_input"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp160_avalon_st_output"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp160_pulling_width_adapter"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp160_pushing_width_adapter"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp160_clock_reset"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset"]]> dut" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]> Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"]]> + queue size: 343 starting:alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2" + alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"]]> + queue size: 341 starting:alt_au "submodules/alt_cusp161_au" + alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"]]> + queue size: 332 starting:alt_reg "submodules/alt_cusp161_reg" + alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 331 starting:alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16" + alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"]]> + queue size: 307 starting:alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input" + alt_vip_vfb_0" instantiated alt_avalon_st_input "din"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 302 starting:alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output" + alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 298 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo" + alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 296 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter" + alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 290 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter" + alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 256 starting:alt_pc "submodules/alt_cusp161_pc" + alt_vip_vfb_0" instantiated alt_pc "pc0"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 196 starting:alt_cmp "submodules/alt_cusp161_cmp" + alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 146 starting:alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset" + alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> queue size: 218 starting:altpll "submodules/Qsys_altpll_0" - - set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --source=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0018_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on - Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing - Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings - Peak virtual memory: 1399 megabytes - Processing ended: Tue Mar 30 09:18:43 2021 - Elapsed time: 00:00:01 - Total CPU time (on all processors): 00:00:00 - Command took 0.958s - Analyser output file not present: Qsys_altpll_0.v.xml - /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0]]> - /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory) + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --source=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.841s Qsys" instantiated altpll "altpll_0"]]> + queue size: 217 starting:i2c_opencores "submodules/i2c_opencores" + Qsys" instantiated i2c_opencores "i2c_opencores_camera"]]> + queue size: 215 starting:altera_avalon_jtag_uart "submodules/Qsys_jtag_uart" + Starting RTL generation for module 'Qsys_jtag_uart' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_jtag_uart' + Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"]]> + queue size: 214 starting:altera_avalon_pio "submodules/Qsys_key" + Starting RTL generation for module 'Qsys_key' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_key' + Qsys" instantiated altera_avalon_pio "key"]]> + queue size: 213 starting:altera_avalon_pio "submodules/Qsys_led" + Starting RTL generation for module 'Qsys_led' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_led' + Qsys" instantiated altera_avalon_pio "led"]]> + queue size: 212 starting:altera_avalon_pio "submodules/Qsys_mipi_pwdn_n" + Starting RTL generation for module 'Qsys_mipi_pwdn_n' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_mipi_pwdn_n' + Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"]]> + queue size: 210 starting:altera_nios2_gen2 "submodules/Qsys_nios2_gen2" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + nios2_gen2" reuses altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu"]]> + Qsys" instantiated altera_nios2_gen2 "nios2_gen2"]]> + queue size: 144 starting:altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu" + Starting RTL generation for module 'Qsys_nios2_gen2_cpu' + Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2021.05.27 17:51:00 (*) Starting Nios II generation + # 2021.05.27 17:51:00 (*) Checking for plaintext license. + # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ + # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty + # 2021.05.27 17:51:01 (*) Plaintext license not found. + # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation). + # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ + # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty + # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) + # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings + # 2021.05.27 17:51:01 (*) Creating all objects for CPU + # 2021.05.27 17:51:01 (*) Testbench + # 2021.05.27 17:51:02 (*) Instruction decoding + # 2021.05.27 17:51:02 (*) Instruction fields + # 2021.05.27 17:51:02 (*) Instruction decodes + # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms + # 2021.05.27 17:51:02 (*) Instruction controls + # 2021.05.27 17:51:02 (*) Pipeline frontend + # 2021.05.27 17:51:02 (*) Pipeline backend + # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects + # 2021.05.27 17:51:06 (*) Creating encrypted RTL + # 2021.05.27 17:51:07 (*) Done Nios II generation + Done RTL generation for module 'Qsys_nios2_gen2_cpu' + nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"]]> + queue size: 210 starting:altera_avalon_onchip_memory2 "submodules/Qsys_onchip_memory2_0" + Starting RTL generation for module 'Qsys_onchip_memory2_0' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_onchip_memory2_0' + Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"]]> + queue size: 209 starting:altera_avalon_new_sdram_controller "submodules/Qsys_sdram" + Starting RTL generation for module 'Qsys_sdram' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_sdram' + Qsys" instantiated altera_avalon_new_sdram_controller "sdram"]]> + queue size: 208 starting:altera_avalon_pio "submodules/Qsys_sw" + Starting RTL generation for module 'Qsys_sw' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_sw' + Qsys" instantiated altera_avalon_pio "sw"]]> + queue size: 207 starting:altera_avalon_sysid_qsys "submodules/Qsys_sysid_qsys" + Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"]]> + queue size: 206 starting:altera_avalon_timer "submodules/Qsys_timer" + Starting RTL generation for module 'Qsys_timer' + Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_timer' + Qsys" instantiated altera_avalon_timer "timer"]]> + queue size: 205 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_0" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 113 modules, 386 connections]]> + Transform: MMTransform + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.029s/0.039s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.012s/0.013s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.013s/0.014s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.012s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.017s/0.027s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.013s/0.016s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.012s/0.014s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.012s/0.013s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.001s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.016s/0.024s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.001s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.008s + Timing: COM:3/0.012s/0.013s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.011s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.011s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.015s/0.022s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.011s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.012s/0.015s + 128 modules, 431 connections]]> + Transform: ResetAdaptation + mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> + mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"]]> + queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> + queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> + queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> + queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> + queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> + queue size: 92 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router" + mm_interconnect_0" instantiated altera_merlin_router "router"]]> + queue size: 91 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001" + mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> + queue size: 90 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002" + mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> + queue size: 86 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006" + mm_interconnect_0" instantiated altera_merlin_router "router_006"]]> + queue size: 75 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" + mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v]]> + queue size: 73 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> + queue size: 72 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> + queue size: 71 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> + queue size: 67 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 56 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> + queue size: 52 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"]]> + queue size: 51 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"]]> + queue size: 41 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux" + mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 40 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001" + mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 39 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" + mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> + queue size: 35 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> + mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> + queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + queue size: 327 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_1" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 22 modules, 64 connections]]> + Transform: MMTransform + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 22 modules, 64 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 22 modules, 64 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 22 modules, 64 connections]]> + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.012s/0.013s + 23 modules, 67 connections]]> + Transform: ResetAdaptation + mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> + mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> + mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002"]]> + mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> + mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> + mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> + mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux"]]> + mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux"]]> + mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> + mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> + mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> + mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> + mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter"]]> + Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"]]> + queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> + queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> + queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> + queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> + queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> + queue size: 13 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router" + mm_interconnect_1" instantiated altera_merlin_router "router"]]> + queue size: 11 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002" + mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> + queue size: 10 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" + mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> + queue size: 9 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux" + mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> + queue size: 7 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux" + mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 6 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux" + mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> + queue size: 5 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux" + mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 3 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" + mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> + queue size: 1 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> + mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> + queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + queue size: 347 starting:altera_irq_mapper "submodules/Qsys_irq_mapper" + Qsys" instantiated altera_irq_mapper "irq_mapper"]]> + queue size: 346 starting:altera_reset_controller "submodules/altera_reset_controller" + Qsys" instantiated altera_reset_controller "rst_controller"]]> + + + + + + + + + + + + + + queue size: 24 starting:EEE_IMGPROC "submodules/EEE_IMGPROC" + Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0"]]> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_AUTO_FOCUS/TERASIC_AUTO_FOCUS_hw.tcl" /> @@ -2432,60 +4024,65 @@ child process exited abnormally name="TERASIC_CAMERA"> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA_hw.tcl" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_RGB.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/CAMERA_Bayer.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer2RGB.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/Bayer_LineBuffer.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/rgb_fifo.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add2.v" /> + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/add4.v" /> queue size: 22 starting:TERASIC_CAMERA "submodules/TERASIC_CAMERA" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/not_a_project_setup.tcl - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on - Command took 0.601s - Command took 0.919s + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/TERASIC_CAMERA/TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0002_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.625s + Command took 0.719s + set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\ip\TERASIC_CAMERA\TERASIC_CAMERA.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0005_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=TERASIC_CAMERA "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=VIDEO_W=D\"640\";VIDEO_H=D\"480\";" --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.614s + Command took 0.704s Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0"]]> @@ -2498,95 +4095,100 @@ child process exited abnormally name="alt_vipitc131_IS2Vid"> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/alt_vip_itc_hw.tcl" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_sync_compare.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_calculate_mode.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_control.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_mode_banks.sv" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid_statemachine.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_fifo.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_generic_count.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_to_binary.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_sync.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_trigger_sync.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_sync_generation.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_frame_counter.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_common_sample_counter.v" /> + path="C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/alt_vipitc131_cvo.sdc" /> queue size: 21 starting:alt_vip_itc "submodules/alt_vipitc131_IS2Vid" set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_sh -t /tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/not_a_project_setup.tcl - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/home/ed/altera_lite/16.0/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0012_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on - Command took 0.544s - Command took 0.880s + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/intelfpga_lite/16.1/ip/altera/clocked_video_output/src_hdl/alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0006_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.616s + Command took 0.718s + set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_sh.exe -t C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/not_a_project_setup.tcl + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:\intelfpga_lite\16.1\ip\altera\clocked_video_output\src_hdl\alt_vipitc131_IS2Vid.sv --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0007_sopcqmap/ --set=HDL_INTERFACE_INSTANCE_NAME=inst --set=HDL_INTERFACE_INSTANCE_ENTITY=alt_vipitc131_IS2Vid "--set=HDL_INTERFACE_INSTANCE_PARAMETERS=NUMBER_OF_COLOUR_PLANES=D\"3\";COLOUR_PLANES_ARE_IN_PARALLEL=D\"1\";BPS=D\"8\";INTERLACED=D\"0\";H_ACTIVE_PIXELS=D\"640\";V_ACTIVE_LINES=D\"480\";ACCEPT_COLOURS_IN_SEQ=D\"0\";FIFO_DEPTH=D\"640\";CLOCKS_ARE_SAME=D\"0\";USE_CONTROL=D\"0\";NO_OF_MODES=D\"1\";THRESHOLD=D\"639\";STD_WIDTH=D\"1\";GENERATE_SYNC=D\"0\";USE_EMBEDDED_SYNCS=D\"0\";AP_LINE=D\"0\";V_BLANK=D\"0\";H_BLANK=D\"0\";H_SYNC_LENGTH=D\"96\";H_FRONT_PORCH=D\"16\";H_BACK_PORCH=D\"48\";V_SYNC_LENGTH=D\"2\";V_FRONT_PORCH=D\"10\";V_BACK_PORCH=D\"33\";F_RISING_EDGE=D\"0\";F_FALLING_EDGE=D\"0\";FIELD0_V_RISING_EDGE=D\"0\";FIELD0_V_BLANK=D\"0\";FIELD0_V_SYNC_LENGTH=D\"0\";FIELD0_V_FRONT_PORCH=D\"0\";FIELD0_V_BACK_PORCH=D\"0\";ANC_LINE=D\"0\";FIELD0_ANC_LINE=D\"0\";" --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.588s + Command took 0.750s Qsys" instantiated alt_vip_itc "alt_vip_itc_0"]]> @@ -2613,1276 +4215,1395 @@ child process exited abnormally value="<frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>640</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>480</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>false</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>true</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>true</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>false</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>1024</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>4</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>1024</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>4</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>false</VFB_DROP_INVALID_FIELDS></frameBufferParams>" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/alt_vip_vfb.cpp" /> + + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_constants.h" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_elementclass_info.h" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_vfb_hwfast.hpp" /> + - + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cdfg_types.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cusp_synth.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_exception.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_lib_types.h" /> + - + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_au.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_eb.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_mm.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_st.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_cmp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fifo.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fifo_paged.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fp_au.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fp_cmp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fp_mult.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_gpio.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_immed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_mac.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_mem.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_mult.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_multadd.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_reg.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_shift.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_tapped_delay.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_bus.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_eb_channel.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_st_channel.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_debug.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_exit.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_overlay.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_pc.h" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cassert" /> - - - - - - - - - - - - - - - - - - - - - - - - - - - - + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cctype" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/climits" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/config/stl_confix.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/config/stl_cusp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/config/stlcomp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstddef" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstdio" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstdlib" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cstring" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/ctype.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/exception" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/fstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/iosfwd" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/iostream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/math.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/memory" /> + + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/pthread.h" /> + + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/sstream" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stdarg.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stddef.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stdexcept" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stdio.h" /> + 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path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_hash.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_iostream.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_list.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_mempool.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_pq.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report_handler.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_temporary.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_vector.h" /> + + + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/frame_buffer.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/forms_rt.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/jdom.jar" /> - + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/launcher.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowbase.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowmanager.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/util/jptf.jar" /> - - - - - + path="C:/intelFPGA_lite/16.1/ip/altera/common/lib/com.altera.megawizard2.jar" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/alt_vip_vfb.cpp" /> + + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_constants.h" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_elementclass_info.h" /> + path="C:/intelfpga_lite/16.1/ip/altera/frame_buffer/lib/vip_vfb_hwfast.hpp" /> + - + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cdfg_types.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_cusp_synth.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_exception.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/alt_lib_types.h" /> + - + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_au.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_eb.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_mm.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_avalon_st.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_cmp.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fifo.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fifo_paged.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/fuLib/alt_fp_au.h" /> + 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path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_eb_channel.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_avalon_st_channel.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_debug.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_exit.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_overlay.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/include/cusp/simlib/alt_pc.h" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cassert" /> - - - - - - - - - - - - - - - - - - - - - - - - - - - - + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/cctype" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/climits" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/config/stl_confix.h" /> + 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path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_relops_cont.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_set.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_site_config.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_fwd.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_fwd.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_hash.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_io.c" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_string_io.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/synthinclude/stlport/stl/_tempbuf.c" /> + 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path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_mant.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_other_defs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_params.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_rep.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/fx/scfx_utils.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_bigint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_biguint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_int_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_length_param.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbdefs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbexterns.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_nbutils.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_signed.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_uint.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_uint_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/int/sc_unsigned.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/misc/sc_concatref.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/datatypes/misc/sc_value_base.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_attribute.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_cmnhdr.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_constants.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_event.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_externs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_kernel_ids.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_defs.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_exps.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_lambda_friends.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_macros.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_module.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_module_name.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_object.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process_b.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_process_host.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_sensitive.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_simcontext.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_time.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_ver.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_wait.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/kernel/sc_wait_cthread.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_vcd_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/tracing/sc_wif_trace.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_hash.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_iostream.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_list.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_mempool.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_pq.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_report_handler.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_string.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_temporary.h" /> + path="C:/intelFPGA_lite/16.1/quartus/cusp/systemc/include/sysc/utils/sc_vector.h" /> + + + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/frame_buffer.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/forms_rt.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/frame_buffer/lib/ip_toolbench/jdom.jar" /> - + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/launcher.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowbase.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/flowmanager.jar" /> + path="C:/intelFPGA_lite/16.1/ip/altera/common/ip_toolbench/v1.3.0/bin/util/jptf.jar" /> - - - - - + path="C:/intelFPGA_lite/16.1/ip/altera/common/lib/com.altera.megawizard2.jar" /> queue size: 20 starting:alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0" - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp160_avalon_st_input"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp160_avalon_st_output"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp160_pulling_width_adapter"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp160_avalon_mm_bursting_master_fifo"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp160_pushing_width_adapter"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp160_muxhot16"]]> - alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp160_pc"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp160_muxbin2"]]> - alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp160_au"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp160_cmp"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp160_reg"]]> - dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp160_clock_reset"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16"]]> + alt_vip_vfb_0" reuses alt_pc "submodules/alt_cusp161_pc"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2"]]> + alt_vip_vfb_0" reuses alt_au "submodules/alt_cusp161_au"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_cmp "submodules/alt_cusp161_cmp"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + alt_vip_vfb_0" reuses alt_reg "submodules/alt_cusp161_reg"]]> + dut" reuses alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset"]]> dut" reuses alt_vip_vfb "submodules/Qsys_alt_vip_vfb_0"]]> Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0"]]> + queue size: 343 starting:alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2" + alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"]]> + queue size: 341 starting:alt_au "submodules/alt_cusp161_au" + alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"]]> + queue size: 332 starting:alt_reg "submodules/alt_cusp161_reg" + alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 331 starting:alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16" + alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"]]> + queue size: 307 starting:alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input" + alt_vip_vfb_0" instantiated alt_avalon_st_input "din"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 302 starting:alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output" + alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 298 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo" + alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 296 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter" + alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 290 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter" + alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 256 starting:alt_pc "submodules/alt_cusp161_pc" + alt_vip_vfb_0" instantiated alt_pc "pc0"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 196 starting:alt_cmp "submodules/alt_cusp161_cmp" + alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + queue size: 146 starting:alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset" + alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> @@ -4061,45 +5782,23 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_altpll/altera_avalon_altpll_hw.tcl" /> queue size: 218 starting:altpll "submodules/Qsys_altpll_0" - - set ALTERA_HW_TCL_KEEP_TEMP_FILES=1 to retain temp files - Command: /home/ed/altera_lite/16.0/quartus/linux64/quartus_map not_a_project --generate_hdl_interface=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --source=/tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=/tmp/alt8716_2763057626446894966.dir/0018_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on - Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing - Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings - Peak virtual memory: 1399 megabytes - Processing ended: Tue Mar 30 09:18:43 2021 - Elapsed time: 00:00:01 - Total CPU time (on all processors): 00:00:00 - Command took 0.958s - Analyser output file not present: Qsys_altpll_0.v.xml - /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0]]> - /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory) + Command: C:/intelfpga_lite/16.1/quartus\bin64/quartus_map.exe not_a_project --generate_hdl_interface=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --source=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0008_sopcgen/Qsys_altpll_0.v --set=HDL_INTERFACE_OUTPUT_PATH=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0009_sopcqmap/ --ini=disable_check_quartus_compatibility_qsys_only=on + Command took 0.841s Qsys" instantiated altpll "altpll_0"]]> @@ -4110,22 +5809,46 @@ child process exited abnormally kind="i2c_opencores" version="12.0" name="i2c_opencores"> - + + + + + + + + path="C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/ip/i2c_opencores/i2c_opencores_hw.tcl" /> - + + queue size: 217 starting:i2c_opencores "submodules/i2c_opencores" + Qsys" instantiated i2c_opencores "i2c_opencores_camera"]]> + @@ -4143,22 +5866,33 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" /> - + + queue size: 215 starting:altera_avalon_jtag_uart "submodules/Qsys_jtag_uart" + Starting RTL generation for module 'Qsys_jtag_uart' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_jtag_uart' + Qsys" instantiated altera_avalon_jtag_uart "jtag_uart"]]> + @@ -4180,22 +5914,33 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> - + + queue size: 214 starting:altera_avalon_pio "submodules/Qsys_key" + Starting RTL generation for module 'Qsys_key' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_key' + Qsys" instantiated altera_avalon_pio "key"]]> + @@ -4217,22 +5962,33 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> - + + queue size: 213 starting:altera_avalon_pio "submodules/Qsys_led" + Starting RTL generation for module 'Qsys_led' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_led' + Qsys" instantiated altera_avalon_pio "led"]]> + @@ -4254,22 +6010,33 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> - + + queue size: 212 starting:altera_avalon_pio "submodules/Qsys_mipi_pwdn_n" + Starting RTL generation for module 'Qsys_mipi_pwdn_n' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_mipi_pwdn_n' + Qsys" instantiated altera_avalon_pio "mipi_pwdn_n"]]> + @@ -4280,7 +6047,7 @@ child process exited abnormally + value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" /> @@ -4308,13 +6075,14 @@ child process exited abnormally + value="<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x386A0' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /><slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /><slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /><slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /><slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /><slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /><slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /><slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /><slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /><slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='EEE_IMGPROC_0.s1' start='0x42000' end='0x42020' type='EEE_IMGPROC.s1' /></address-map>" /> + @@ -4471,29 +6239,140 @@ child process exited abnormally - - + + + + + + + + + + + + + + + + + + + + path="C:/intelfpga_lite/16.1/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" /> - + + + - + + queue size: 210 starting:altera_nios2_gen2 "submodules/Qsys_nios2_gen2" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + nios2_gen2" reuses altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu"]]> + Qsys" instantiated altera_nios2_gen2 "nios2_gen2"]]> + queue size: 144 starting:altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu" + Starting RTL generation for module 'Qsys_nios2_gen2_cpu' + Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2021.05.27 17:51:00 (*) Starting Nios II generation + # 2021.05.27 17:51:00 (*) Checking for plaintext license. + # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ + # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty + # 2021.05.27 17:51:01 (*) Plaintext license not found. + # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation). + # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ + # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty + # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) + # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings + # 2021.05.27 17:51:01 (*) Creating all objects for CPU + # 2021.05.27 17:51:01 (*) Testbench + # 2021.05.27 17:51:02 (*) Instruction decoding + # 2021.05.27 17:51:02 (*) Instruction fields + # 2021.05.27 17:51:02 (*) Instruction decodes + # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms + # 2021.05.27 17:51:02 (*) Instruction controls + # 2021.05.27 17:51:02 (*) Pipeline frontend + # 2021.05.27 17:51:02 (*) Pipeline backend + # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects + # 2021.05.27 17:51:06 (*) Creating encrypted RTL + # 2021.05.27 17:51:07 (*) Done Nios II generation + Done RTL generation for module 'Qsys_nios2_gen2_cpu' + nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"]]> + + + value="ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1" /> + @@ -4507,6 +6386,7 @@ child process exited abnormally + @@ -4522,22 +6402,33 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" /> - + + queue size: 210 starting:altera_avalon_onchip_memory2 "submodules/Qsys_onchip_memory2_0" + Starting RTL generation for module 'Qsys_onchip_memory2_0' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_onchip_memory2_0' + Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0"]]> + @@ -4564,22 +6455,37 @@ child process exited abnormally - + + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/altera_avalon_new_sdram_controller_hw.tcl" /> - + + queue size: 209 starting:altera_avalon_new_sdram_controller "submodules/Qsys_sdram" + Starting RTL generation for module 'Qsys_sdram' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_sdram' + Qsys" instantiated altera_avalon_new_sdram_controller "sdram"]]> + @@ -4601,41 +6507,60 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" /> - + + queue size: 208 starting:altera_avalon_pio "submodules/Qsys_sw" + Starting RTL generation for module 'Qsys_sw' + Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_sw' + Qsys" instantiated altera_avalon_pio "sw"]]> + - - + + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_sysid_qsys/altera_avalon_sysid_qsys_hw.tcl" /> - + + queue size: 207 starting:altera_avalon_sysid_qsys "submodules/Qsys_sysid_qsys" + Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys"]]> + @@ -4654,396 +6579,1365 @@ child process exited abnormally - + + + + path="C:/intelfpga_lite/16.1/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" /> - + + queue size: 206 starting:altera_avalon_timer "submodules/Qsys_timer" + Starting RTL generation for module 'Qsys_timer' + Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ] + Done RTL generation for module 'Qsys_timer' + Qsys" instantiated altera_avalon_timer "timer"]]> + - - +};set_instance_parameter_value {nios2_gen2_instruction_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {nios2_gen2_instruction_master_agent} {ID} {1};set_instance_parameter_value {nios2_gen2_instruction_master_agent} {BURSTWRAP_VALUE} {3};set_instance_parameter_value {nios2_gen2_instruction_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {nios2_gen2_instruction_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {nios2_gen2_instruction_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {nios2_gen2_instruction_master_agent} {USE_WRITERESPONSE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ST_DATA_W} {97};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ID} {5};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent} {ECC_ENABLE} {0};add_instance {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {jtag_uart_avalon_jtag_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {i2c_opencores_mipi_avalon_slave_0_agent} {altera_merlin_slave_agent};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_DATA_H} {31};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_DATA_L} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {ST_DATA_W} {97};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {ID} {4};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent} {ECC_ENABLE} {0};add_instance {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {i2c_opencores_camera_avalon_slave_0_agent} {altera_merlin_slave_agent};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_DATA_H} {31};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_DATA_L} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {ST_DATA_W} {97};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {ID} {3};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent} {ECC_ENABLE} {0};add_instance {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sysid_qsys_control_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sysid_qsys_control_slave_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {sysid_qsys_control_slave_agent} {ST_DATA_W} {97};set_instance_parameter_value {sysid_qsys_control_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sysid_qsys_control_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sysid_qsys_control_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sysid_qsys_control_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sysid_qsys_control_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sysid_qsys_control_slave_agent} {ID} {13};set_instance_parameter_value {sysid_qsys_control_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent} {ECC_ENABLE} {0};add_instance {sysid_qsys_control_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sysid_qsys_control_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {nios2_gen2_debug_mem_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {ST_DATA_W} {97};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {ID} {10};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent} {ECC_ENABLE} {0};add_instance {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {nios2_gen2_debug_mem_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {altera_merlin_slave_agent};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_DATA_H} {31};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_DATA_L} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {ST_DATA_W} {97};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {ID} {1};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent} {ECC_ENABLE} {0};add_instance {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {altpll_0_pll_slave_agent} {altera_merlin_slave_agent};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_DATA_H} {31};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_DATA_L} {0};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {altpll_0_pll_slave_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {altpll_0_pll_slave_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {altpll_0_pll_slave_agent} {ST_DATA_W} {97};set_instance_parameter_value {altpll_0_pll_slave_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {altpll_0_pll_slave_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {altpll_0_pll_slave_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {altpll_0_pll_slave_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {altpll_0_pll_slave_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {altpll_0_pll_slave_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {altpll_0_pll_slave_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {altpll_0_pll_slave_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {altpll_0_pll_slave_agent} {ID} {2};set_instance_parameter_value {altpll_0_pll_slave_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {altpll_0_pll_slave_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {altpll_0_pll_slave_agent} {ECC_ENABLE} {0};add_instance {altpll_0_pll_slave_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {altpll_0_pll_slave_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {onchip_memory2_0_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {onchip_memory2_0_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {onchip_memory2_0_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {onchip_memory2_0_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ID} {11};set_instance_parameter_value {onchip_memory2_0_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent} {ECC_ENABLE} {0};add_instance {onchip_memory2_0_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {onchip_memory2_0_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {timer_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {timer_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {timer_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {timer_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {timer_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {timer_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {timer_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {timer_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {timer_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {timer_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {timer_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {timer_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {timer_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {timer_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {timer_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {timer_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {timer_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {timer_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {timer_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {timer_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {timer_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {timer_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {timer_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {timer_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {timer_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {timer_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {timer_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {timer_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {timer_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {timer_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {timer_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {timer_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {timer_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {timer_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {timer_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {timer_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {timer_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {timer_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {timer_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {timer_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {timer_s1_agent} {ID} {14};set_instance_parameter_value {timer_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {timer_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {timer_s1_agent} {ECC_ENABLE} {0};add_instance {timer_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {timer_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {led_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {led_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {led_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {led_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {led_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {led_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {led_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {led_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {led_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {led_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {led_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {led_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {led_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {led_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {led_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {led_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {led_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {led_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {led_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {led_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {led_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {led_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {led_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {led_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {led_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {led_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {led_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {led_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {led_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {led_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {led_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {led_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {led_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {led_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {led_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {led_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {led_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {led_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {led_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {led_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {led_s1_agent} {ID} {7};set_instance_parameter_value {led_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {led_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {led_s1_agent} {ECC_ENABLE} {0};add_instance {led_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {led_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {led_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {led_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {led_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {led_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {led_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {led_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {led_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {led_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {led_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {led_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {led_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {led_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {led_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sw_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sw_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {sw_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {sw_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {sw_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {sw_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {sw_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {sw_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {sw_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {sw_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {sw_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {sw_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {sw_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {sw_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {sw_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {sw_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {sw_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {sw_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {sw_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {sw_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {sw_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {sw_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {sw_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sw_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {sw_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {sw_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {sw_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {sw_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {sw_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {sw_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sw_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {sw_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {sw_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sw_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {sw_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sw_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sw_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {sw_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sw_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {sw_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {sw_s1_agent} {ID} {12};set_instance_parameter_value {sw_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sw_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sw_s1_agent} {ECC_ENABLE} {0};add_instance {sw_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sw_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {key_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {key_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {key_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {key_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {key_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {key_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {key_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {key_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {key_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {key_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {key_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {key_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {key_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {key_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {key_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {key_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {key_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {key_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {key_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {key_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {key_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {key_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {key_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {key_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {key_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {key_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {key_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {key_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {key_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {key_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {key_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {key_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {key_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {key_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {key_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {key_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {key_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {key_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {key_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {key_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {key_s1_agent} {ID} {6};set_instance_parameter_value {key_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {key_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {key_s1_agent} {ECC_ENABLE} {0};add_instance {key_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {key_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {key_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {key_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {key_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {key_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {key_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {key_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {key_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {key_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {key_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {key_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {key_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {key_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {key_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mipi_reset_n_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {mipi_reset_n_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mipi_reset_n_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {mipi_reset_n_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {mipi_reset_n_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mipi_reset_n_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mipi_reset_n_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mipi_reset_n_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mipi_reset_n_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mipi_reset_n_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mipi_reset_n_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mipi_reset_n_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mipi_reset_n_s1_agent} {ID} {9};set_instance_parameter_value {mipi_reset_n_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mipi_reset_n_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mipi_reset_n_s1_agent} {ECC_ENABLE} {0};add_instance {mipi_reset_n_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mipi_reset_n_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {mipi_pwdn_n_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {ID} {8};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent} {ECC_ENABLE} {0};add_instance {mipi_pwdn_n_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {mipi_pwdn_n_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {EEE_IMGPROC_0_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_ORI_BURST_SIZE_H} {96};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_ORI_BURST_SIZE_L} {94};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_RESPONSE_STATUS_H} {93};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_RESPONSE_STATUS_L} {92};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BURST_SIZE_H} {69};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BURST_SIZE_L} {67};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BEGIN_BURST} {74};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_PROTECTION_H} {87};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_PROTECTION_L} {85};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BURSTWRAP_H} {66};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BURSTWRAP_L} {64};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_ADDR_H} {54};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_TRANS_COMPRESSED_READ} {55};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_TRANS_READ} {58};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_DATA_H} {31};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_SRC_ID_H} {79};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_SRC_ID_L} {76};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_DEST_ID_H} {83};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_DEST_ID_L} {80};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {ST_CHANNEL_W} {15};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {ST_DATA_W} {97};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {MAX_BURSTWRAP} {7};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {ID} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent} {ECC_ENABLE} {0};add_instance {EEE_IMGPROC_0_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {98};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {EEE_IMGPROC_0_s1_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {EEE_IMGPROC_0_s1_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {11 10 14 1 3 4 8 9 6 12 7 2 13 5 0 };set_instance_parameter_value {router} {CHANNEL_ID} {000000010000000 000000000010000 000000100000000 000000000100000 000000000000100 000000000000010 010000000000000 001000000000000 000100000000000 000010000000000 000001000000000 000000001000000 000000000001000 000000000000001 100000000000000 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both both both both both both both both read read both both read both both };set_instance_parameter_value {router} {START_ADDRESS} {0x20000 0x40800 0x41000 0x41020 0x41040 0x41060 0x41080 0x41090 0x410a0 0x410b0 0x410c0 0x410d0 0x410e0 0x410e8 0x42000 };set_instance_parameter_value {router} {END_ADDRESS} {0x40000 0x41000 0x41020 0x41040 0x41060 0x41080 0x41090 0x410a0 0x410b0 0x410c0 0x410d0 0x410e0 0x410e8 0x410f0 0x42020 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {54};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router} {PKT_TRANS_READ} {58};set_instance_parameter_value {router} {ST_DATA_W} {97};set_instance_parameter_value {router} {ST_CHANNEL_W} {15};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {7};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {11};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {11 10 };set_instance_parameter_value {router_001} {CHANNEL_ID} {10 01 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x20000 0x40800 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x40000 0x41000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {54};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_001} {ST_DATA_W} {97};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {1};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {11};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {1 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {54};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_002} {ST_DATA_W} {97};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {router_003} {altera_merlin_router};set_instance_parameter_value {router_003} {DESTINATION_ID} {0 };set_instance_parameter_value {router_003} {CHANNEL_ID} {1 };set_instance_parameter_value {router_003} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_003} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_003} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_003} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_003} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_003} {SPAN_OFFSET} {};set_instance_parameter_value {router_003} {PKT_ADDR_H} {54};set_instance_parameter_value {router_003} {PKT_ADDR_L} {36};set_instance_parameter_value {router_003} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_003} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_003} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_003} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_003} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_003} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_003} {ST_DATA_W} {97};set_instance_parameter_value {router_003} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_003} {DECODER_TYPE} {1};set_instance_parameter_value {router_003} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_003} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_003} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_003} {MEMORY_ALIASING_DECODE} {0};add_instance {router_004} {altera_merlin_router};set_instance_parameter_value {router_004} {DESTINATION_ID} {0 };set_instance_parameter_value {router_004} {CHANNEL_ID} {1 };set_instance_parameter_value {router_004} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_004} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_004} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_004} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_004} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_004} {SPAN_OFFSET} {};set_instance_parameter_value {router_004} {PKT_ADDR_H} {54};set_instance_parameter_value {router_004} {PKT_ADDR_L} {36};set_instance_parameter_value {router_004} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_004} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_004} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_004} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_004} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_004} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_004} {ST_DATA_W} {97};set_instance_parameter_value {router_004} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_004} {DECODER_TYPE} {1};set_instance_parameter_value {router_004} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_004} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_004} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_004} {MEMORY_ALIASING_DECODE} {0};add_instance {router_005} {altera_merlin_router};set_instance_parameter_value {router_005} {DESTINATION_ID} {0 };set_instance_parameter_value {router_005} {CHANNEL_ID} {1 };set_instance_parameter_value {router_005} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_005} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_005} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_005} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_005} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_005} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_005} {SPAN_OFFSET} {};set_instance_parameter_value {router_005} {PKT_ADDR_H} {54};set_instance_parameter_value {router_005} {PKT_ADDR_L} {36};set_instance_parameter_value {router_005} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_005} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_005} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_005} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_005} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_005} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_005} {ST_DATA_W} {97};set_instance_parameter_value {router_005} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_005} {DECODER_TYPE} {1};set_instance_parameter_value {router_005} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_005} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_005} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_005} {MEMORY_ALIASING_DECODE} {0};add_instance {router_006} {altera_merlin_router};set_instance_parameter_value {router_006} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_006} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_006} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_006} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_006} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_006} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_006} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_006} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_006} {SPAN_OFFSET} {};set_instance_parameter_value {router_006} {PKT_ADDR_H} {54};set_instance_parameter_value {router_006} {PKT_ADDR_L} {36};set_instance_parameter_value {router_006} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_006} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_006} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_006} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_006} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_006} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_006} {ST_DATA_W} {97};set_instance_parameter_value {router_006} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_006} {DECODER_TYPE} {1};set_instance_parameter_value {router_006} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_006} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_006} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_006} {MEMORY_ALIASING_DECODE} {0};add_instance {router_007} {altera_merlin_router};set_instance_parameter_value {router_007} {DESTINATION_ID} {0 };set_instance_parameter_value {router_007} {CHANNEL_ID} {1 };set_instance_parameter_value {router_007} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_007} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_007} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_007} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_007} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_007} {SPAN_OFFSET} {};set_instance_parameter_value {router_007} {PKT_ADDR_H} {54};set_instance_parameter_value {router_007} {PKT_ADDR_L} {36};set_instance_parameter_value {router_007} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_007} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_007} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_007} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_007} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_007} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_007} {ST_DATA_W} {97};set_instance_parameter_value {router_007} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_007} {DECODER_TYPE} {1};set_instance_parameter_value {router_007} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_007} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_007} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_007} {MEMORY_ALIASING_DECODE} {0};add_instance {router_008} {altera_merlin_router};set_instance_parameter_value {router_008} {DESTINATION_ID} {0 };set_instance_parameter_value {router_008} {CHANNEL_ID} {1 };set_instance_parameter_value {router_008} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_008} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_008} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_008} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_008} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_008} {SPAN_OFFSET} {};set_instance_parameter_value {router_008} {PKT_ADDR_H} {54};set_instance_parameter_value {router_008} {PKT_ADDR_L} {36};set_instance_parameter_value {router_008} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_008} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_008} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_008} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_008} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_008} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_008} {ST_DATA_W} {97};set_instance_parameter_value {router_008} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_008} {DECODER_TYPE} {1};set_instance_parameter_value {router_008} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_008} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_008} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_008} {MEMORY_ALIASING_DECODE} {0};add_instance {router_009} {altera_merlin_router};set_instance_parameter_value {router_009} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_009} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_009} {TYPE_OF_TRANSACTION} {both read };set_instance_parameter_value {router_009} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_009} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_009} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_009} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_009} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_009} {SPAN_OFFSET} {};set_instance_parameter_value {router_009} {PKT_ADDR_H} {54};set_instance_parameter_value {router_009} {PKT_ADDR_L} {36};set_instance_parameter_value {router_009} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_009} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_009} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_009} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_009} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_009} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_009} {ST_DATA_W} {97};set_instance_parameter_value {router_009} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_009} {DECODER_TYPE} {1};set_instance_parameter_value {router_009} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_009} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_009} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_009} {MEMORY_ALIASING_DECODE} {0};add_instance {router_010} {altera_merlin_router};set_instance_parameter_value {router_010} {DESTINATION_ID} {0 };set_instance_parameter_value {router_010} {CHANNEL_ID} {1 };set_instance_parameter_value {router_010} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_010} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_010} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_010} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_010} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_010} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_010} {SPAN_OFFSET} {};set_instance_parameter_value {router_010} {PKT_ADDR_H} {54};set_instance_parameter_value {router_010} {PKT_ADDR_L} {36};set_instance_parameter_value {router_010} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_010} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_010} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_010} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_010} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_010} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_010} {ST_DATA_W} {97};set_instance_parameter_value {router_010} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_010} {DECODER_TYPE} {1};set_instance_parameter_value {router_010} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_010} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_010} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_010} {MEMORY_ALIASING_DECODE} {0};add_instance {router_011} {altera_merlin_router};set_instance_parameter_value {router_011} {DESTINATION_ID} {0 };set_instance_parameter_value {router_011} {CHANNEL_ID} {1 };set_instance_parameter_value {router_011} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_011} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_011} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_011} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_011} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_011} {SPAN_OFFSET} {};set_instance_parameter_value {router_011} {PKT_ADDR_H} {54};set_instance_parameter_value {router_011} {PKT_ADDR_L} {36};set_instance_parameter_value {router_011} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_011} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_011} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_011} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_011} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_011} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_011} {ST_DATA_W} {97};set_instance_parameter_value {router_011} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_011} {DECODER_TYPE} {1};set_instance_parameter_value {router_011} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_011} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_011} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_011} {MEMORY_ALIASING_DECODE} {0};add_instance {router_012} {altera_merlin_router};set_instance_parameter_value {router_012} {DESTINATION_ID} {0 };set_instance_parameter_value {router_012} {CHANNEL_ID} {1 };set_instance_parameter_value {router_012} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_012} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_012} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_012} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_012} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_012} {SPAN_OFFSET} {};set_instance_parameter_value {router_012} {PKT_ADDR_H} {54};set_instance_parameter_value {router_012} {PKT_ADDR_L} {36};set_instance_parameter_value {router_012} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_012} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_012} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_012} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_012} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_012} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_012} {ST_DATA_W} {97};set_instance_parameter_value {router_012} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_012} {DECODER_TYPE} {1};set_instance_parameter_value {router_012} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_012} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_012} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_012} {MEMORY_ALIASING_DECODE} {0};add_instance {router_013} {altera_merlin_router};set_instance_parameter_value {router_013} {DESTINATION_ID} {0 };set_instance_parameter_value {router_013} {CHANNEL_ID} {1 };set_instance_parameter_value {router_013} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_013} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_013} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_013} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_013} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_013} {SPAN_OFFSET} {};set_instance_parameter_value {router_013} {PKT_ADDR_H} {54};set_instance_parameter_value {router_013} {PKT_ADDR_L} {36};set_instance_parameter_value {router_013} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_013} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_013} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_013} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_013} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_013} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_013} {ST_DATA_W} {97};set_instance_parameter_value {router_013} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_013} {DECODER_TYPE} {1};set_instance_parameter_value {router_013} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_013} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_013} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_013} {MEMORY_ALIASING_DECODE} {0};add_instance {router_014} {altera_merlin_router};set_instance_parameter_value {router_014} {DESTINATION_ID} {0 };set_instance_parameter_value {router_014} {CHANNEL_ID} {1 };set_instance_parameter_value {router_014} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_014} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_014} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_014} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_014} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_014} {SPAN_OFFSET} {};set_instance_parameter_value {router_014} {PKT_ADDR_H} {54};set_instance_parameter_value {router_014} {PKT_ADDR_L} {36};set_instance_parameter_value {router_014} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_014} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_014} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_014} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_014} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_014} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_014} {ST_DATA_W} {97};set_instance_parameter_value {router_014} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_014} {DECODER_TYPE} {1};set_instance_parameter_value {router_014} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_014} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_014} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_014} {MEMORY_ALIASING_DECODE} {0};add_instance {router_015} {altera_merlin_router};set_instance_parameter_value {router_015} {DESTINATION_ID} {0 };set_instance_parameter_value {router_015} {CHANNEL_ID} {1 };set_instance_parameter_value {router_015} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_015} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_015} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_015} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_015} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_015} {SPAN_OFFSET} {};set_instance_parameter_value {router_015} {PKT_ADDR_H} {54};set_instance_parameter_value {router_015} {PKT_ADDR_L} {36};set_instance_parameter_value {router_015} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_015} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_015} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_015} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_015} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_015} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_015} {ST_DATA_W} {97};set_instance_parameter_value {router_015} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_015} {DECODER_TYPE} {1};set_instance_parameter_value {router_015} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_015} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_015} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_015} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_015} {MEMORY_ALIASING_DECODE} {0};add_instance {router_016} {altera_merlin_router};set_instance_parameter_value {router_016} {DESTINATION_ID} {0 };set_instance_parameter_value {router_016} {CHANNEL_ID} {1 };set_instance_parameter_value {router_016} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_016} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {END_ADDRESS} {0x0 };set_instance_parameter_value {router_016} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_016} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_016} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_016} {SPAN_OFFSET} {};set_instance_parameter_value {router_016} {PKT_ADDR_H} {54};set_instance_parameter_value {router_016} {PKT_ADDR_L} {36};set_instance_parameter_value {router_016} {PKT_PROTECTION_H} {87};set_instance_parameter_value {router_016} {PKT_PROTECTION_L} {85};set_instance_parameter_value {router_016} {PKT_DEST_ID_H} {83};set_instance_parameter_value {router_016} {PKT_DEST_ID_L} {80};set_instance_parameter_value {router_016} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {router_016} {PKT_TRANS_READ} {58};set_instance_parameter_value {router_016} {ST_DATA_W} {97};set_instance_parameter_value {router_016} {ST_CHANNEL_W} {15};set_instance_parameter_value {router_016} {DECODER_TYPE} {1};set_instance_parameter_value {router_016} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_016} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_016} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_016} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_016} {MEMORY_ALIASING_DECODE} {0};add_instance {nios2_gen2_data_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_DEST_ID_H} {83};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_DEST_ID_L} {80};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_SRC_ID_H} {79};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_SRC_ID_L} {76};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_THREAD_ID_H} {84};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PKT_THREAD_ID_L} {84};set_instance_parameter_value {nios2_gen2_data_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {nios2_gen2_data_master_limiter} {MAX_OUTSTANDING_RESPONSES} {5};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PIPELINED} {0};set_instance_parameter_value {nios2_gen2_data_master_limiter} {ST_DATA_W} {97};set_instance_parameter_value {nios2_gen2_data_master_limiter} {ST_CHANNEL_W} {15};set_instance_parameter_value {nios2_gen2_data_master_limiter} {VALID_WIDTH} {15};set_instance_parameter_value {nios2_gen2_data_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {nios2_gen2_data_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {nios2_gen2_data_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {nios2_gen2_data_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {nios2_gen2_data_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {nios2_gen2_data_master_limiter} {REORDER} {0};add_instance {nios2_gen2_instruction_master_limiter} {altera_merlin_traffic_limiter};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_DEST_ID_H} {83};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_DEST_ID_L} {80};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_SRC_ID_H} {79};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_SRC_ID_L} {76};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_BYTE_CNT_H} {63};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_BYTE_CNT_L} {61};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_TRANS_POSTED} {56};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_TRANS_WRITE} {57};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_THREAD_ID_H} {84};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PKT_THREAD_ID_L} {84};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {MAX_BURST_LENGTH} {1};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {MAX_OUTSTANDING_RESPONSES} {1};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PIPELINED} {0};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {ST_DATA_W} {97};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {ST_CHANNEL_W} {15};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {VALID_WIDTH} {15};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {ENFORCE_ORDER} {1};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {PREVENT_HAZARDS} {0};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {SUPPORTS_POSTED_WRITES} {1};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {SUPPORTS_NONPOSTED_WRITES} {0};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};set_instance_parameter_value {nios2_gen2_instruction_master_limiter} {REORDER} {0};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {97};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {15};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {15};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {97};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {2};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {15};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_001} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_001} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_001} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_001} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_002} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_002} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_002} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_002} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_002} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_002} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_002} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_002} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_003} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_003} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_003} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_003} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_003} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_003} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_003} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_003} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_004} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_004} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_004} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_004} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_004} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_004} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_004} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_004} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_005} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_005} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_005} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_005} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_005} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_005} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_005} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_005} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_006} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_006} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_006} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_006} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_006} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_006} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_006} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_006} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_007} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_007} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_007} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_007} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux_007} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_007} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_007} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_007} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_008} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_008} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_008} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_008} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_008} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_008} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_008} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_008} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_009} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_009} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_009} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_009} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_009} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_009} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_009} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_009} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_010} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_010} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_010} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_010} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_010} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_010} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_010} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_010} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_011} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_011} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_011} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_011} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_011} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_011} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_011} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_011} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_012} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_012} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_012} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_012} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_012} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_012} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_012} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_012} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_013} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_013} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_013} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_013} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_013} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_013} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_013} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_013} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {cmd_mux_014} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux_014} {ST_DATA_W} {97};set_instance_parameter_value {cmd_mux_014} {ST_CHANNEL_W} {15};set_instance_parameter_value {cmd_mux_014} {NUM_INPUTS} {1};set_instance_parameter_value {cmd_mux_014} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux_014} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux_014} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux_014} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {cmd_mux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_001} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_001} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_002} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_002} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_002} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_002} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_002} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_003} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_003} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_003} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_003} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_003} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_003} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_004} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_004} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_004} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_004} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_004} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_004} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_005} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_005} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_005} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_005} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_005} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_005} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_006} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_006} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_006} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_006} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_006} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_006} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_007} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_007} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_007} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_007} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux_007} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_007} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_008} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_008} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_008} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_008} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_008} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_008} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_009} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_009} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_009} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_009} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_009} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_009} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_010} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_010} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_010} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_010} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_010} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_010} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_011} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_011} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_011} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_011} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_011} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_011} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_012} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_012} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_012} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_012} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_012} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_012} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_013} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_013} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_013} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_013} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_013} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_013} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_demux_014} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux_014} {ST_DATA_W} {97};set_instance_parameter_value {rsp_demux_014} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_demux_014} {NUM_OUTPUTS} {1};set_instance_parameter_value {rsp_demux_014} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux_014} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {97};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {15};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {97};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {15};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {2};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {59};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(96:94) response_status(93:92) cache(91:88) protection(87:85) thread_id(84) dest_id(83:80) src_id(79:76) qos(75) begin_burst(74) data_sideband(73) addr_sideband(72) burst_type(71:70) burst_size(69:67) burstwrap(66:64) byte_cnt(63:61) trans_exclusive(60) trans_lock(59) trans_read(58) trans_write(57) trans_posted(56) trans_compressed_read(55) addr(54:36) byteen(35:32) data(31:0)};add_instance {crosser} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser} {DATA_WIDTH} {97};set_instance_parameter_value {crosser} {BITS_PER_SYMBOL} {97};set_instance_parameter_value {crosser} {USE_PACKETS} {1};set_instance_parameter_value {crosser} {USE_CHANNEL} {1};set_instance_parameter_value {crosser} {CHANNEL_WIDTH} {15};set_instance_parameter_value {crosser} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser} {USE_ERROR} {0};set_instance_parameter_value {crosser} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_001} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_001} {DATA_WIDTH} {97};set_instance_parameter_value {crosser_001} {BITS_PER_SYMBOL} {97};set_instance_parameter_value {crosser_001} {USE_PACKETS} {1};set_instance_parameter_value {crosser_001} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_001} {CHANNEL_WIDTH} {15};set_instance_parameter_value {crosser_001} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_001} {USE_ERROR} {0};set_instance_parameter_value {crosser_001} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_001} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_001} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_002} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_002} {DATA_WIDTH} {97};set_instance_parameter_value {crosser_002} {BITS_PER_SYMBOL} {97};set_instance_parameter_value {crosser_002} {USE_PACKETS} {1};set_instance_parameter_value {crosser_002} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_002} {CHANNEL_WIDTH} {15};set_instance_parameter_value {crosser_002} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_002} {USE_ERROR} {0};set_instance_parameter_value {crosser_002} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_002} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_002} {USE_OUTPUT_PIPELINE} {0};add_instance {crosser_003} {altera_avalon_st_handshake_clock_crosser};set_instance_parameter_value {crosser_003} {DATA_WIDTH} {97};set_instance_parameter_value {crosser_003} {BITS_PER_SYMBOL} {97};set_instance_parameter_value {crosser_003} {USE_PACKETS} {1};set_instance_parameter_value {crosser_003} {USE_CHANNEL} {1};set_instance_parameter_value {crosser_003} {CHANNEL_WIDTH} {15};set_instance_parameter_value {crosser_003} {MAX_CHANNEL} {0};set_instance_parameter_value {crosser_003} {USE_ERROR} {0};set_instance_parameter_value {crosser_003} {ERROR_WIDTH} {1};set_instance_parameter_value {crosser_003} {VALID_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {READY_SYNC_DEPTH} {2};set_instance_parameter_value {crosser_003} {USE_OUTPUT_PIPELINE} {0};add_instance {nios2_gen2_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {nios2_gen2_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {nios2_gen2_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {nios2_gen2_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {nios2_gen2_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {TERASIC_AUTO_FOCUS_0_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {TERASIC_AUTO_FOCUS_0_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {altpll_0_inclk_interface_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {altpll_0_inclk_interface_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {altpll_0_inclk_interface_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {altpll_0_inclk_interface_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {altpll_0_inclk_interface_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {clk_50_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_50_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {50000000};set_instance_parameter_value {clk_50_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_instance {altpll_0_c2_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {altpll_0_c2_clock_bridge} {EXPLICIT_CLOCK_RATE} {100000000};set_instance_parameter_value {altpll_0_c2_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {nios2_gen2_data_master_translator.avalon_universal_master_0} {nios2_gen2_data_master_agent.av} {avalon};set_connection_parameter_value {nios2_gen2_data_master_translator.avalon_universal_master_0/nios2_gen2_data_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {nios2_gen2_data_master_translator.avalon_universal_master_0/nios2_gen2_data_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {nios2_gen2_data_master_translator.avalon_universal_master_0/nios2_gen2_data_master_agent.av} {defaultConnection} {false};add_connection {nios2_gen2_instruction_master_translator.avalon_universal_master_0} {nios2_gen2_instruction_master_agent.av} {avalon};set_connection_parameter_value {nios2_gen2_instruction_master_translator.avalon_universal_master_0/nios2_gen2_instruction_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {nios2_gen2_instruction_master_translator.avalon_universal_master_0/nios2_gen2_instruction_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {nios2_gen2_instruction_master_translator.avalon_universal_master_0/nios2_gen2_instruction_master_agent.av} {defaultConnection} {false};add_connection {jtag_uart_avalon_jtag_slave_agent.m0} {jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {jtag_uart_avalon_jtag_slave_agent.m0/jtag_uart_avalon_jtag_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {jtag_uart_avalon_jtag_slave_agent.rf_source} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.out} {jtag_uart_avalon_jtag_slave_agent.rf_sink} {avalon_streaming};add_connection {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_src} {jtag_uart_avalon_jtag_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux.src} {jtag_uart_avalon_jtag_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/jtag_uart_avalon_jtag_slave_agent.cp} {qsys_mm.command};add_connection {i2c_opencores_mipi_avalon_slave_0_agent.m0} {i2c_opencores_mipi_avalon_slave_0_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent.m0/i2c_opencores_mipi_avalon_slave_0_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent.m0/i2c_opencores_mipi_avalon_slave_0_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {i2c_opencores_mipi_avalon_slave_0_agent.m0/i2c_opencores_mipi_avalon_slave_0_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {i2c_opencores_mipi_avalon_slave_0_agent.rf_source} {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo.in} {avalon_streaming};add_connection {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo.out} {i2c_opencores_mipi_avalon_slave_0_agent.rf_sink} {avalon_streaming};add_connection {i2c_opencores_mipi_avalon_slave_0_agent.rdata_fifo_src} {i2c_opencores_mipi_avalon_slave_0_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_001.src} {i2c_opencores_mipi_avalon_slave_0_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_001.src/i2c_opencores_mipi_avalon_slave_0_agent.cp} {qsys_mm.command};add_connection {i2c_opencores_camera_avalon_slave_0_agent.m0} {i2c_opencores_camera_avalon_slave_0_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {i2c_opencores_camera_avalon_slave_0_agent.m0/i2c_opencores_camera_avalon_slave_0_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {i2c_opencores_camera_avalon_slave_0_agent.m0/i2c_opencores_camera_avalon_slave_0_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {i2c_opencores_camera_avalon_slave_0_agent.m0/i2c_opencores_camera_avalon_slave_0_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {i2c_opencores_camera_avalon_slave_0_agent.rf_source} {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo.in} {avalon_streaming};add_connection {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo.out} {i2c_opencores_camera_avalon_slave_0_agent.rf_sink} {avalon_streaming};add_connection {i2c_opencores_camera_avalon_slave_0_agent.rdata_fifo_src} {i2c_opencores_camera_avalon_slave_0_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_002.src} {i2c_opencores_camera_avalon_slave_0_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_002.src/i2c_opencores_camera_avalon_slave_0_agent.cp} {qsys_mm.command};add_connection {sysid_qsys_control_slave_agent.m0} {sysid_qsys_control_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sysid_qsys_control_slave_agent.m0/sysid_qsys_control_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sysid_qsys_control_slave_agent.m0/sysid_qsys_control_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sysid_qsys_control_slave_agent.m0/sysid_qsys_control_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sysid_qsys_control_slave_agent.rf_source} {sysid_qsys_control_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {sysid_qsys_control_slave_agent_rsp_fifo.out} {sysid_qsys_control_slave_agent.rf_sink} {avalon_streaming};add_connection {sysid_qsys_control_slave_agent.rdata_fifo_src} {sysid_qsys_control_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_003.src} {sysid_qsys_control_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_003.src/sysid_qsys_control_slave_agent.cp} {qsys_mm.command};add_connection {nios2_gen2_debug_mem_slave_agent.m0} {nios2_gen2_debug_mem_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {nios2_gen2_debug_mem_slave_agent.m0/nios2_gen2_debug_mem_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {nios2_gen2_debug_mem_slave_agent.m0/nios2_gen2_debug_mem_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {nios2_gen2_debug_mem_slave_agent.m0/nios2_gen2_debug_mem_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {nios2_gen2_debug_mem_slave_agent.rf_source} {nios2_gen2_debug_mem_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {nios2_gen2_debug_mem_slave_agent_rsp_fifo.out} {nios2_gen2_debug_mem_slave_agent.rf_sink} {avalon_streaming};add_connection {nios2_gen2_debug_mem_slave_agent.rdata_fifo_src} {nios2_gen2_debug_mem_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_004.src} {nios2_gen2_debug_mem_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_004.src/nios2_gen2_debug_mem_slave_agent.cp} {qsys_mm.command};add_connection {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.m0} {TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.m0/TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.m0/TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.m0/TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.rf_source} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo.in} {avalon_streaming};add_connection {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo.out} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.rf_sink} {avalon_streaming};add_connection {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.rdata_fifo_src} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo.in} {avalon_streaming};add_connection {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo.out} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_005.src} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_005.src/TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.cp} {qsys_mm.command};add_connection {altpll_0_pll_slave_agent.m0} {altpll_0_pll_slave_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {altpll_0_pll_slave_agent.m0/altpll_0_pll_slave_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {altpll_0_pll_slave_agent.m0/altpll_0_pll_slave_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {altpll_0_pll_slave_agent.m0/altpll_0_pll_slave_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {altpll_0_pll_slave_agent.rf_source} {altpll_0_pll_slave_agent_rsp_fifo.in} {avalon_streaming};add_connection {altpll_0_pll_slave_agent_rsp_fifo.out} {altpll_0_pll_slave_agent.rf_sink} {avalon_streaming};add_connection {altpll_0_pll_slave_agent.rdata_fifo_src} {altpll_0_pll_slave_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_006.src} {altpll_0_pll_slave_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_006.src/altpll_0_pll_slave_agent.cp} {qsys_mm.command};add_connection {onchip_memory2_0_s1_agent.m0} {onchip_memory2_0_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {onchip_memory2_0_s1_agent.m0/onchip_memory2_0_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {onchip_memory2_0_s1_agent.rf_source} {onchip_memory2_0_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {onchip_memory2_0_s1_agent_rsp_fifo.out} {onchip_memory2_0_s1_agent.rf_sink} {avalon_streaming};add_connection {onchip_memory2_0_s1_agent.rdata_fifo_src} {onchip_memory2_0_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_007.src} {onchip_memory2_0_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_007.src/onchip_memory2_0_s1_agent.cp} {qsys_mm.command};add_connection {timer_s1_agent.m0} {timer_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {timer_s1_agent.m0/timer_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {timer_s1_agent.m0/timer_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {timer_s1_agent.m0/timer_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {timer_s1_agent.rf_source} {timer_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {timer_s1_agent_rsp_fifo.out} {timer_s1_agent.rf_sink} {avalon_streaming};add_connection {timer_s1_agent.rdata_fifo_src} {timer_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_008.src} {timer_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_008.src/timer_s1_agent.cp} {qsys_mm.command};add_connection {led_s1_agent.m0} {led_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {led_s1_agent.m0/led_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {led_s1_agent.m0/led_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {led_s1_agent.m0/led_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {led_s1_agent.rf_source} {led_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {led_s1_agent_rsp_fifo.out} {led_s1_agent.rf_sink} {avalon_streaming};add_connection {led_s1_agent.rdata_fifo_src} {led_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_009.src} {led_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_009.src/led_s1_agent.cp} {qsys_mm.command};add_connection {sw_s1_agent.m0} {sw_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sw_s1_agent.m0/sw_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sw_s1_agent.m0/sw_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sw_s1_agent.m0/sw_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sw_s1_agent.rf_source} {sw_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sw_s1_agent_rsp_fifo.out} {sw_s1_agent.rf_sink} {avalon_streaming};add_connection {sw_s1_agent.rdata_fifo_src} {sw_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_010.src} {sw_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_010.src/sw_s1_agent.cp} {qsys_mm.command};add_connection {key_s1_agent.m0} {key_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {key_s1_agent.m0/key_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {key_s1_agent.m0/key_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {key_s1_agent.m0/key_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {key_s1_agent.rf_source} {key_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {key_s1_agent_rsp_fifo.out} {key_s1_agent.rf_sink} {avalon_streaming};add_connection {key_s1_agent.rdata_fifo_src} {key_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_011.src} {key_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_011.src/key_s1_agent.cp} {qsys_mm.command};add_connection {mipi_reset_n_s1_agent.m0} {mipi_reset_n_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mipi_reset_n_s1_agent.m0/mipi_reset_n_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mipi_reset_n_s1_agent.m0/mipi_reset_n_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mipi_reset_n_s1_agent.m0/mipi_reset_n_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mipi_reset_n_s1_agent.rf_source} {mipi_reset_n_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {mipi_reset_n_s1_agent_rsp_fifo.out} {mipi_reset_n_s1_agent.rf_sink} {avalon_streaming};add_connection {mipi_reset_n_s1_agent.rdata_fifo_src} {mipi_reset_n_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_012.src} {mipi_reset_n_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_012.src/mipi_reset_n_s1_agent.cp} {qsys_mm.command};add_connection {mipi_pwdn_n_s1_agent.m0} {mipi_pwdn_n_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {mipi_pwdn_n_s1_agent.m0/mipi_pwdn_n_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {mipi_pwdn_n_s1_agent.m0/mipi_pwdn_n_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {mipi_pwdn_n_s1_agent.m0/mipi_pwdn_n_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {mipi_pwdn_n_s1_agent.rf_source} {mipi_pwdn_n_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {mipi_pwdn_n_s1_agent_rsp_fifo.out} {mipi_pwdn_n_s1_agent.rf_sink} {avalon_streaming};add_connection {mipi_pwdn_n_s1_agent.rdata_fifo_src} {mipi_pwdn_n_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_013.src} {mipi_pwdn_n_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_013.src/mipi_pwdn_n_s1_agent.cp} {qsys_mm.command};add_connection {EEE_IMGPROC_0_s1_agent.m0} {EEE_IMGPROC_0_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {EEE_IMGPROC_0_s1_agent.m0/EEE_IMGPROC_0_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {EEE_IMGPROC_0_s1_agent.m0/EEE_IMGPROC_0_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {EEE_IMGPROC_0_s1_agent.m0/EEE_IMGPROC_0_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {EEE_IMGPROC_0_s1_agent.rf_source} {EEE_IMGPROC_0_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {EEE_IMGPROC_0_s1_agent_rsp_fifo.out} {EEE_IMGPROC_0_s1_agent.rf_sink} {avalon_streaming};add_connection {EEE_IMGPROC_0_s1_agent.rdata_fifo_src} {EEE_IMGPROC_0_s1_agent_rdata_fifo.in} {avalon_streaming};add_connection {EEE_IMGPROC_0_s1_agent_rdata_fifo.out} {EEE_IMGPROC_0_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {cmd_mux_014.src} {EEE_IMGPROC_0_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {cmd_mux_014.src/EEE_IMGPROC_0_s1_agent.cp} {qsys_mm.command};add_connection {nios2_gen2_data_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {nios2_gen2_data_master_agent.cp/router.sink} {qsys_mm.command};add_connection {nios2_gen2_instruction_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {nios2_gen2_instruction_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {jtag_uart_avalon_jtag_slave_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {jtag_uart_avalon_jtag_slave_agent.rp/router_002.sink} {qsys_mm.response};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {i2c_opencores_mipi_avalon_slave_0_agent.rp} {router_003.sink} {avalon_streaming};preview_set_connection_tag {i2c_opencores_mipi_avalon_slave_0_agent.rp/router_003.sink} {qsys_mm.response};add_connection {router_003.src} {rsp_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_003.src/rsp_demux_001.sink} {qsys_mm.response};add_connection {i2c_opencores_camera_avalon_slave_0_agent.rp} {router_004.sink} {avalon_streaming};preview_set_connection_tag {i2c_opencores_camera_avalon_slave_0_agent.rp/router_004.sink} {qsys_mm.response};add_connection {router_004.src} {rsp_demux_002.sink} {avalon_streaming};preview_set_connection_tag {router_004.src/rsp_demux_002.sink} {qsys_mm.response};add_connection {sysid_qsys_control_slave_agent.rp} {router_005.sink} {avalon_streaming};preview_set_connection_tag {sysid_qsys_control_slave_agent.rp/router_005.sink} {qsys_mm.response};add_connection {router_005.src} {rsp_demux_003.sink} {avalon_streaming};preview_set_connection_tag {router_005.src/rsp_demux_003.sink} {qsys_mm.response};add_connection {nios2_gen2_debug_mem_slave_agent.rp} {router_006.sink} {avalon_streaming};preview_set_connection_tag {nios2_gen2_debug_mem_slave_agent.rp/router_006.sink} {qsys_mm.response};add_connection {router_006.src} {rsp_demux_004.sink} {avalon_streaming};preview_set_connection_tag {router_006.src/rsp_demux_004.sink} {qsys_mm.response};add_connection {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.rp} {router_007.sink} {avalon_streaming};preview_set_connection_tag {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.rp/router_007.sink} {qsys_mm.response};add_connection {router_007.src} {rsp_demux_005.sink} {avalon_streaming};preview_set_connection_tag {router_007.src/rsp_demux_005.sink} {qsys_mm.response};add_connection {altpll_0_pll_slave_agent.rp} {router_008.sink} {avalon_streaming};preview_set_connection_tag {altpll_0_pll_slave_agent.rp/router_008.sink} {qsys_mm.response};add_connection {router_008.src} {rsp_demux_006.sink} {avalon_streaming};preview_set_connection_tag {router_008.src/rsp_demux_006.sink} {qsys_mm.response};add_connection {onchip_memory2_0_s1_agent.rp} {router_009.sink} {avalon_streaming};preview_set_connection_tag {onchip_memory2_0_s1_agent.rp/router_009.sink} {qsys_mm.response};add_connection {router_009.src} {rsp_demux_007.sink} {avalon_streaming};preview_set_connection_tag {router_009.src/rsp_demux_007.sink} {qsys_mm.response};add_connection {timer_s1_agent.rp} {router_010.sink} {avalon_streaming};preview_set_connection_tag {timer_s1_agent.rp/router_010.sink} {qsys_mm.response};add_connection {router_010.src} {rsp_demux_008.sink} {avalon_streaming};preview_set_connection_tag {router_010.src/rsp_demux_008.sink} {qsys_mm.response};add_connection {led_s1_agent.rp} {router_011.sink} {avalon_streaming};preview_set_connection_tag {led_s1_agent.rp/router_011.sink} {qsys_mm.response};add_connection {router_011.src} {rsp_demux_009.sink} {avalon_streaming};preview_set_connection_tag {router_011.src/rsp_demux_009.sink} {qsys_mm.response};add_connection {sw_s1_agent.rp} {router_012.sink} {avalon_streaming};preview_set_connection_tag {sw_s1_agent.rp/router_012.sink} {qsys_mm.response};add_connection {router_012.src} {rsp_demux_010.sink} {avalon_streaming};preview_set_connection_tag {router_012.src/rsp_demux_010.sink} {qsys_mm.response};add_connection {key_s1_agent.rp} {router_013.sink} {avalon_streaming};preview_set_connection_tag {key_s1_agent.rp/router_013.sink} {qsys_mm.response};add_connection {router_013.src} {rsp_demux_011.sink} {avalon_streaming};preview_set_connection_tag {router_013.src/rsp_demux_011.sink} {qsys_mm.response};add_connection {mipi_reset_n_s1_agent.rp} {router_014.sink} {avalon_streaming};preview_set_connection_tag {mipi_reset_n_s1_agent.rp/router_014.sink} {qsys_mm.response};add_connection {router_014.src} {rsp_demux_012.sink} {avalon_streaming};preview_set_connection_tag {router_014.src/rsp_demux_012.sink} {qsys_mm.response};add_connection {mipi_pwdn_n_s1_agent.rp} {router_015.sink} {avalon_streaming};preview_set_connection_tag {mipi_pwdn_n_s1_agent.rp/router_015.sink} {qsys_mm.response};add_connection {router_015.src} {rsp_demux_013.sink} {avalon_streaming};preview_set_connection_tag {router_015.src/rsp_demux_013.sink} {qsys_mm.response};add_connection {EEE_IMGPROC_0_s1_agent.rp} {router_016.sink} {avalon_streaming};preview_set_connection_tag {EEE_IMGPROC_0_s1_agent.rp/router_016.sink} {qsys_mm.response};add_connection {router_016.src} {rsp_demux_014.sink} {avalon_streaming};preview_set_connection_tag {router_016.src/rsp_demux_014.sink} {qsys_mm.response};add_connection {router.src} {nios2_gen2_data_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router.src/nios2_gen2_data_master_limiter.cmd_sink} {qsys_mm.command};add_connection {nios2_gen2_data_master_limiter.cmd_src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {nios2_gen2_data_master_limiter.cmd_src/cmd_demux.sink} {qsys_mm.command};add_connection {rsp_mux.src} {nios2_gen2_data_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/nios2_gen2_data_master_limiter.rsp_sink} {qsys_mm.response};add_connection {nios2_gen2_data_master_limiter.rsp_src} {nios2_gen2_data_master_agent.rp} {avalon_streaming};preview_set_connection_tag {nios2_gen2_data_master_limiter.rsp_src/nios2_gen2_data_master_agent.rp} {qsys_mm.response};add_connection {router_001.src} {nios2_gen2_instruction_master_limiter.cmd_sink} {avalon_streaming};preview_set_connection_tag {router_001.src/nios2_gen2_instruction_master_limiter.cmd_sink} {qsys_mm.command};add_connection {nios2_gen2_instruction_master_limiter.cmd_src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {nios2_gen2_instruction_master_limiter.cmd_src/cmd_demux_001.sink} {qsys_mm.command};add_connection {rsp_mux_001.src} {nios2_gen2_instruction_master_limiter.rsp_sink} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/nios2_gen2_instruction_master_limiter.rsp_sink} {qsys_mm.response};add_connection {nios2_gen2_instruction_master_limiter.rsp_src} {nios2_gen2_instruction_master_agent.rp} {avalon_streaming};preview_set_connection_tag {nios2_gen2_instruction_master_limiter.rsp_src/nios2_gen2_instruction_master_agent.rp} {qsys_mm.response};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux.src1} {cmd_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src1/cmd_mux_001.sink0} {qsys_mm.command};add_connection {cmd_demux.src2} {cmd_mux_002.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src2/cmd_mux_002.sink0} {qsys_mm.command};add_connection {cmd_demux.src3} {cmd_mux_003.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src3/cmd_mux_003.sink0} {qsys_mm.command};add_connection {cmd_demux.src4} {cmd_mux_004.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src4/cmd_mux_004.sink0} {qsys_mm.command};add_connection {cmd_demux.src6} {cmd_mux_006.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src6/cmd_mux_006.sink0} {qsys_mm.command};add_connection {cmd_demux.src7} {cmd_mux_007.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src7/cmd_mux_007.sink0} {qsys_mm.command};add_connection {cmd_demux.src8} {cmd_mux_008.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src8/cmd_mux_008.sink0} {qsys_mm.command};add_connection {cmd_demux.src9} {cmd_mux_009.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src9/cmd_mux_009.sink0} {qsys_mm.command};add_connection {cmd_demux.src10} {cmd_mux_010.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src10/cmd_mux_010.sink0} {qsys_mm.command};add_connection {cmd_demux.src11} {cmd_mux_011.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src11/cmd_mux_011.sink0} {qsys_mm.command};add_connection {cmd_demux.src12} {cmd_mux_012.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src12/cmd_mux_012.sink0} {qsys_mm.command};add_connection {cmd_demux.src13} {cmd_mux_013.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src13/cmd_mux_013.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux_004.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux_004.sink1} {qsys_mm.command};add_connection {cmd_demux_001.src1} {cmd_mux_007.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src1/cmd_mux_007.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux_001.src0} {rsp_mux.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_001.src0/rsp_mux.sink1} {qsys_mm.response};add_connection {rsp_demux_002.src0} {rsp_mux.sink2} {avalon_streaming};preview_set_connection_tag {rsp_demux_002.src0/rsp_mux.sink2} {qsys_mm.response};add_connection {rsp_demux_003.src0} {rsp_mux.sink3} {avalon_streaming};preview_set_connection_tag {rsp_demux_003.src0/rsp_mux.sink3} {qsys_mm.response};add_connection {rsp_demux_004.src0} {rsp_mux.sink4} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src0/rsp_mux.sink4} {qsys_mm.response};add_connection {rsp_demux_004.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux_004.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {rsp_demux_006.src0} {rsp_mux.sink6} {avalon_streaming};preview_set_connection_tag {rsp_demux_006.src0/rsp_mux.sink6} {qsys_mm.response};add_connection {rsp_demux_007.src0} {rsp_mux.sink7} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src0/rsp_mux.sink7} {qsys_mm.response};add_connection {rsp_demux_007.src1} {rsp_mux_001.sink1} {avalon_streaming};preview_set_connection_tag {rsp_demux_007.src1/rsp_mux_001.sink1} {qsys_mm.response};add_connection {rsp_demux_008.src0} {rsp_mux.sink8} {avalon_streaming};preview_set_connection_tag {rsp_demux_008.src0/rsp_mux.sink8} {qsys_mm.response};add_connection {rsp_demux_009.src0} {rsp_mux.sink9} {avalon_streaming};preview_set_connection_tag {rsp_demux_009.src0/rsp_mux.sink9} {qsys_mm.response};add_connection {rsp_demux_010.src0} {rsp_mux.sink10} {avalon_streaming};preview_set_connection_tag {rsp_demux_010.src0/rsp_mux.sink10} {qsys_mm.response};add_connection {rsp_demux_011.src0} {rsp_mux.sink11} {avalon_streaming};preview_set_connection_tag {rsp_demux_011.src0/rsp_mux.sink11} {qsys_mm.response};add_connection {rsp_demux_012.src0} {rsp_mux.sink12} {avalon_streaming};preview_set_connection_tag {rsp_demux_012.src0/rsp_mux.sink12} {qsys_mm.response};add_connection {rsp_demux_013.src0} {rsp_mux.sink13} {avalon_streaming};preview_set_connection_tag {rsp_demux_013.src0/rsp_mux.sink13} {qsys_mm.response};add_connection {cmd_demux.src5} {crosser.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src5/crosser.in} {qsys_mm.command};add_connection {crosser.out} {cmd_mux_005.sink0} {avalon_streaming};preview_set_connection_tag {crosser.out/cmd_mux_005.sink0} {qsys_mm.command};add_connection {cmd_demux.src14} {crosser_001.in} {avalon_streaming};preview_set_connection_tag {cmd_demux.src14/crosser_001.in} {qsys_mm.command};add_connection {crosser_001.out} {cmd_mux_014.sink0} {avalon_streaming};preview_set_connection_tag {crosser_001.out/cmd_mux_014.sink0} {qsys_mm.command};add_connection {rsp_demux_005.src0} {crosser_002.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_005.src0/crosser_002.in} {qsys_mm.response};add_connection {crosser_002.out} {rsp_mux.sink5} {avalon_streaming};preview_set_connection_tag {crosser_002.out/rsp_mux.sink5} {qsys_mm.response};add_connection {rsp_demux_014.src0} {crosser_003.in} {avalon_streaming};preview_set_connection_tag {rsp_demux_014.src0/crosser_003.in} {qsys_mm.response};add_connection {crosser_003.out} {rsp_mux.sink14} {avalon_streaming};preview_set_connection_tag {crosser_003.out/rsp_mux.sink14} {qsys_mm.response};add_connection {nios2_gen2_data_master_limiter.cmd_valid} {cmd_demux.sink_valid} {avalon_streaming};add_connection {nios2_gen2_instruction_master_limiter.cmd_valid} {cmd_demux_001.sink_valid} {avalon_streaming};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_data_master_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_instruction_master_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {i2c_opencores_mipi_avalon_slave_0_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {i2c_opencores_camera_avalon_slave_0_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {sysid_qsys_control_slave_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_debug_mem_slave_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {onchip_memory2_0_s1_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {timer_s1_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {led_s1_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {sw_s1_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {key_s1_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {mipi_reset_n_s1_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {mipi_pwdn_n_s1_translator.reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_data_master_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_instruction_master_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {i2c_opencores_mipi_avalon_slave_0_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {i2c_opencores_camera_avalon_slave_0_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {sysid_qsys_control_slave_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {sysid_qsys_control_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_debug_mem_slave_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_debug_mem_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {onchip_memory2_0_s1_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {onchip_memory2_0_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {timer_s1_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {timer_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {led_s1_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {led_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {sw_s1_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {sw_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {key_s1_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {key_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {mipi_reset_n_s1_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {mipi_reset_n_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {mipi_pwdn_n_s1_agent.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {mipi_pwdn_n_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_003.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_004.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_005.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_006.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_009.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_010.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_011.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_012.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_013.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_014.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {router_015.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_data_master_limiter.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {nios2_gen2_instruction_master_limiter.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_001.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_002.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_003.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_004.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_007.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_008.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_009.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_010.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_011.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_012.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {cmd_mux_013.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_001.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_002.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_003.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_004.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_007.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_008.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_009.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_010.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_011.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_012.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_demux_013.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {crosser.in_clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {crosser_001.in_clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {crosser_002.out_clk_reset} {reset};add_connection {nios2_gen2_reset_reset_bridge.out_reset} {crosser_003.out_clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {EEE_IMGPROC_0_s1_translator.reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {EEE_IMGPROC_0_s1_agent.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {EEE_IMGPROC_0_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {EEE_IMGPROC_0_s1_agent_rdata_fifo.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {router_007.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {router_016.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {cmd_mux_005.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {cmd_mux_014.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {rsp_demux_005.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {rsp_demux_014.clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {crosser.out_clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {crosser_001.out_clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {crosser_002.in_clk_reset} {reset};add_connection {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.out_reset} {crosser_003.in_clk_reset} {reset};add_connection {altpll_0_inclk_interface_reset_reset_bridge.out_reset} {altpll_0_pll_slave_translator.reset} {reset};add_connection {altpll_0_inclk_interface_reset_reset_bridge.out_reset} {altpll_0_pll_slave_agent.clk_reset} {reset};add_connection {altpll_0_inclk_interface_reset_reset_bridge.out_reset} {altpll_0_pll_slave_agent_rsp_fifo.clk_reset} {reset};add_connection {altpll_0_inclk_interface_reset_reset_bridge.out_reset} {router_008.clk_reset} {reset};add_connection {altpll_0_inclk_interface_reset_reset_bridge.out_reset} {cmd_mux_006.clk_reset} {reset};add_connection {altpll_0_inclk_interface_reset_reset_bridge.out_reset} {rsp_demux_006.clk_reset} {reset};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_data_master_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_instruction_master_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {i2c_opencores_mipi_avalon_slave_0_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {i2c_opencores_camera_avalon_slave_0_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {sysid_qsys_control_slave_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_debug_mem_slave_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {altpll_0_pll_slave_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {onchip_memory2_0_s1_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {timer_s1_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {led_s1_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {sw_s1_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {key_s1_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {mipi_reset_n_s1_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {mipi_pwdn_n_s1_translator.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_data_master_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_instruction_master_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {jtag_uart_avalon_jtag_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {i2c_opencores_mipi_avalon_slave_0_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {i2c_opencores_mipi_avalon_slave_0_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {i2c_opencores_camera_avalon_slave_0_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {i2c_opencores_camera_avalon_slave_0_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {sysid_qsys_control_slave_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {sysid_qsys_control_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_debug_mem_slave_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_debug_mem_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {altpll_0_pll_slave_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {altpll_0_pll_slave_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {onchip_memory2_0_s1_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {onchip_memory2_0_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {timer_s1_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {timer_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {led_s1_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {led_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {sw_s1_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {sw_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {key_s1_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {key_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {mipi_reset_n_s1_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {mipi_reset_n_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {mipi_pwdn_n_s1_agent.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {mipi_pwdn_n_s1_agent_rsp_fifo.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_003.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_004.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_005.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_006.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_008.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_009.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_010.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_011.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_012.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_013.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_014.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {router_015.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_data_master_limiter.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_instruction_master_limiter.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_001.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_001.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_002.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_002.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_003.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_003.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_004.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_004.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_006.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_006.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_007.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_007.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_008.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_008.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_009.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_009.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_010.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_010.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_011.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_011.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_012.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_012.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {cmd_mux_013.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {rsp_demux_013.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {crosser.in_clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {crosser_001.in_clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {crosser_002.out_clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {crosser_003.out_clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {nios2_gen2_reset_reset_bridge.clk} {clock};add_connection {clk_50_clk_clock_bridge.out_clk} {altpll_0_inclk_interface_reset_reset_bridge.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {EEE_IMGPROC_0_s1_translator.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rsp_fifo.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {TERASIC_AUTO_FOCUS_0_mm_ctrl_agent_rdata_fifo.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {EEE_IMGPROC_0_s1_agent.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {EEE_IMGPROC_0_s1_agent_rsp_fifo.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {EEE_IMGPROC_0_s1_agent_rdata_fifo.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {router_007.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {router_016.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {cmd_mux_005.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {rsp_demux_005.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {cmd_mux_014.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {rsp_demux_014.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {crosser.out_clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {crosser_001.out_clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {crosser_002.in_clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {crosser_003.in_clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.clk} {clock};add_interface {altpll_0_c2} {clock} {slave};set_interface_property {altpll_0_c2} {EXPORT_OF} {altpll_0_c2_clock_bridge.in_clk};add_interface {clk_50_clk} {clock} {slave};set_interface_property {clk_50_clk} {EXPORT_OF} {clk_50_clk_clock_bridge.in_clk};add_interface {altpll_0_inclk_interface_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {altpll_0_inclk_interface_reset_reset_bridge_in_reset} {EXPORT_OF} {altpll_0_inclk_interface_reset_reset_bridge.in_reset};add_interface {nios2_gen2_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {nios2_gen2_reset_reset_bridge_in_reset} {EXPORT_OF} {nios2_gen2_reset_reset_bridge.in_reset};add_interface {TERASIC_AUTO_FOCUS_0_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {TERASIC_AUTO_FOCUS_0_reset_reset_bridge_in_reset} {EXPORT_OF} {TERASIC_AUTO_FOCUS_0_reset_reset_bridge.in_reset};add_interface {nios2_gen2_data_master} {avalon} {slave};set_interface_property {nios2_gen2_data_master} {EXPORT_OF} {nios2_gen2_data_master_translator.avalon_anti_master_0};add_interface {nios2_gen2_instruction_master} {avalon} {slave};set_interface_property {nios2_gen2_instruction_master} {EXPORT_OF} {nios2_gen2_instruction_master_translator.avalon_anti_master_0};add_interface {altpll_0_pll_slave} {avalon} {master};set_interface_property {altpll_0_pll_slave} {EXPORT_OF} {altpll_0_pll_slave_translator.avalon_anti_slave_0};add_interface {EEE_IMGPROC_0_s1} {avalon} {master};set_interface_property {EEE_IMGPROC_0_s1} {EXPORT_OF} {EEE_IMGPROC_0_s1_translator.avalon_anti_slave_0};add_interface {i2c_opencores_camera_avalon_slave_0} {avalon} {master};set_interface_property {i2c_opencores_camera_avalon_slave_0} {EXPORT_OF} {i2c_opencores_camera_avalon_slave_0_translator.avalon_anti_slave_0};add_interface {i2c_opencores_mipi_avalon_slave_0} {avalon} {master};set_interface_property {i2c_opencores_mipi_avalon_slave_0} {EXPORT_OF} {i2c_opencores_mipi_avalon_slave_0_translator.avalon_anti_slave_0};add_interface {jtag_uart_avalon_jtag_slave} {avalon} {master};set_interface_property {jtag_uart_avalon_jtag_slave} {EXPORT_OF} {jtag_uart_avalon_jtag_slave_translator.avalon_anti_slave_0};add_interface {key_s1} {avalon} {master};set_interface_property {key_s1} {EXPORT_OF} {key_s1_translator.avalon_anti_slave_0};add_interface {led_s1} {avalon} {master};set_interface_property {led_s1} {EXPORT_OF} {led_s1_translator.avalon_anti_slave_0};add_interface {mipi_pwdn_n_s1} {avalon} {master};set_interface_property {mipi_pwdn_n_s1} {EXPORT_OF} {mipi_pwdn_n_s1_translator.avalon_anti_slave_0};add_interface {mipi_reset_n_s1} {avalon} {master};set_interface_property {mipi_reset_n_s1} {EXPORT_OF} {mipi_reset_n_s1_translator.avalon_anti_slave_0};add_interface {nios2_gen2_debug_mem_slave} {avalon} {master};set_interface_property {nios2_gen2_debug_mem_slave} {EXPORT_OF} {nios2_gen2_debug_mem_slave_translator.avalon_anti_slave_0};add_interface {onchip_memory2_0_s1} {avalon} {master};set_interface_property {onchip_memory2_0_s1} {EXPORT_OF} {onchip_memory2_0_s1_translator.avalon_anti_slave_0};add_interface {sw_s1} {avalon} {master};set_interface_property {sw_s1} {EXPORT_OF} {sw_s1_translator.avalon_anti_slave_0};add_interface {sysid_qsys_control_slave} {avalon} {master};set_interface_property {sysid_qsys_control_slave} {EXPORT_OF} {sysid_qsys_control_slave_translator.avalon_anti_slave_0};add_interface {TERASIC_AUTO_FOCUS_0_mm_ctrl} {avalon} {master};set_interface_property {TERASIC_AUTO_FOCUS_0_mm_ctrl} {EXPORT_OF} {TERASIC_AUTO_FOCUS_0_mm_ctrl_translator.avalon_anti_slave_0};add_interface {timer_s1} {avalon} {master};set_interface_property {timer_s1} {EXPORT_OF} {timer_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.EEE_IMGPROC_0.s1} {0};set_module_assignment {interconnect_id.TERASIC_AUTO_FOCUS_0.mm_ctrl} {1};set_module_assignment {interconnect_id.altpll_0.pll_slave} {2};set_module_assignment {interconnect_id.i2c_opencores_camera.avalon_slave_0} {3};set_module_assignment {interconnect_id.i2c_opencores_mipi.avalon_slave_0} {4};set_module_assignment {interconnect_id.jtag_uart.avalon_jtag_slave} {5};set_module_assignment {interconnect_id.key.s1} {6};set_module_assignment {interconnect_id.led.s1} {7};set_module_assignment {interconnect_id.mipi_pwdn_n.s1} {8};set_module_assignment {interconnect_id.mipi_reset_n.s1} {9};set_module_assignment {interconnect_id.nios2_gen2.data_master} {0};set_module_assignment {interconnect_id.nios2_gen2.debug_mem_slave} {10};set_module_assignment {interconnect_id.nios2_gen2.instruction_master} {1};set_module_assignment {interconnect_id.onchip_memory2_0.s1} {11};set_module_assignment {interconnect_id.sw.s1} {12};set_module_assignment {interconnect_id.sysid_qsys.control_slave} {13};set_module_assignment {interconnect_id.timer.s1} {14};" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" /> - + + + + + + + + + + + + + + + + + + + + + + + + + + - + + queue size: 205 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_0" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 113 modules, 386 connections]]> + Transform: MMTransform + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 113 modules, 386 connections]]> + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.029s/0.039s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.012s/0.013s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.013s/0.014s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.012s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.017s/0.027s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.013s/0.016s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.012s/0.014s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.012s/0.013s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.001s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.016s/0.024s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.001s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.008s + Timing: COM:3/0.012s/0.013s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.011s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.000s + Timing: ELA:1/0.007s + Timing: COM:3/0.011s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.015s/0.022s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.000s/0.001s + Timing: ELA:1/0.007s + Timing: COM:3/0.011s/0.012s + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.012s/0.015s + 128 modules, 431 connections]]> + Transform: ResetAdaptation + mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002"]]> + mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> + mm_interconnect_0" reuses altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux"]]> + mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux"]]> + mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter"]]> + Qsys" instantiated altera_mm_interconnect "mm_interconnect_0"]]> + queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> + queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> + queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> + queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> + queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> + queue size: 92 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router" + mm_interconnect_0" instantiated altera_merlin_router "router"]]> + queue size: 91 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001" + mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> + queue size: 90 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002" + mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> + queue size: 86 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006" + mm_interconnect_0" instantiated altera_merlin_router "router_006"]]> + queue size: 75 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" + mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v]]> + queue size: 73 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> + queue size: 72 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> + queue size: 71 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> + queue size: 67 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 56 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> + queue size: 52 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"]]> + queue size: 51 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"]]> + queue size: 41 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux" + mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 40 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001" + mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 39 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" + mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> + queue size: 35 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> + mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> + queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + @@ -5114,55 +8008,402 @@ child process exited abnormally user_default="0" /> </address_map> };set_instance_parameter_value {alt_vip_vfb_0_write_master_agent} {SUPPRESS_0_BYTEEN_RSP} {0};set_instance_parameter_value {alt_vip_vfb_0_write_master_agent} {ID} {1};set_instance_parameter_value {alt_vip_vfb_0_write_master_agent} {BURSTWRAP_VALUE} {1};set_instance_parameter_value {alt_vip_vfb_0_write_master_agent} {CACHE_VALUE} {0};set_instance_parameter_value {alt_vip_vfb_0_write_master_agent} {SECURE_ACCESS_BIT} {1};set_instance_parameter_value {alt_vip_vfb_0_write_master_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {alt_vip_vfb_0_write_master_agent} {USE_WRITERESPONSE} {0};add_instance {sdram_s1_agent} {altera_merlin_slave_agent};set_instance_parameter_value {sdram_s1_agent} {PKT_ORI_BURST_SIZE_H} {85};set_instance_parameter_value {sdram_s1_agent} {PKT_ORI_BURST_SIZE_L} {83};set_instance_parameter_value {sdram_s1_agent} {PKT_RESPONSE_STATUS_H} {82};set_instance_parameter_value {sdram_s1_agent} {PKT_RESPONSE_STATUS_L} {81};set_instance_parameter_value {sdram_s1_agent} {PKT_BURST_SIZE_H} {64};set_instance_parameter_value {sdram_s1_agent} {PKT_BURST_SIZE_L} {62};set_instance_parameter_value {sdram_s1_agent} {PKT_TRANS_LOCK} {54};set_instance_parameter_value {sdram_s1_agent} {PKT_BEGIN_BURST} {69};set_instance_parameter_value {sdram_s1_agent} {PKT_PROTECTION_H} {76};set_instance_parameter_value {sdram_s1_agent} {PKT_PROTECTION_L} {74};set_instance_parameter_value {sdram_s1_agent} {PKT_BURSTWRAP_H} {61};set_instance_parameter_value {sdram_s1_agent} {PKT_BURSTWRAP_L} {61};set_instance_parameter_value {sdram_s1_agent} {PKT_BYTE_CNT_H} {60};set_instance_parameter_value {sdram_s1_agent} {PKT_BYTE_CNT_L} {56};set_instance_parameter_value {sdram_s1_agent} {PKT_ADDR_H} {49};set_instance_parameter_value {sdram_s1_agent} {PKT_ADDR_L} {18};set_instance_parameter_value {sdram_s1_agent} {PKT_TRANS_COMPRESSED_READ} {50};set_instance_parameter_value {sdram_s1_agent} {PKT_TRANS_POSTED} {51};set_instance_parameter_value {sdram_s1_agent} {PKT_TRANS_WRITE} {52};set_instance_parameter_value {sdram_s1_agent} {PKT_TRANS_READ} {53};set_instance_parameter_value {sdram_s1_agent} {PKT_DATA_H} {15};set_instance_parameter_value {sdram_s1_agent} {PKT_DATA_L} {0};set_instance_parameter_value {sdram_s1_agent} {PKT_BYTEEN_H} {17};set_instance_parameter_value {sdram_s1_agent} {PKT_BYTEEN_L} {16};set_instance_parameter_value {sdram_s1_agent} {PKT_SRC_ID_H} {71};set_instance_parameter_value {sdram_s1_agent} {PKT_SRC_ID_L} {71};set_instance_parameter_value {sdram_s1_agent} {PKT_DEST_ID_H} {72};set_instance_parameter_value {sdram_s1_agent} {PKT_DEST_ID_L} {72};set_instance_parameter_value {sdram_s1_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {sdram_s1_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {sdram_s1_agent} {ST_DATA_W} {86};set_instance_parameter_value {sdram_s1_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {sdram_s1_agent} {AVS_BURSTCOUNT_W} {2};set_instance_parameter_value {sdram_s1_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {sdram_s1_agent} {MERLIN_PACKET_FORMAT} {ori_burst_size(85:83) response_status(82:81) cache(80:77) protection(76:74) thread_id(73) dest_id(72) src_id(71) qos(70) begin_burst(69) data_sideband(68) addr_sideband(67) burst_type(66:65) burst_size(64:62) burstwrap(61) byte_cnt(60:56) trans_exclusive(55) trans_lock(54) trans_read(53) trans_write(52) trans_posted(51) trans_compressed_read(50) addr(49:18) byteen(17:16) data(15:0)};set_instance_parameter_value {sdram_s1_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {sdram_s1_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {sdram_s1_agent} {MAX_BYTE_CNT} {2};set_instance_parameter_value {sdram_s1_agent} {MAX_BURSTWRAP} {1};set_instance_parameter_value {sdram_s1_agent} {ID} {0};set_instance_parameter_value {sdram_s1_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {sdram_s1_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {sdram_s1_agent} {ECC_ENABLE} {0};add_instance {sdram_s1_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {BITS_PER_SYMBOL} {87};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {FIFO_DEPTH} {8};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sdram_s1_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {sdram_s1_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {BITS_PER_SYMBOL} {18};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {FIFO_DEPTH} {8};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {EMPTY_LATENCY} {3};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {1};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {sdram_s1_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x4000000 };set_instance_parameter_value {router} {END_ADDRESS} {0x8000000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {67};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {94};set_instance_parameter_value {router} {PKT_PROTECTION_L} {92};set_instance_parameter_value {router} {PKT_DEST_ID_H} {90};set_instance_parameter_value {router} {PKT_DEST_ID_L} {90};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {70};set_instance_parameter_value {router} {PKT_TRANS_READ} {71};set_instance_parameter_value {router} {ST_DATA_W} {104};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x4000000 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x8000000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {67};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {94};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {92};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {90};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {90};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {70};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {71};set_instance_parameter_value {router_001} {ST_DATA_W} {104};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 1 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {read write };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {49};set_instance_parameter_value {router_002} {PKT_ADDR_L} {18};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {76};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {74};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {72};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {72};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {52};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {53};set_instance_parameter_value {router_002} {ST_DATA_W} {86};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {ori_burst_size(85:83) response_status(82:81) cache(80:77) protection(76:74) thread_id(73) dest_id(72) src_id(71) qos(70) begin_burst(69) data_sideband(68) addr_sideband(67) burst_type(66:65) burst_size(64:62) burstwrap(61) byte_cnt(60:56) trans_exclusive(55) trans_lock(54) trans_read(53) trans_write(52) trans_posted(51) trans_compressed_read(50) addr(49:18) byteen(17:16) data(15:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};add_instance {sdram_s1_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_ADDR_H} {49};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_ADDR_L} {18};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BEGIN_BURST} {69};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BYTE_CNT_H} {60};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BYTE_CNT_L} {56};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BYTEEN_H} {17};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BYTEEN_L} {16};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BURST_SIZE_H} {64};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BURST_SIZE_L} {62};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BURST_TYPE_H} {66};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BURST_TYPE_L} {65};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BURSTWRAP_H} {61};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_BURSTWRAP_L} {61};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {50};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_TRANS_WRITE} {52};set_instance_parameter_value {sdram_s1_burst_adapter} {PKT_TRANS_READ} {53};set_instance_parameter_value {sdram_s1_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {sdram_s1_burst_adapter} {IN_NARROW_SIZE} {0};set_instance_parameter_value {sdram_s1_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {sdram_s1_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {sdram_s1_burst_adapter} {ST_DATA_W} {86};set_instance_parameter_value {sdram_s1_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {sdram_s1_burst_adapter} {OUT_BYTE_CNT_H} {57};set_instance_parameter_value {sdram_s1_burst_adapter} {OUT_BURSTWRAP_H} {61};set_instance_parameter_value {sdram_s1_burst_adapter} {MERLIN_PACKET_FORMAT} {ori_burst_size(85:83) response_status(82:81) cache(80:77) protection(76:74) thread_id(73) dest_id(72) src_id(71) qos(70) begin_burst(69) data_sideband(68) addr_sideband(67) burst_type(66:65) burst_size(64:62) burstwrap(61) byte_cnt(60:56) trans_exclusive(55) trans_lock(54) trans_read(53) trans_write(52) trans_posted(51) trans_compressed_read(50) addr(49:18) byteen(17:16) data(15:0)};set_instance_parameter_value {sdram_s1_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {sdram_s1_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {sdram_s1_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {sdram_s1_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {sdram_s1_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {sdram_s1_burst_adapter} {BURSTWRAP_CONST_MASK} {1};set_instance_parameter_value {sdram_s1_burst_adapter} {BURSTWRAP_CONST_VALUE} {1};set_instance_parameter_value {sdram_s1_burst_adapter} {ADAPTER_VERSION} {13.1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {104};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {104};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {104};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {72};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {50 30 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {104};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {104};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {72};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {104};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {72};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};add_instance {sdram_s1_rsp_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_ADDR_H} {49};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_ADDR_L} {18};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_DATA_H} {15};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_H} {17};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BYTEEN_L} {16};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_H} {60};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BYTE_CNT_L} {56};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {50};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_TRANS_WRITE} {52};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_H} {61};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BURSTWRAP_L} {61};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_H} {64};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BURST_SIZE_L} {62};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {82};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {81};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {55};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_H} {66};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_BURST_TYPE_L} {65};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {83};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {85};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_ST_DATA_W} {86};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_ADDR_H} {67};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_ADDR_L} {36};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_DATA_H} {31};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_H} {35};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BYTEEN_L} {32};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_H} {78};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BYTE_CNT_L} {74};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {68};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_H} {82};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BURST_SIZE_L} {80};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {100};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {99};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {73};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_H} {84};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_BURST_TYPE_L} {83};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {101};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {103};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_ST_DATA_W} {104};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {RESPONSE_PATH} {1};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {PACKING} {1};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(85:83) response_status(82:81) cache(80:77) protection(76:74) thread_id(73) dest_id(72) src_id(71) qos(70) begin_burst(69) data_sideband(68) addr_sideband(67) burst_type(66:65) burst_size(64:62) burstwrap(61) byte_cnt(60:56) trans_exclusive(55) trans_lock(54) trans_read(53) trans_write(52) trans_posted(51) trans_compressed_read(50) addr(49:18) byteen(17:16) data(15:0)};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {sdram_s1_rsp_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {sdram_s1_cmd_width_adapter} {altera_merlin_width_adapter};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_ADDR_H} {67};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_ADDR_L} {36};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_DATA_H} {31};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_DATA_L} {0};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_H} {35};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BYTEEN_L} {32};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_H} {78};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BYTE_CNT_L} {74};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_TRANS_COMPRESSED_READ} {68};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_TRANS_WRITE} {70};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_H} {79};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BURSTWRAP_L} {79};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_H} {82};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BURST_SIZE_L} {80};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_H} {100};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_RESPONSE_STATUS_L} {99};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_TRANS_EXCLUSIVE} {73};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_H} {84};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_BURST_TYPE_L} {83};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_L} {101};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_PKT_ORI_BURST_SIZE_H} {103};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_ST_DATA_W} {104};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_ADDR_H} {49};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_ADDR_L} {18};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_DATA_H} {15};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_DATA_L} {0};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_H} {17};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BYTEEN_L} {16};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_H} {60};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BYTE_CNT_L} {56};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_TRANS_COMPRESSED_READ} {50};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_H} {64};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BURST_SIZE_L} {62};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_H} {82};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_RESPONSE_STATUS_L} {81};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_TRANS_EXCLUSIVE} {55};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_H} {66};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_BURST_TYPE_L} {65};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_L} {83};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_PKT_ORI_BURST_SIZE_H} {85};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_ST_DATA_W} {86};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OPTIMIZE_FOR_RSP} {0};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {RESPONSE_PATH} {0};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {CONSTANT_BURST_SIZE} {1};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {PACKING} {1};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {IN_MERLIN_PACKET_FORMAT} {ori_burst_size(103:101) response_status(100:99) cache(98:95) protection(94:92) thread_id(91) dest_id(90) src_id(89) qos(88) begin_burst(87) data_sideband(86) addr_sideband(85) burst_type(84:83) burst_size(82:80) burstwrap(79) byte_cnt(78:74) trans_exclusive(73) trans_lock(72) trans_read(71) trans_write(70) trans_posted(69) trans_compressed_read(68) addr(67:36) byteen(35:32) data(31:0)};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {OUT_MERLIN_PACKET_FORMAT} {ori_burst_size(85:83) response_status(82:81) cache(80:77) protection(76:74) thread_id(73) dest_id(72) src_id(71) qos(70) begin_burst(69) data_sideband(68) addr_sideband(67) burst_type(66:65) burst_size(64:62) burstwrap(61) byte_cnt(60:56) trans_exclusive(55) trans_lock(54) trans_read(53) trans_write(52) trans_posted(51) trans_compressed_read(50) addr(49:18) byteen(17:16) data(15:0)};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {COMMAND_SIZE_W} {3};set_instance_parameter_value {sdram_s1_cmd_width_adapter} {ENABLE_ADDRESS_ALIGNMENT} {0};add_instance {alt_vip_vfb_0_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {alt_vip_vfb_0_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {alt_vip_vfb_0_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {alt_vip_vfb_0_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {alt_vip_vfb_0_reset_reset_bridge} {USE_RESET_REQUEST} {0};add_instance {altpll_0_c2_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {altpll_0_c2_clock_bridge} {EXPLICIT_CLOCK_RATE} {100000000};set_instance_parameter_value {altpll_0_c2_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {alt_vip_vfb_0_read_master_translator.avalon_universal_master_0} {alt_vip_vfb_0_read_master_agent.av} {avalon};set_connection_parameter_value {alt_vip_vfb_0_read_master_translator.avalon_universal_master_0/alt_vip_vfb_0_read_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {alt_vip_vfb_0_read_master_translator.avalon_universal_master_0/alt_vip_vfb_0_read_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {alt_vip_vfb_0_read_master_translator.avalon_universal_master_0/alt_vip_vfb_0_read_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux.src} {alt_vip_vfb_0_read_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux.src/alt_vip_vfb_0_read_master_agent.rp} {qsys_mm.response};add_connection {alt_vip_vfb_0_write_master_translator.avalon_universal_master_0} {alt_vip_vfb_0_write_master_agent.av} {avalon};set_connection_parameter_value {alt_vip_vfb_0_write_master_translator.avalon_universal_master_0/alt_vip_vfb_0_write_master_agent.av} {arbitrationPriority} {1};set_connection_parameter_value {alt_vip_vfb_0_write_master_translator.avalon_universal_master_0/alt_vip_vfb_0_write_master_agent.av} {baseAddress} {0x0000};set_connection_parameter_value {alt_vip_vfb_0_write_master_translator.avalon_universal_master_0/alt_vip_vfb_0_write_master_agent.av} {defaultConnection} {false};add_connection {rsp_mux_001.src} {alt_vip_vfb_0_write_master_agent.rp} {avalon_streaming};preview_set_connection_tag {rsp_mux_001.src/alt_vip_vfb_0_write_master_agent.rp} {qsys_mm.response};add_connection {sdram_s1_agent.m0} {sdram_s1_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {sdram_s1_agent.m0/sdram_s1_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {sdram_s1_agent.m0/sdram_s1_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {sdram_s1_agent.m0/sdram_s1_translator.avalon_universal_slave_0} {defaultConnection} {false};add_connection {sdram_s1_agent.rf_source} {sdram_s1_agent_rsp_fifo.in} {avalon_streaming};add_connection {sdram_s1_agent_rsp_fifo.out} {sdram_s1_agent.rf_sink} {avalon_streaming};add_connection {sdram_s1_agent.rdata_fifo_src} {sdram_s1_agent_rdata_fifo.in} {avalon_streaming};add_connection {sdram_s1_agent_rdata_fifo.out} {sdram_s1_agent.rdata_fifo_sink} {avalon_streaming};add_connection {alt_vip_vfb_0_read_master_agent.cp} {router.sink} {avalon_streaming};preview_set_connection_tag {alt_vip_vfb_0_read_master_agent.cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {alt_vip_vfb_0_write_master_agent.cp} {router_001.sink} {avalon_streaming};preview_set_connection_tag {alt_vip_vfb_0_write_master_agent.cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {sdram_s1_agent.rp} {router_002.sink} {avalon_streaming};preview_set_connection_tag {sdram_s1_agent.rp/router_002.sink} {qsys_mm.response};add_connection {sdram_s1_burst_adapter.source0} {sdram_s1_agent.cp} {avalon_streaming};preview_set_connection_tag {sdram_s1_burst_adapter.source0/sdram_s1_agent.cp} {qsys_mm.command};add_connection {cmd_demux.src0} {cmd_mux.sink0} {avalon_streaming};preview_set_connection_tag {cmd_demux.src0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {cmd_mux.sink1} {avalon_streaming};preview_set_connection_tag {cmd_demux_001.src0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {rsp_mux.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {rsp_mux_001.sink0} {avalon_streaming};preview_set_connection_tag {rsp_demux.src1/rsp_mux_001.sink0} {qsys_mm.response};add_connection {router_002.src} {sdram_s1_rsp_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {router_002.src/sdram_s1_rsp_width_adapter.sink} {qsys_mm.response};add_connection {sdram_s1_rsp_width_adapter.src} {rsp_demux.sink} {avalon_streaming};preview_set_connection_tag {sdram_s1_rsp_width_adapter.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_mux.src} {sdram_s1_cmd_width_adapter.sink} {avalon_streaming};preview_set_connection_tag {cmd_mux.src/sdram_s1_cmd_width_adapter.sink} {qsys_mm.command};add_connection {sdram_s1_cmd_width_adapter.src} {sdram_s1_burst_adapter.sink0} {avalon_streaming};preview_set_connection_tag {sdram_s1_cmd_width_adapter.src/sdram_s1_burst_adapter.sink0} {qsys_mm.command};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {alt_vip_vfb_0_read_master_translator.reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {alt_vip_vfb_0_write_master_translator.reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {sdram_s1_translator.reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {alt_vip_vfb_0_read_master_agent.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {alt_vip_vfb_0_write_master_agent.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {sdram_s1_agent.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {sdram_s1_agent_rsp_fifo.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {sdram_s1_agent_rdata_fifo.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {sdram_s1_burst_adapter.cr0_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {sdram_s1_rsp_width_adapter.clk_reset} {reset};add_connection {alt_vip_vfb_0_reset_reset_bridge.out_reset} {sdram_s1_cmd_width_adapter.clk_reset} {reset};add_connection {altpll_0_c2_clock_bridge.out_clk} {alt_vip_vfb_0_read_master_translator.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {alt_vip_vfb_0_write_master_translator.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {sdram_s1_translator.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {alt_vip_vfb_0_read_master_agent.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {alt_vip_vfb_0_write_master_agent.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {sdram_s1_agent.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {sdram_s1_agent_rsp_fifo.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {sdram_s1_agent_rdata_fifo.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {router.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {sdram_s1_burst_adapter.cr0} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {sdram_s1_rsp_width_adapter.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {sdram_s1_cmd_width_adapter.clk} {clock};add_connection {altpll_0_c2_clock_bridge.out_clk} {alt_vip_vfb_0_reset_reset_bridge.clk} {clock};add_interface {altpll_0_c2} {clock} {slave};set_interface_property {altpll_0_c2} {EXPORT_OF} {altpll_0_c2_clock_bridge.in_clk};add_interface {alt_vip_vfb_0_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {alt_vip_vfb_0_reset_reset_bridge_in_reset} {EXPORT_OF} {alt_vip_vfb_0_reset_reset_bridge.in_reset};add_interface {alt_vip_vfb_0_read_master} {avalon} {slave};set_interface_property {alt_vip_vfb_0_read_master} {EXPORT_OF} {alt_vip_vfb_0_read_master_translator.avalon_anti_master_0};add_interface {alt_vip_vfb_0_write_master} {avalon} {slave};set_interface_property {alt_vip_vfb_0_write_master} {EXPORT_OF} {alt_vip_vfb_0_write_master_translator.avalon_anti_master_0};add_interface {sdram_s1} {avalon} {master};set_interface_property {sdram_s1} {EXPORT_OF} {sdram_s1_translator.avalon_anti_slave_0};set_module_assignment {interconnect_id.alt_vip_vfb_0.read_master} {0};set_module_assignment {interconnect_id.alt_vip_vfb_0.write_master} {1};set_module_assignment {interconnect_id.sdram.s1} {0};" /> - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" /> - + + + + + + + + + + + + + + + + + + - + + queue size: 327 starting:altera_mm_interconnect "submodules/Qsys_mm_interconnect_1" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 22 modules, 64 connections]]> + Transform: MMTransform + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 22 modules, 64 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 22 modules, 64 connections]]> + Transform: InitialInterconnectTransform + 0 modules, 0 connections]]> + Transform: TerminalIdAssignmentUpdateTransform + Transform: DefaultSlaveTransform + Transform: TranslatorTransform + No Avalon connections, skipping transform + Transform: IDPadTransform + Transform: DomainTransform + Transform: RouterTransform + Transform: TrafficLimiterTransform + Transform: BurstTransform + Transform: TreeTransform + Transform: NetworkToSwitchTransform + Transform: WidthTransform + Transform: RouterTableTransform + Transform: ThreadIDMappingTableTransform + Transform: ClockCrossingTransform + Transform: PipelineTransform + Transform: SpotPipelineTransform + Transform: PerformanceMonitorTransform + Transform: TrafficLimiterUpdateTransform + Transform: InsertClockAndResetBridgesTransform + Transform: InterconnectConnectionsTagger + Transform: HierarchyTransform + 22 modules, 64 connections]]> + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + + + + Inserting error_adapter: error_adapter_0 + Timing: ELA:1/0.000s + Timing: ELA:2/0.001s/0.001s + Timing: ELA:1/0.006s + Timing: COM:3/0.012s/0.013s + 23 modules, 67 connections]]> + Transform: ResetAdaptation + mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_1" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> + mm_interconnect_1" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> + mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_1" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> + mm_interconnect_1" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> + mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_1" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> + mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> + mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router"]]> + mm_interconnect_1" reuses altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002"]]> + mm_interconnect_1" reuses altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter"]]> + mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> + mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux"]]> + mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux"]]> + mm_interconnect_1" reuses altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux"]]> + mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> + mm_interconnect_1" reuses altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux"]]> + mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> + mm_interconnect_1" reuses altera_merlin_width_adapter "submodules/altera_merlin_width_adapter"]]> + mm_interconnect_1" reuses altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter"]]> + Qsys" instantiated altera_mm_interconnect "mm_interconnect_1"]]> + queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> + queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> + queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> + queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> + queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> + queue size: 13 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router" + mm_interconnect_1" instantiated altera_merlin_router "router"]]> + queue size: 11 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002" + mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> + queue size: 10 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" + mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> + queue size: 9 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux" + mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> + queue size: 7 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux" + mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 6 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux" + mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> + queue size: 5 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux" + mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + queue size: 3 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" + mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> + queue size: 1 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> + mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> + queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + - + + + + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" /> - + + queue size: 347 starting:altera_irq_mapper "submodules/Qsys_irq_mapper" + Qsys" instantiated altera_irq_mapper "irq_mapper"]]> + - + + + + + + path="C:/intelfpga_lite/16.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" /> - + + queue size: 346 starting:altera_reset_controller "submodules/altera_reset_controller" + Qsys" instantiated altera_reset_controller "rst_controller"]]> + + name="alt_cusp161_muxbin2"> - + + + - + + queue size: 343 starting:alt_cusp_muxbin2 "submodules/alt_cusp161_muxbin2" + alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst"]]> + + name="alt_cusp161_au"> - + + + + + - + + queue size: 341 starting:alt_au "submodules/alt_cusp161_au" + alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au"]]> + + name="alt_cusp161_reg"> - + + + + - + + queue size: 332 starting:alt_reg "submodules/alt_cusp161_reg" + alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + name="alt_cusp161_muxhot16"> - + + + - + + queue size: 331 starting:alt_cusp_muxhot16 "submodules/alt_cusp161_muxhot16" + alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst"]]> + + name="alt_cusp161_avalon_st_input"> - + + + + - + + queue size: 307 starting:alt_avalon_st_input "submodules/alt_cusp161_avalon_st_input" + alt_vip_vfb_0" instantiated alt_avalon_st_input "din"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + name="alt_cusp161_avalon_st_output"> - + + + + + - + + queue size: 302 starting:alt_avalon_st_output "submodules/alt_cusp161_avalon_st_output" + alt_vip_vfb_0" instantiated alt_avalon_st_output "dout"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + name="alt_cusp161_avalon_mm_bursting_master_fifo"> @@ -5305,12 +8609,47 @@ child process exited abnormally - + + + + + + + + + + + + - + + queue size: 298 starting:alt_avalon_mm_bursting_master_fifo "submodules/alt_cusp161_avalon_mm_bursting_master_fifo" + alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + name="alt_cusp161_pulling_width_adapter"> - + + + + - + + queue size: 296 starting:alt_cusp_pulling_width_adapter "submodules/alt_cusp161_pulling_width_adapter" + alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + name="alt_cusp161_pushing_width_adapter"> - + + + + - + + queue size: 290 starting:alt_cusp_pushing_width_adapter "submodules/alt_cusp161_pushing_width_adapter" + alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + name="alt_cusp161_pc"> @@ -5367,12 +8728,23 @@ child process exited abnormally name="PROGRAM_TRACE" value="Qsys_alt_vip_vfb_0_vfb_writer_vfb_writer.trace" /> - + + + + - + + queue size: 256 starting:alt_pc "submodules/alt_cusp161_pc" + alt_vip_vfb_0" instantiated alt_pc "pc0"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + name="alt_cusp161_cmp"> - + + + + - + + queue size: 196 starting:alt_cmp "submodules/alt_cusp161_cmp" + alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + - + name="alt_cusp161_clock_reset"> + + + + - + + queue size: 146 starting:alt_cusp_testbench_clock "submodules/alt_cusp161_clock_reset" + alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 144 starting:altera_nios2_gen2_unit "submodules/Qsys_nios2_gen2_cpu" + Starting RTL generation for module 'Qsys_nios2_gen2_cpu' + Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] + # 2021.05.27 17:51:00 (*) Starting Nios II generation + # 2021.05.27 17:51:00 (*) Checking for plaintext license. + # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ + # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty + # 2021.05.27 17:51:01 (*) Plaintext license not found. + # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation). + # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ + # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable + # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty + # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) + # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings + # 2021.05.27 17:51:01 (*) Creating all objects for CPU + # 2021.05.27 17:51:01 (*) Testbench + # 2021.05.27 17:51:02 (*) Instruction decoding + # 2021.05.27 17:51:02 (*) Instruction fields + # 2021.05.27 17:51:02 (*) Instruction decodes + # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms + # 2021.05.27 17:51:02 (*) Instruction controls + # 2021.05.27 17:51:02 (*) Pipeline frontend + # 2021.05.27 17:51:02 (*) Pipeline backend + # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects + # 2021.05.27 17:51:06 (*) Creating encrypted RTL + # 2021.05.27 17:51:07 (*) Done Nios II generation + Done RTL generation for module 'Qsys_nios2_gen2_cpu' + nios2_gen2" instantiated altera_nios2_gen2_unit "cpu"]]> + + + + + + + + + + + + + + + + queue size: 143 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" + mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator"]]> + + + + + + + + + + + + + + + queue size: 141 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" + mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator"]]> + + + + + + + + + + + + + + + queue size: 126 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" + mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent"]]> + + + + + + + + + + + + + + + + queue size: 124 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" + mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent"]]> + + + + + + + + + + + + + + + + + + queue size: 123 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" + mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 92 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router" + mm_interconnect_0" instantiated altera_merlin_router "router"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 91 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_001" + mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 90 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_002" + mm_interconnect_0" instantiated altera_merlin_router "router_002"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 86 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_0_router_006" + mm_interconnect_0" instantiated altera_merlin_router "router_006"]]> + + + + + + + + + + + + + + + + + queue size: 75 starting:altera_merlin_traffic_limiter "submodules/altera_merlin_traffic_limiter" + mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v]]> + + + + + + + + + + + + + + + + + + + + + queue size: 73 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> + + + + + + + + + + + + + + + + + + + + + queue size: 72 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_cmd_demux_001" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"]]> + + + + + + + + + + + + + + + + + + + + + + + + queue size: 71 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> + + + + + + + + + + + + + + + + + + + + + + + + queue size: 67 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_cmd_mux_004" + mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + + + + + + + + + + + + + + + + + + + + + queue size: 56 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"]]> + + + + + + + + + + + + + + + + + + + + + queue size: 52 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_004" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004"]]> + + + + + + + + + + + + + + + + + + + + + queue size: 51 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_0_rsp_demux_005" + mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005"]]> + + + + + + + + + + + + + + + + + + + + + + + + queue size: 41 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux" + mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + + + + + + + + + + + + + + + + + + + + + + + + queue size: 40 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_0_rsp_mux_001" + mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 39 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" + mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 35 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> + mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> + queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 13 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router" + mm_interconnect_1" instantiated altera_merlin_router "router"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 11 starting:altera_merlin_router "submodules/Qsys_mm_interconnect_1_router_002" + mm_interconnect_1" instantiated altera_merlin_router "router_002"]]> + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 10 starting:altera_merlin_burst_adapter "submodules/altera_merlin_burst_adapter" + mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v]]> + + + + + + + + + + + + + + + + + + + + + queue size: 9 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_cmd_demux" + mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux"]]> + + + + + + + + + + + + + + + + + + + + + + + + queue size: 7 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_cmd_mux" + mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + + + + + + + + + + + + + + + + + + + + + queue size: 6 starting:altera_merlin_demultiplexer "submodules/Qsys_mm_interconnect_1_rsp_demux" + mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux"]]> + + + + + + + + + + + + + + + + + + + + + + + + queue size: 5 starting:altera_merlin_multiplexer "submodules/Qsys_mm_interconnect_1_rsp_mux" + mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv]]> + + + + + + + + + + + + + + + + + + + + + + queue size: 3 starting:altera_merlin_width_adapter "submodules/altera_merlin_width_adapter" + mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter"]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv]]> + C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 1 starting:altera_avalon_st_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 3 modules, 3 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + avalon_st_adapter" reuses error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0"]]> + mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> + queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 1 starting:error_adapter "submodules/Qsys_mm_interconnect_0_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 0 starting:error_adapter "submodules/Qsys_mm_interconnect_1_avalon_st_adapter_error_adapter_0" + avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> + diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt index 6db46bd..88b925a 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt +++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation.rpt @@ -1,7 +1,9 @@ Info: Starting: Create block symbol file (.bsf) -Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G +Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --block-symbol-file --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys" --family="MAX 10" --part=10M50DAF484C7G Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Reading input file +Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0] +Progress: Parameterizing module EEE_IMGPROC_0 Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] @@ -10,35 +12,35 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0] Progress: Parameterizing module alt_vip_itc_0 Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Parameterizing module alt_vip_vfb_0 -Progress: Adding altpll_0 [altpll 16.0] +Progress: Adding altpll_0 [altpll 16.1] Progress: Parameterizing module altpll_0 -Progress: Adding clk_50 [clock_source 16.0] +Progress: Adding clk_50 [clock_source 16.1] Progress: Parameterizing module clk_50 Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_camera Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_mipi -Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] +Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Parameterizing module jtag_uart -Progress: Adding key [altera_avalon_pio 16.0] +Progress: Adding key [altera_avalon_pio 16.1] Progress: Parameterizing module key -Progress: Adding led [altera_avalon_pio 16.0] +Progress: Adding led [altera_avalon_pio 16.1] Progress: Parameterizing module led -Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] +Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_pwdn_n -Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] +Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_reset_n -Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] +Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Parameterizing module nios2_gen2 -Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] +Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Parameterizing module onchip_memory2_0 -Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] +Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Parameterizing module sdram -Progress: Adding sw [altera_avalon_pio 16.0] +Progress: Adding sw [altera_avalon_pio 16.1] Progress: Parameterizing module sw -Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] +Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Parameterizing module sysid_qsys -Progress: Adding timer [altera_avalon_timer 16.0] +Progress: Adding timer [altera_avalon_timer 16.1] Progress: Parameterizing module timer Progress: Building connections Progress: Parameterizing connections @@ -47,6 +49,7 @@ Progress: Done reading input file Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. @@ -54,9 +57,11 @@ Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Info: Starting: Create HDL design files for synthesis -Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G +Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --synthesis=VERILOG --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys\synthesis" --family="MAX 10" --part=10M50DAF484C7G Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Reading input file +Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0] +Progress: Parameterizing module EEE_IMGPROC_0 Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] @@ -65,35 +70,35 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0] Progress: Parameterizing module alt_vip_itc_0 Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Parameterizing module alt_vip_vfb_0 -Progress: Adding altpll_0 [altpll 16.0] +Progress: Adding altpll_0 [altpll 16.1] Progress: Parameterizing module altpll_0 -Progress: Adding clk_50 [clock_source 16.0] +Progress: Adding clk_50 [clock_source 16.1] Progress: Parameterizing module clk_50 Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_camera Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_mipi -Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] +Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Parameterizing module jtag_uart -Progress: Adding key [altera_avalon_pio 16.0] +Progress: Adding key [altera_avalon_pio 16.1] Progress: Parameterizing module key -Progress: Adding led [altera_avalon_pio 16.0] +Progress: Adding led [altera_avalon_pio 16.1] Progress: Parameterizing module led -Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] +Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_pwdn_n -Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] +Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_reset_n -Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] +Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Parameterizing module nios2_gen2 -Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] +Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Parameterizing module onchip_memory2_0 -Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] +Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Parameterizing module sdram -Progress: Adding sw [altera_avalon_pio 16.0] +Progress: Adding sw [altera_avalon_pio 16.1] Progress: Parameterizing module sw -Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] +Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Parameterizing module sysid_qsys -Progress: Adding timer [altera_avalon_timer 16.0] +Progress: Adding timer [altera_avalon_timer 16.1] Progress: Parameterizing module timer Progress: Building connections Progress: Parameterizing connections @@ -102,28 +107,167 @@ Progress: Done reading input file Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0 +Info: Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0 Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 +Info: Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14 +Info: EEE_IMGPROC_0: "Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0" Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0" Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0" Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0" Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0" -Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally -Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092322619640" ("eval" body line 1) invoked from within "eval exec $cbx_cmd " -Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v is missing -Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings -Error: Peak virtual memory: 1399 megabytes -Error: Processing ended: Tue Mar 30 09:18:43 2021 -Error: Elapsed time: 00:00:01 -Error: Total CPU time (on all processors): 00:00:00 -Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0 -Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0017_sopcgen/Qsys_altpll_0.v (No such file or directory) Info: altpll_0: "Qsys" instantiated altpll "altpll_0" -Error: Generation stopped, 218 or more modules remaining -Info: Qsys: Done "Qsys" with 33 modules, 34 files -Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning +Info: i2c_opencores_camera: "Qsys" instantiated i2c_opencores "i2c_opencores_camera" +Info: jtag_uart: Starting RTL generation for module 'Qsys_jtag_uart' +Info: jtag_uart: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0011_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] +Info: jtag_uart: Done RTL generation for module 'Qsys_jtag_uart' +Info: jtag_uart: "Qsys" instantiated altera_avalon_jtag_uart "jtag_uart" +Info: key: Starting RTL generation for module 'Qsys_key' +Info: key: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0012_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ] +Info: key: Done RTL generation for module 'Qsys_key' +Info: key: "Qsys" instantiated altera_avalon_pio "key" +Info: led: Starting RTL generation for module 'Qsys_led' +Info: led: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0013_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ] +Info: led: Done RTL generation for module 'Qsys_led' +Info: led: "Qsys" instantiated altera_avalon_pio "led" +Info: mipi_pwdn_n: Starting RTL generation for module 'Qsys_mipi_pwdn_n' +Info: mipi_pwdn_n: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0014_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ] +Info: mipi_pwdn_n: Done RTL generation for module 'Qsys_mipi_pwdn_n' +Info: mipi_pwdn_n: "Qsys" instantiated altera_avalon_pio "mipi_pwdn_n" +Info: nios2_gen2: "Qsys" instantiated altera_nios2_gen2 "nios2_gen2" +Info: onchip_memory2_0: Starting RTL generation for module 'Qsys_onchip_memory2_0' +Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0015_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ] +Info: onchip_memory2_0: Done RTL generation for module 'Qsys_onchip_memory2_0' +Info: onchip_memory2_0: "Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0" +Info: sdram: Starting RTL generation for module 'Qsys_sdram' +Info: sdram: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0016_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ] +Info: sdram: Done RTL generation for module 'Qsys_sdram' +Info: sdram: "Qsys" instantiated altera_avalon_new_sdram_controller "sdram" +Info: sw: Starting RTL generation for module 'Qsys_sw' +Info: sw: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0017_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ] +Info: sw: Done RTL generation for module 'Qsys_sw' +Info: sw: "Qsys" instantiated altera_avalon_pio "sw" +Info: sysid_qsys: "Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys" +Info: timer: Starting RTL generation for module 'Qsys_timer' +Info: timer: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0019_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ] +Info: timer: Done RTL generation for module 'Qsys_timer' +Info: timer: "Qsys" instantiated altera_avalon_timer "timer" +Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0 +Info: mm_interconnect_0: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_0" +Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 +Info: mm_interconnect_1: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_1" +Info: irq_mapper: "Qsys" instantiated altera_irq_mapper "irq_mapper" +Info: rst_controller: "Qsys" instantiated altera_reset_controller "rst_controller" +Info: vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst" +Info: vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au" +Info: vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst" +Info: din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: fu_id_4494_line325_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: cpu: Starting RTL generation for module 'Qsys_nios2_gen2_cpu' +Info: cpu: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_3370923321813107178.dir/0022_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] +Info: cpu: # 2021.05.27 17:51:00 (*) Starting Nios II generation +Info: cpu: # 2021.05.27 17:51:00 (*) Checking for plaintext license. +Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ +Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty +Info: cpu: # 2021.05.27 17:51:01 (*) Plaintext license not found. +Info: cpu: # 2021.05.27 17:51:01 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2021.05.27 17:51:01 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ +Info: cpu: # 2021.05.27 17:51:01 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2021.05.27 17:51:01 (*) LM_LICENSE_FILE environment variable is empty +Info: cpu: # 2021.05.27 17:51:01 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) +Info: cpu: # 2021.05.27 17:51:01 (*) Elaborating CPU configuration settings +Info: cpu: # 2021.05.27 17:51:01 (*) Creating all objects for CPU +Info: cpu: # 2021.05.27 17:51:01 (*) Testbench +Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decoding +Info: cpu: # 2021.05.27 17:51:02 (*) Instruction fields +Info: cpu: # 2021.05.27 17:51:02 (*) Instruction decodes +Info: cpu: # 2021.05.27 17:51:02 (*) Signals for RTL simulation waveforms +Info: cpu: # 2021.05.27 17:51:02 (*) Instruction controls +Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline frontend +Info: cpu: # 2021.05.27 17:51:02 (*) Pipeline backend +Info: cpu: # 2021.05.27 17:51:05 (*) Generating RTL from CPU objects +Info: cpu: # 2021.05.27 17:51:06 (*) Creating encrypted RTL +Info: cpu: # 2021.05.27 17:51:07 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'Qsys_nios2_gen2_cpu' +Info: cpu: "nios2_gen2" instantiated altera_nios2_gen2_unit "cpu" +Info: nios2_gen2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator" +Info: jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator" +Info: nios2_gen2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent" +Info: jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent" +Info: jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo" +Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" +Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001" +Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002" +Info: router_006: "mm_interconnect_0" instantiated altera_merlin_router "router_006" +Info: nios2_gen2_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v +Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" +Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001" +Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" +Info: cmd_mux_004: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" +Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004" +Info: rsp_demux_005: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005" +Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v +Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" +Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router" +Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002" +Info: sdram_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v +Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux" +Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux" +Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: sdram_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter" +Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" +Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" +Info: Qsys: Done "Qsys" with 67 modules, 142 files +Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis diff --git a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt index 3a37812..332e2e7 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt +++ b/Vision/DE10_LITE_D8M_VIP_16/Qsys/Qsys_generation_previous.rpt @@ -1,7 +1,9 @@ Info: Starting: Create block symbol file (.bsf) -Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --block-symbol-file --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys --family="MAX 10" --part=10M50DAF484C7G +Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --block-symbol-file --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys" --family="MAX 10" --part=10M50DAF484C7G Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Reading input file +Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0] +Progress: Parameterizing module EEE_IMGPROC_0 Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] @@ -10,36 +12,38 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0] Progress: Parameterizing module alt_vip_itc_0 Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Parameterizing module alt_vip_vfb_0 -Progress: Adding altpll_0 [altpll 16.0] +Progress: Adding altpll_0 [altpll 16.1] Progress: Parameterizing module altpll_0 -Progress: Adding clk_50 [clock_source 16.0] +Progress: Adding clk_50 [clock_source 16.1] Progress: Parameterizing module clk_50 Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_camera Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_mipi -Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] +Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Parameterizing module jtag_uart -Progress: Adding key [altera_avalon_pio 16.0] +Progress: Adding key [altera_avalon_pio 16.1] Progress: Parameterizing module key -Progress: Adding led [altera_avalon_pio 16.0] +Progress: Adding led [altera_avalon_pio 16.1] Progress: Parameterizing module led -Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] +Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_pwdn_n -Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] +Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_reset_n -Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] +Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Parameterizing module nios2_gen2 -Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] +Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Parameterizing module onchip_memory2_0 -Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] +Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Parameterizing module sdram -Progress: Adding sw [altera_avalon_pio 16.0] +Progress: Adding sw [altera_avalon_pio 16.1] Progress: Parameterizing module sw -Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] +Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Parameterizing module sysid_qsys -Progress: Adding timer [altera_avalon_timer 16.0] +Progress: Adding timer [altera_avalon_timer 16.1] Progress: Parameterizing module timer +Progress: Adding uart_interface_0 [uart_interface 1.0] +Progress: Parameterizing module uart_interface_0 Progress: Building connections Progress: Parameterizing connections Progress: Validating @@ -47,6 +51,7 @@ Progress: Done reading input file Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. @@ -54,9 +59,11 @@ Info: qsys-generate succeeded. Info: Finished: Create block symbol file (.bsf) Info: Info: Starting: Create HDL design files for synthesis -Info: qsys-generate /home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys.qsys --synthesis=VERILOG --output-directory=/home/ed/stuff/EEE2Rover/DE10_LITE_D8M_VIP_16/Qsys/synthesis --family="MAX 10" --part=10M50DAF484C7G +Info: qsys-generate "C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys.qsys" --synthesis=VERILOG --output-directory="C:\Users\Anish Ghanekar\OneDrive - Imperial College London\GitHub\EE2Rover\Vision\DE10_LITE_D8M_VIP_16\Qsys\synthesis" --family="MAX 10" --part=10M50DAF484C7G Progress: Loading DE10_LITE_D8M_VIP_16/Qsys.qsys Progress: Reading input file +Progress: Adding EEE_IMGPROC_0 [EEE_IMGPROC 1.0] +Progress: Parameterizing module EEE_IMGPROC_0 Progress: Adding TERASIC_AUTO_FOCUS_0 [TERASIC_AUTO_FOCUS 1.0] Progress: Parameterizing module TERASIC_AUTO_FOCUS_0 Progress: Adding TERASIC_CAMERA_0 [TERASIC_CAMERA 1.0] @@ -65,36 +72,38 @@ Progress: Adding alt_vip_itc_0 [alt_vip_itc 14.0] Progress: Parameterizing module alt_vip_itc_0 Progress: Adding alt_vip_vfb_0 [alt_vip_vfb 13.1] Progress: Parameterizing module alt_vip_vfb_0 -Progress: Adding altpll_0 [altpll 16.0] +Progress: Adding altpll_0 [altpll 16.1] Progress: Parameterizing module altpll_0 -Progress: Adding clk_50 [clock_source 16.0] +Progress: Adding clk_50 [clock_source 16.1] Progress: Parameterizing module clk_50 Progress: Adding i2c_opencores_camera [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_camera Progress: Adding i2c_opencores_mipi [i2c_opencores 12.0] Progress: Parameterizing module i2c_opencores_mipi -Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.0] +Progress: Adding jtag_uart [altera_avalon_jtag_uart 16.1] Progress: Parameterizing module jtag_uart -Progress: Adding key [altera_avalon_pio 16.0] +Progress: Adding key [altera_avalon_pio 16.1] Progress: Parameterizing module key -Progress: Adding led [altera_avalon_pio 16.0] +Progress: Adding led [altera_avalon_pio 16.1] Progress: Parameterizing module led -Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.0] +Progress: Adding mipi_pwdn_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_pwdn_n -Progress: Adding mipi_reset_n [altera_avalon_pio 16.0] +Progress: Adding mipi_reset_n [altera_avalon_pio 16.1] Progress: Parameterizing module mipi_reset_n -Progress: Adding nios2_gen2 [altera_nios2_gen2 16.0] +Progress: Adding nios2_gen2 [altera_nios2_gen2 16.1] Progress: Parameterizing module nios2_gen2 -Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.0] +Progress: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 16.1] Progress: Parameterizing module onchip_memory2_0 -Progress: Adding sdram [altera_avalon_new_sdram_controller 16.0] +Progress: Adding sdram [altera_avalon_new_sdram_controller 16.1] Progress: Parameterizing module sdram -Progress: Adding sw [altera_avalon_pio 16.0] +Progress: Adding sw [altera_avalon_pio 16.1] Progress: Parameterizing module sw -Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.0] +Progress: Adding sysid_qsys [altera_avalon_sysid_qsys 16.1] Progress: Parameterizing module sysid_qsys -Progress: Adding timer [altera_avalon_timer 16.0] +Progress: Adding timer [altera_avalon_timer 16.1] Progress: Parameterizing module timer +Progress: Adding uart_interface_0 [uart_interface 1.0] +Progress: Parameterizing module uart_interface_0 Progress: Building connections Progress: Parameterizing connections Progress: Validating @@ -102,28 +111,168 @@ Progress: Done reading input file Info: Qsys.alt_vip_vfb_0: The Frame Buffer will no longer be available after 16.1, please upgrade to Frame Buffer II. Info: Qsys.jtag_uart: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board Info: Qsys.key: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. +Info: Qsys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release. Info: Qsys.sw: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. Info: Qsys.sysid_qsys: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID Info: Qsys.sysid_qsys: Time stamp will be automatically updated when this component is generated. Info: Qsys: Generating Qsys "Qsys" for QUARTUS_SYNTH Info: Inserting clock-crossing logic between cmd_demux.src5 and cmd_mux_005.sink0 +Info: Inserting clock-crossing logic between cmd_demux.src14 and cmd_mux_014.sink0 Info: Inserting clock-crossing logic between rsp_demux_005.src0 and rsp_mux.sink5 +Info: Inserting clock-crossing logic between rsp_demux_014.src0 and rsp_mux.sink14 +Info: EEE_IMGPROC_0: "Qsys" instantiated EEE_IMGPROC "EEE_IMGPROC_0" Info: TERASIC_AUTO_FOCUS_0: "Qsys" instantiated TERASIC_AUTO_FOCUS "TERASIC_AUTO_FOCUS_0" Info: TERASIC_CAMERA_0: "Qsys" instantiated TERASIC_CAMERA "TERASIC_CAMERA_0" Info: alt_vip_itc_0: "Qsys" instantiated alt_vip_itc "alt_vip_itc_0" Info: alt_vip_vfb_0: "Qsys" instantiated alt_vip_vfb "alt_vip_vfb_0" -Info: altpll_0: Error while generating Qsys_altpll_0.v : 1 : Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally -Info: altpll_0: Illegal port or parameter name scandone Illegal port or parameter name scanclkena Illegal port or parameter name scandataout Illegal port or parameter name configupdate Illegal port or parameter name scandata child process exited abnormally while executing "exec /home/ed/altera_lite/16.0/quartus/linux64/clearbox altpll_avalon device_family=MAX10 CBX_FILE=Qsys_altpll_0.v -f cbxcmdln_1617092145442977" ("eval" body line 1) invoked from within "eval exec $cbx_cmd " -Error: Can't continue processing -- expected file /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v is missing -Warning: Quartus Prime Generate HDL Interface was unsuccessful. 1 error, 0 warnings -Error: Peak virtual memory: 1399 megabytes -Error: Processing ended: Tue Mar 30 09:15:46 2021 -Error: Elapsed time: 00:00:00 -Error: Total CPU time (on all processors): 00:00:00 -Error: altpll_0: File /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v written by generation callback did not contain a module called Qsys_altpll_0 -Error: altpll_0: /tmp/alt8716_2763057626446894966.dir/0014_sopcgen/Qsys_altpll_0.v (No such file or directory) Info: altpll_0: "Qsys" instantiated altpll "altpll_0" -Error: Generation stopped, 218 or more modules remaining -Info: Qsys: Done "Qsys" with 33 modules, 34 files -Error: qsys-generate failed with exit code 1: 8 Errors, 1 Warning +Info: i2c_opencores_camera: "Qsys" instantiated i2c_opencores "i2c_opencores_camera" +Info: jtag_uart: Starting RTL generation for module 'Qsys_jtag_uart' +Info: jtag_uart: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=Qsys_jtag_uart --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0012_jtag_uart_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0012_jtag_uart_gen//Qsys_jtag_uart_component_configuration.pl --do_build_sim=0 ] +Info: jtag_uart: Done RTL generation for module 'Qsys_jtag_uart' +Info: jtag_uart: "Qsys" instantiated altera_avalon_jtag_uart "jtag_uart" +Info: key: Starting RTL generation for module 'Qsys_key' +Info: key: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_key --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0013_key_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0013_key_gen//Qsys_key_component_configuration.pl --do_build_sim=0 ] +Info: key: Done RTL generation for module 'Qsys_key' +Info: key: "Qsys" instantiated altera_avalon_pio "key" +Info: led: Starting RTL generation for module 'Qsys_led' +Info: led: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_led --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0014_led_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0014_led_gen//Qsys_led_component_configuration.pl --do_build_sim=0 ] +Info: led: Done RTL generation for module 'Qsys_led' +Info: led: "Qsys" instantiated altera_avalon_pio "led" +Info: mipi_pwdn_n: Starting RTL generation for module 'Qsys_mipi_pwdn_n' +Info: mipi_pwdn_n: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_mipi_pwdn_n --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0015_mipi_pwdn_n_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0015_mipi_pwdn_n_gen//Qsys_mipi_pwdn_n_component_configuration.pl --do_build_sim=0 ] +Info: mipi_pwdn_n: Done RTL generation for module 'Qsys_mipi_pwdn_n' +Info: mipi_pwdn_n: "Qsys" instantiated altera_avalon_pio "mipi_pwdn_n" +Info: nios2_gen2: "Qsys" instantiated altera_nios2_gen2 "nios2_gen2" +Info: onchip_memory2_0: Starting RTL generation for module 'Qsys_onchip_memory2_0' +Info: onchip_memory2_0: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=Qsys_onchip_memory2_0 --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0016_onchip_memory2_0_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0016_onchip_memory2_0_gen//Qsys_onchip_memory2_0_component_configuration.pl --do_build_sim=0 ] +Info: onchip_memory2_0: Done RTL generation for module 'Qsys_onchip_memory2_0' +Info: onchip_memory2_0: "Qsys" instantiated altera_avalon_onchip_memory2 "onchip_memory2_0" +Info: sdram: Starting RTL generation for module 'Qsys_sdram' +Info: sdram: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_new_sdram_controller/generate_rtl.pl --name=Qsys_sdram --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0017_sdram_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0017_sdram_gen//Qsys_sdram_component_configuration.pl --do_build_sim=0 ] +Info: sdram: Done RTL generation for module 'Qsys_sdram' +Info: sdram: "Qsys" instantiated altera_avalon_new_sdram_controller "sdram" +Info: sw: Starting RTL generation for module 'Qsys_sw' +Info: sw: Generation command is [exec C:/intelfpga_lite/16.1/quartus/bin64/perl/bin/perl.exe -I C:/intelfpga_lite/16.1/quartus/bin64/perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=Qsys_sw --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0018_sw_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0018_sw_gen//Qsys_sw_component_configuration.pl --do_build_sim=0 ] +Info: sw: Done RTL generation for module 'Qsys_sw' +Info: sw: "Qsys" instantiated altera_avalon_pio "sw" +Info: sysid_qsys: "Qsys" instantiated altera_avalon_sysid_qsys "sysid_qsys" +Info: timer: Starting RTL generation for module 'Qsys_timer' +Info: timer: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//perl/bin/perl.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/common -I C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- C:/intelfpga_lite/16.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=Qsys_timer --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0020_timer_gen/ --quartus_dir=C:/intelfpga_lite/16.1/quartus --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0020_timer_gen//Qsys_timer_component_configuration.pl --do_build_sim=0 ] +Info: timer: Done RTL generation for module 'Qsys_timer' +Info: timer: "Qsys" instantiated altera_avalon_timer "timer" +Info: uart_interface_0: "Qsys" instantiated uart_interface "uart_interface_0" +Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0 +Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0 +Info: mm_interconnect_0: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_0" +Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0 +Info: mm_interconnect_1: "Qsys" instantiated altera_mm_interconnect "mm_interconnect_1" +Info: irq_mapper: "Qsys" instantiated altera_irq_mapper "irq_mapper" +Info: rst_controller: "Qsys" instantiated altera_reset_controller "rst_controller" +Info: vfb_writer_packet_write_address_au_l_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxbin2 "vfb_writer_packet_write_address_au_l_muxinst" +Info: vfb_writer_packet_write_address_au: "alt_vip_vfb_0" instantiated alt_au "vfb_writer_packet_write_address_au" +Info: vfb_writer_overflow_flag_reg: "alt_vip_vfb_0" instantiated alt_reg "vfb_writer_overflow_flag_reg" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: vfb_writer_length_counter_au_enable_muxinst: "alt_vip_vfb_0" instantiated alt_cusp_muxhot16 "vfb_writer_length_counter_au_enable_muxinst" +Info: din: "alt_vip_vfb_0" instantiated alt_avalon_st_input "din" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: dout: "alt_vip_vfb_0" instantiated alt_avalon_st_output "dout" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: read_master: "alt_vip_vfb_0" instantiated alt_avalon_mm_bursting_master_fifo "read_master" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: read_master_pull: "alt_vip_vfb_0" instantiated alt_cusp_pulling_width_adapter "read_master_pull" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: write_master_push: "alt_vip_vfb_0" instantiated alt_cusp_pushing_width_adapter "write_master_push" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: pc0: "alt_vip_vfb_0" instantiated alt_pc "pc0" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: fu_id_4494_line325_93: "alt_vip_vfb_0" instantiated alt_cmp "fu_id_4494_line325_93" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: clocksource: "alt_vip_vfb_0" instantiated alt_cusp_testbench_clock "clocksource" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/alt_cusp161_package.vhd +Info: cpu: Starting RTL generation for module 'Qsys_nios2_gen2_cpu' +Info: cpu: Generation command is [exec C:/intelFPGA_lite/16.1/quartus/bin64//eperlcmd.exe -I C:/intelFPGA_lite/16.1/quartus/bin64//perl/lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/europa -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin/perl_lib -I C:/intelfpga_lite/16.1/quartus/sopc_builder/bin -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- C:/intelfpga_lite/16.1/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=Qsys_nios2_gen2_cpu --dir=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0024_cpu_gen/ --quartus_bindir=C:/intelFPGA_lite/16.1/quartus/bin64/ --verilog --config=C:/Users/ANISHG~1/AppData/Local/Temp/alt8774_8656851003626341876.dir/0024_cpu_gen//Qsys_nios2_gen2_cpu_processor_configuration.pl --do_build_sim=0 ] +Info: cpu: # 2021.05.27 17:14:55 (*) Starting Nios II generation +Info: cpu: # 2021.05.27 17:14:55 (*) Checking for plaintext license. +Info: cpu: # 2021.05.27 17:14:55 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ +Info: cpu: # 2021.05.27 17:14:55 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2021.05.27 17:14:55 (*) LM_LICENSE_FILE environment variable is empty +Info: cpu: # 2021.05.27 17:14:55 (*) Plaintext license not found. +Info: cpu: # 2021.05.27 17:14:55 (*) Checking for encrypted license (non-evaluation). +Info: cpu: # 2021.05.27 17:14:56 (*) Couldn't query license setup in Quartus directory C:/intelFPGA_lite/16.1/quartus/bin64/ +Info: cpu: # 2021.05.27 17:14:56 (*) Defaulting to contents of LM_LICENSE_FILE environment variable +Info: cpu: # 2021.05.27 17:14:56 (*) LM_LICENSE_FILE environment variable is empty +Info: cpu: # 2021.05.27 17:14:56 (*) Encrypted license not found. Defaulting to OCP evaluation license (produces a time-limited SOF) +Info: cpu: # 2021.05.27 17:14:56 (*) Elaborating CPU configuration settings +Info: cpu: # 2021.05.27 17:14:56 (*) Creating all objects for CPU +Info: cpu: # 2021.05.27 17:14:56 (*) Testbench +Info: cpu: # 2021.05.27 17:14:56 (*) Instruction decoding +Info: cpu: # 2021.05.27 17:14:56 (*) Instruction fields +Info: cpu: # 2021.05.27 17:14:56 (*) Instruction decodes +Info: cpu: # 2021.05.27 17:14:57 (*) Signals for RTL simulation waveforms +Info: cpu: # 2021.05.27 17:14:57 (*) Instruction controls +Info: cpu: # 2021.05.27 17:14:57 (*) Pipeline frontend +Info: cpu: # 2021.05.27 17:14:57 (*) Pipeline backend +Info: cpu: # 2021.05.27 17:14:59 (*) Generating RTL from CPU objects +Info: cpu: # 2021.05.27 17:15:00 (*) Creating encrypted RTL +Info: cpu: # 2021.05.27 17:15:01 (*) Done Nios II generation +Info: cpu: Done RTL generation for module 'Qsys_nios2_gen2_cpu' +Info: cpu: "nios2_gen2" instantiated altera_nios2_gen2_unit "cpu" +Info: nios2_gen2_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_gen2_data_master_translator" +Info: jtag_uart_avalon_jtag_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "jtag_uart_avalon_jtag_slave_translator" +Info: nios2_gen2_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_gen2_data_master_agent" +Info: jtag_uart_avalon_jtag_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "jtag_uart_avalon_jtag_slave_agent" +Info: jtag_uart_avalon_jtag_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "jtag_uart_avalon_jtag_slave_agent_rsp_fifo" +Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router" +Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001" +Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002" +Info: router_006: "mm_interconnect_0" instantiated altera_merlin_router "router_006" +Info: nios2_gen2_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_gen2_data_master_limiter" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_sc_fifo.v +Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux" +Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001" +Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux" +Info: cmd_mux_004: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_004" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux" +Info: rsp_demux_004: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_004" +Info: rsp_demux_005: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_005" +Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v +Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter" +Info: router: "mm_interconnect_1" instantiated altera_merlin_router "router" +Info: router_002: "mm_interconnect_1" instantiated altera_merlin_router "router_002" +Info: sdram_s1_burst_adapter: "mm_interconnect_1" instantiated altera_merlin_burst_adapter "sdram_s1_burst_adapter" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_avalon_st_pipeline_base.v +Info: cmd_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "cmd_demux" +Info: cmd_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "cmd_mux" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: rsp_demux: "mm_interconnect_1" instantiated altera_merlin_demultiplexer "rsp_demux" +Info: rsp_mux: "mm_interconnect_1" instantiated altera_merlin_multiplexer "rsp_mux" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_arbitrator.sv +Info: sdram_s1_rsp_width_adapter: "mm_interconnect_1" instantiated altera_merlin_width_adapter "sdram_s1_rsp_width_adapter" +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_address_alignment.sv +Info: Reusing file C:/Users/Anish Ghanekar/OneDrive - Imperial College London/GitHub/EE2Rover/Vision/DE10_LITE_D8M_VIP_16/Qsys/synthesis/submodules/altera_merlin_burst_uncompressor.sv +Info: avalon_st_adapter: "mm_interconnect_1" instantiated altera_avalon_st_adapter "avalon_st_adapter" +Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" +Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0" +Info: Qsys: Done "Qsys" with 68 modules, 143 files +Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis diff --git a/Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v b/Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v index 5d55bda..13f2d0f 100644 --- a/Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v +++ b/Vision/DE10_LITE_D8M_VIP_16/ip/EEE_IMGPROC/EEE_IMGPROC.v @@ -72,13 +72,25 @@ parameter BB_COL_DEFAULT = 24'h00ff00; wire [7:0] red, green, blue, grey; wire [7:0] red_out, green_out, blue_out; +wire [8:0] hue; +wire [7:0] saturation, value; wire sop, eop, in_valid, out_ready; //////////////////////////////////////////////////////////////////////// +// RGB --> HSV Conversion +wire [7:0] min, max, delta; +assign min = (red < green) ? ((red < blue) ? red : blue) : ((green < blue) ? green : blue); +assign max = (red > green) ? ((red > blue) ? red : blue) : ((green > blue) ? green : blue); +assign delta = max - min; +assign hue = (red == max) ? (green - blue)/delta : ((green == max) ? 8'h55+((blue - red)/delta) : 8'haa+((red - green)/delta)); +assign saturation = (max == 8'h00) ? 8'h00 : delta / max; +assign value = max; + // Detect red areas wire red_detect; -assign red_detect = red[7] & ~green[7] & ~blue[7]; +//assign red_detect = red[7] & ~green[7] & ~blue[7]; +assign red_detect = blue[7]; // Find boundary of cursor box diff --git a/Vision/DE10_LITE_D8M_VIP_16/uart_interface_hw.tcl b/Vision/DE10_LITE_D8M_VIP_16/uart_interface_hw.tcl new file mode 100644 index 0000000..367e37d --- /dev/null +++ b/Vision/DE10_LITE_D8M_VIP_16/uart_interface_hw.tcl @@ -0,0 +1,115 @@ +# TCL File Generated by Component Editor 16.1 +# Thu May 27 17:12:45 BST 2021 +# DO NOT MODIFY + + +# +# uart_interface "uart_interface" v1.0 +# 2021.05.27.17:12:45 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module uart_interface +# +set_module_property DESCRIPTION "" +set_module_property NAME uart_interface +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME uart_interface +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL uart +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file uart.v VERILOG PATH ip/de10lite-hdl/uart.v TOP_LEVEL_FILE + + +# +# parameters +# +add_parameter CLK_FREQ INTEGER 50000000 +set_parameter_property CLK_FREQ DEFAULT_VALUE 50000000 +set_parameter_property CLK_FREQ DISPLAY_NAME CLK_FREQ +set_parameter_property CLK_FREQ TYPE INTEGER +set_parameter_property CLK_FREQ UNITS None +set_parameter_property CLK_FREQ HDL_PARAMETER true +add_parameter BAUD INTEGER 115200 +set_parameter_property BAUD DEFAULT_VALUE 115200 +set_parameter_property BAUD DISPLAY_NAME BAUD +set_parameter_property BAUD TYPE INTEGER +set_parameter_property BAUD UNITS None +set_parameter_property BAUD HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset reset reset Input 1 + + +# +# connection point conduit_end +# +add_interface conduit_end conduit end +set_interface_property conduit_end associatedClock clock +set_interface_property conduit_end associatedReset "" +set_interface_property conduit_end ENABLED true +set_interface_property conduit_end EXPORT_OF "" +set_interface_property conduit_end PORT_NAME_MAP "" +set_interface_property conduit_end CMSIS_SVD_VARIABLES "" +set_interface_property conduit_end SVD_ADDRESS_GROUP "" + +add_interface_port conduit_end rx rx Input 1 +add_interface_port conduit_end rx_data rx_data Output 8 +add_interface_port conduit_end rx_valid rx_valid Output 1 +add_interface_port conduit_end tx tx Output 1 +add_interface_port conduit_end tx_data tx_data Input 8 +add_interface_port conduit_end tx_transmit tx_transmit Input 1 +add_interface_port conduit_end tx_ready tx_ready Output 1 +