2021-05-18 11:20:27 +00:00
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component Qsys is
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port (
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alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
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alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(23 downto 0); -- vid_data
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alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
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alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
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alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
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alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
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alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
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alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
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alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
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altpll_0_areset_conduit_export : in std_logic := 'X'; -- export
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altpll_0_locked_conduit_export : out std_logic; -- export
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clk_clk : in std_logic := 'X'; -- clk
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clk_sdram_clk : out std_logic; -- clk
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clk_vga_clk : out std_logic; -- clk
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d8m_xclkin_clk : out std_logic; -- clk
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eee_imgproc_0_conduit_mode_new_signal : in std_logic := 'X'; -- new_signal
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i2c_opencores_camera_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
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i2c_opencores_camera_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
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i2c_opencores_mipi_export_scl_pad_io : inout std_logic := 'X'; -- scl_pad_io
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i2c_opencores_mipi_export_sda_pad_io : inout std_logic := 'X'; -- sda_pad_io
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key_external_connection_export : in std_logic_vector(1 downto 0) := (others => 'X'); -- export
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led_external_connection_export : out std_logic_vector(9 downto 0); -- export
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mipi_pwdn_n_external_connection_export : out std_logic; -- export
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mipi_reset_n_external_connection_export : out std_logic; -- export
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reset_reset_n : in std_logic := 'X'; -- reset_n
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sdram_wire_addr : out std_logic_vector(12 downto 0); -- addr
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sdram_wire_ba : out std_logic_vector(1 downto 0); -- ba
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sdram_wire_cas_n : out std_logic; -- cas_n
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sdram_wire_cke : out std_logic; -- cke
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sdram_wire_cs_n : out std_logic; -- cs_n
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sdram_wire_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- dq
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sdram_wire_dqm : out std_logic_vector(1 downto 0); -- dqm
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sdram_wire_ras_n : out std_logic; -- ras_n
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sdram_wire_we_n : out std_logic; -- we_n
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sw_external_connection_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
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terasic_auto_focus_0_conduit_vcm_i2c_sda : inout std_logic := 'X'; -- vcm_i2c_sda
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terasic_auto_focus_0_conduit_clk50 : in std_logic := 'X'; -- clk50
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terasic_auto_focus_0_conduit_vcm_i2c_scl : inout std_logic := 'X'; -- vcm_i2c_scl
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terasic_camera_0_conduit_end_D : in std_logic_vector(11 downto 0) := (others => 'X'); -- D
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terasic_camera_0_conduit_end_FVAL : in std_logic := 'X'; -- FVAL
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terasic_camera_0_conduit_end_LVAL : in std_logic := 'X'; -- LVAL
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2021-06-08 18:07:13 +00:00
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terasic_camera_0_conduit_end_PIXCLK : in std_logic := 'X'; -- PIXCLK
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uart_0_rx_tx_rxd : in std_logic := 'X'; -- rxd
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uart_0_rx_tx_txd : out std_logic -- txd
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2021-05-18 11:20:27 +00:00
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);
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end component Qsys;
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u0 : component Qsys
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port map (
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alt_vip_itc_0_clocked_video_vid_clk => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_clk, -- alt_vip_itc_0_clocked_video.vid_clk
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alt_vip_itc_0_clocked_video_vid_data => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_data, -- .vid_data
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alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_alt_vip_itc_0_clocked_video_underflow, -- .underflow
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alt_vip_itc_0_clocked_video_vid_datavalid => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_datavalid, -- .vid_datavalid
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alt_vip_itc_0_clocked_video_vid_v_sync => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_v_sync, -- .vid_v_sync
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alt_vip_itc_0_clocked_video_vid_h_sync => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_h_sync, -- .vid_h_sync
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alt_vip_itc_0_clocked_video_vid_f => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_f, -- .vid_f
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alt_vip_itc_0_clocked_video_vid_h => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_h, -- .vid_h
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alt_vip_itc_0_clocked_video_vid_v => CONNECTED_TO_alt_vip_itc_0_clocked_video_vid_v, -- .vid_v
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altpll_0_areset_conduit_export => CONNECTED_TO_altpll_0_areset_conduit_export, -- altpll_0_areset_conduit.export
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altpll_0_locked_conduit_export => CONNECTED_TO_altpll_0_locked_conduit_export, -- altpll_0_locked_conduit.export
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clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
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clk_sdram_clk => CONNECTED_TO_clk_sdram_clk, -- clk_sdram.clk
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clk_vga_clk => CONNECTED_TO_clk_vga_clk, -- clk_vga.clk
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d8m_xclkin_clk => CONNECTED_TO_d8m_xclkin_clk, -- d8m_xclkin.clk
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eee_imgproc_0_conduit_mode_new_signal => CONNECTED_TO_eee_imgproc_0_conduit_mode_new_signal, -- eee_imgproc_0_conduit_mode.new_signal
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i2c_opencores_camera_export_scl_pad_io => CONNECTED_TO_i2c_opencores_camera_export_scl_pad_io, -- i2c_opencores_camera_export.scl_pad_io
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i2c_opencores_camera_export_sda_pad_io => CONNECTED_TO_i2c_opencores_camera_export_sda_pad_io, -- .sda_pad_io
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i2c_opencores_mipi_export_scl_pad_io => CONNECTED_TO_i2c_opencores_mipi_export_scl_pad_io, -- i2c_opencores_mipi_export.scl_pad_io
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i2c_opencores_mipi_export_sda_pad_io => CONNECTED_TO_i2c_opencores_mipi_export_sda_pad_io, -- .sda_pad_io
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key_external_connection_export => CONNECTED_TO_key_external_connection_export, -- key_external_connection.export
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led_external_connection_export => CONNECTED_TO_led_external_connection_export, -- led_external_connection.export
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mipi_pwdn_n_external_connection_export => CONNECTED_TO_mipi_pwdn_n_external_connection_export, -- mipi_pwdn_n_external_connection.export
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mipi_reset_n_external_connection_export => CONNECTED_TO_mipi_reset_n_external_connection_export, -- mipi_reset_n_external_connection.export
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reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
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sdram_wire_addr => CONNECTED_TO_sdram_wire_addr, -- sdram_wire.addr
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sdram_wire_ba => CONNECTED_TO_sdram_wire_ba, -- .ba
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sdram_wire_cas_n => CONNECTED_TO_sdram_wire_cas_n, -- .cas_n
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sdram_wire_cke => CONNECTED_TO_sdram_wire_cke, -- .cke
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sdram_wire_cs_n => CONNECTED_TO_sdram_wire_cs_n, -- .cs_n
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sdram_wire_dq => CONNECTED_TO_sdram_wire_dq, -- .dq
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sdram_wire_dqm => CONNECTED_TO_sdram_wire_dqm, -- .dqm
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sdram_wire_ras_n => CONNECTED_TO_sdram_wire_ras_n, -- .ras_n
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sdram_wire_we_n => CONNECTED_TO_sdram_wire_we_n, -- .we_n
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sw_external_connection_export => CONNECTED_TO_sw_external_connection_export, -- sw_external_connection.export
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terasic_auto_focus_0_conduit_vcm_i2c_sda => CONNECTED_TO_terasic_auto_focus_0_conduit_vcm_i2c_sda, -- terasic_auto_focus_0_conduit.vcm_i2c_sda
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terasic_auto_focus_0_conduit_clk50 => CONNECTED_TO_terasic_auto_focus_0_conduit_clk50, -- .clk50
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terasic_auto_focus_0_conduit_vcm_i2c_scl => CONNECTED_TO_terasic_auto_focus_0_conduit_vcm_i2c_scl, -- .vcm_i2c_scl
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terasic_camera_0_conduit_end_D => CONNECTED_TO_terasic_camera_0_conduit_end_D, -- terasic_camera_0_conduit_end.D
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terasic_camera_0_conduit_end_FVAL => CONNECTED_TO_terasic_camera_0_conduit_end_FVAL, -- .FVAL
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terasic_camera_0_conduit_end_LVAL => CONNECTED_TO_terasic_camera_0_conduit_end_LVAL, -- .LVAL
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2021-06-08 18:07:13 +00:00
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terasic_camera_0_conduit_end_PIXCLK => CONNECTED_TO_terasic_camera_0_conduit_end_PIXCLK, -- .PIXCLK
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uart_0_rx_tx_rxd => CONNECTED_TO_uart_0_rx_tx_rxd, -- uart_0_rx_tx.rxd
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uart_0_rx_tx_txd => CONNECTED_TO_uart_0_rx_tx_txd -- .txd
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2021-05-18 11:20:27 +00:00
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);
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