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ELEC50003-P1-CW/Vision/DE10_LITE_D8M_VIP_16/Qsys.qsys

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<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element EEE_IMGPROC_0
{
datum _sortIndex
{
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value = "18";
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type = "int";
}
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datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
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}
element Qsys
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element Qsys
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element Qsys
{
datum _originalDeviceFamily
{
value = "Cyclone V";
type = "String";
}
}
element TERASIC_AUTO_FOCUS_0
{
datum _sortIndex
{
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value = "17";
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type = "int";
}
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datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
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}
element TERASIC_AUTO_FOCUS_0.mm_ctrl
{
datum baseAddress
{
value = "266272";
type = "String";
}
}
element TERASIC_CAMERA_0
{
datum _sortIndex
{
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value = "14";
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type = "int";
}
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datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
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}
element alt_vip_itc_0
{
datum _sortIndex
{
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value = "19";
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type = "int";
}
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datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
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}
element alt_vip_vfb_0
{
datum _sortIndex
{
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value = "16";
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type = "int";
}
datum megawizard_uipreferences
{
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value = "{output_directory=F:\\Ed\\Stuff\\EEE2Rover\\DE10_LITE_D8M_VIP_16, output_language=VERILOG}";
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type = "String";
}
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datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
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}
element altpll_0
{
datum _sortIndex
{
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value = "20";
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type = "int";
}
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datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
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}
element altpll_0.pll_slave
{
datum baseAddress
{
value = "266448";
type = "String";
}
}
element clk_50
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element i2c_opencores_camera
{
datum _sortIndex
{
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value = "6";
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type = "int";
}
}
element i2c_opencores_camera.avalon_slave_0
{
datum baseAddress
{
value = "266304";
type = "String";
}
}
element i2c_opencores_mipi
{
datum _sortIndex
{
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value = "5";
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type = "int";
}
}
element i2c_opencores_mipi.avalon_slave_0
{
datum baseAddress
{
value = "266336";
type = "String";
}
}
element jtag_uart
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element jtag_uart.avalon_jtag_slave
{
datum baseAddress
{
value = "266472";
type = "String";
}
}
element key
{
datum _sortIndex
{
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value = "9";
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type = "int";
}
}
element key.s1
{
datum baseAddress
{
value = "266400";
type = "String";
}
}
element led
{
datum _sortIndex
{
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value = "7";
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type = "int";
}
}
element led.s1
{
datum baseAddress
{
value = "266432";
type = "String";
}
}
element mipi_pwdn_n
{
datum _sortIndex
{
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value = "11";
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type = "int";
}
}
element mipi_pwdn_n.s1
{
datum baseAddress
{
value = "266368";
type = "String";
}
}
element mipi_reset_n
{
datum _sortIndex
{
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value = "10";
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type = "int";
}
}
element mipi_reset_n.s1
{
datum baseAddress
{
value = "266384";
type = "String";
}
}
element nios2_gen2
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element nios2_gen2.debug_mem_slave
{
datum baseAddress
{
value = "264192";
type = "String";
}
}
element onchip_memory2_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element onchip_memory2_0.s1
{
datum baseAddress
{
value = "131072";
type = "String";
}
}
element sdram
{
datum _sortIndex
{
value = "15";
type = "int";
}
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datum sopceditor_expanded
{
value = "0";
type = "boolean";
}
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}
element sdram.s1
{
datum baseAddress
{
value = "67108864";
type = "String";
}
}
element sw
{
datum _sortIndex
{
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value = "8";
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type = "int";
}
}
element sw.s1
{
datum baseAddress
{
value = "266416";
type = "String";
}
}
element sysid_qsys
{
datum _sortIndex
{
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value = "12";
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type = "int";
}
}
element sysid_qsys.control_slave
{
datum baseAddress
{
value = "266464";
type = "String";
}
}
element timer
{
datum _sortIndex
{
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value = "13";
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type = "int";
}
}
element timer.s1
{
datum baseAddress
{
value = "266240";
type = "String";
}
}
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element uart_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
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}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="10M50DAF484C7G" />
<parameter name="deviceFamily" value="MAX 10" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName">DE10_LITE_D8M_VIP.qpf</parameter>
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
name="alt_vip_itc_0_clocked_video"
internal="alt_vip_itc_0.clocked_video"
type="conduit"
dir="end" />
<interface
name="altpll_0_areset_conduit"
internal="altpll_0.areset_conduit"
type="conduit"
dir="end" />
<interface
name="altpll_0_configupdate_conduit"
internal="altpll_0.configupdate_conduit" />
<interface
name="altpll_0_locked_conduit"
internal="altpll_0.locked_conduit"
type="conduit"
dir="end" />
<interface
name="altpll_0_phasedone_conduit"
internal="altpll_0.phasedone_conduit" />
<interface
name="altpll_0_scanclkena_conduit"
internal="altpll_0.scanclkena_conduit" />
<interface name="altpll_0_scandata_conduit" internal="altpll_0.scandata_conduit" />
<interface
name="altpll_0_scandataout_conduit"
internal="altpll_0.scandataout_conduit" />
<interface name="altpll_0_scandone_conduit" internal="altpll_0.scandone_conduit" />
<interface name="clk" internal="clk_50.clk_in" type="clock" dir="end" />
<interface name="clk_sdram" internal="altpll_0.c1" type="clock" dir="start" />
<interface name="clk_vga" internal="altpll_0.c3" type="clock" dir="start" />
<interface name="d8m_xclkin" internal="altpll_0.c4" type="clock" dir="start" />
<interface
name="eee_imgproc_0_conduit_mode"
internal="EEE_IMGPROC_0.conduit_mode"
type="conduit"
dir="end" />
<interface
name="i2c_opencores_camera_export"
internal="i2c_opencores_camera.export"
type="conduit"
dir="end" />
<interface
name="i2c_opencores_mipi_export"
internal="i2c_opencores_mipi.export"
type="conduit"
dir="end" />
<interface
name="key_external_connection"
internal="key.external_connection"
type="conduit"
dir="end" />
<interface
name="led_external_connection"
internal="led.external_connection"
type="conduit"
dir="end" />
<interface
name="mipi_pwdn_n_external_connection"
internal="mipi_pwdn_n.external_connection"
type="conduit"
dir="end" />
<interface
name="mipi_reset_n_external_connection"
internal="mipi_reset_n.external_connection"
type="conduit"
dir="end" />
<interface name="reset" internal="clk_50.clk_in_reset" type="reset" dir="end" />
<interface name="sdram_wire" internal="sdram.wire" type="conduit" dir="end" />
<interface
name="sw_external_connection"
internal="sw.external_connection"
type="conduit"
dir="end" />
<interface
name="terasic_auto_focus_0_conduit"
internal="TERASIC_AUTO_FOCUS_0.Conduit"
type="conduit"
dir="end" />
<interface
name="terasic_camera_0_conduit_end"
internal="TERASIC_CAMERA_0.conduit_end"
type="conduit"
dir="end" />
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<interface
name="uart_0_rx_tx"
internal="uart_0.external_connection"
type="conduit"
dir="end" />
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<module name="EEE_IMGPROC_0" kind="EEE_IMGPROC" version="1.0" enabled="1" />
<module
name="TERASIC_AUTO_FOCUS_0"
kind="TERASIC_AUTO_FOCUS"
version="1.0"
enabled="1">
<parameter name="VIDEO_H" value="480" />
<parameter name="VIDEO_W" value="640" />
</module>
<module
name="TERASIC_CAMERA_0"
kind="TERASIC_CAMERA"
version="1.0"
enabled="1">
<parameter name="VIDEO_H" value="480" />
<parameter name="VIDEO_W" value="640" />
</module>
<module name="alt_vip_itc_0" kind="alt_vip_itc" version="14.0" enabled="1">
<parameter name="ACCEPT_COLOURS_IN_SEQ" value="0" />
<parameter name="ANC_LINE" value="0" />
<parameter name="AP_LINE" value="0" />
<parameter name="BPS" value="8" />
<parameter name="CLOCKS_ARE_SAME" value="0" />
<parameter name="COLOUR_PLANES_ARE_IN_PARALLEL" value="1" />
<parameter name="FAMILY" value="MAX 10" />
<parameter name="FIELD0_ANC_LINE" value="0" />
<parameter name="FIELD0_V_BACK_PORCH" value="0" />
<parameter name="FIELD0_V_BLANK" value="0" />
<parameter name="FIELD0_V_FRONT_PORCH" value="0" />
<parameter name="FIELD0_V_RISING_EDGE" value="0" />
<parameter name="FIELD0_V_SYNC_LENGTH" value="0" />
<parameter name="FIFO_DEPTH" value="640" />
<parameter name="F_FALLING_EDGE" value="0" />
<parameter name="F_RISING_EDGE" value="0" />
<parameter name="GENERATE_SYNC" value="0" />
<parameter name="H_ACTIVE_PIXELS" value="640" />
<parameter name="H_BACK_PORCH" value="48" />
<parameter name="H_BLANK" value="0" />
<parameter name="H_FRONT_PORCH" value="16" />
<parameter name="H_SYNC_LENGTH" value="96" />
<parameter name="INTERLACED" value="0" />
<parameter name="NO_OF_MODES" value="1" />
<parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
<parameter name="STD_WIDTH" value="1" />
<parameter name="THRESHOLD" value="639" />
<parameter name="USE_CONTROL" value="0" />
<parameter name="USE_EMBEDDED_SYNCS" value="0" />
<parameter name="V_ACTIVE_LINES" value="480" />
<parameter name="V_BACK_PORCH" value="33" />
<parameter name="V_BLANK" value="0" />
<parameter name="V_FRONT_PORCH" value="10" />
<parameter name="V_SYNC_LENGTH" value="2" />
</module>
<module name="alt_vip_vfb_0" kind="alt_vip_vfb" version="13.1" enabled="1">
<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="PARAMETERISATION"><![CDATA[<frameBufferParams><VFB_NAME>MyFrameBuffer</VFB_NAME><VFB_MAX_WIDTH>640</VFB_MAX_WIDTH><VFB_MAX_HEIGHT>480</VFB_MAX_HEIGHT><VFB_BPS>8</VFB_BPS><VFB_CHANNELS_IN_SEQ>1</VFB_CHANNELS_IN_SEQ><VFB_CHANNELS_IN_PAR>3</VFB_CHANNELS_IN_PAR><VFB_WRITER_RUNTIME_CONTROL>false</VFB_WRITER_RUNTIME_CONTROL><VFB_DROP_FRAMES>true</VFB_DROP_FRAMES><VFB_READER_RUNTIME_CONTROL>0</VFB_READER_RUNTIME_CONTROL><VFB_REPEAT_FRAMES>true</VFB_REPEAT_FRAMES><VFB_FRAMEBUFFERS_ADDR>00000000</VFB_FRAMEBUFFERS_ADDR><VFB_MEM_PORT_WIDTH>32</VFB_MEM_PORT_WIDTH><VFB_MEM_MASTERS_USE_SEPARATE_CLOCK>false</VFB_MEM_MASTERS_USE_SEPARATE_CLOCK><VFB_RDATA_FIFO_DEPTH>1024</VFB_RDATA_FIFO_DEPTH><VFB_RDATA_BURST_TARGET>4</VFB_RDATA_BURST_TARGET><VFB_WDATA_FIFO_DEPTH>1024</VFB_WDATA_FIFO_DEPTH><VFB_WDATA_BURST_TARGET>4</VFB_WDATA_BURST_TARGET><VFB_MAX_NUMBER_PACKETS>1</VFB_MAX_NUMBER_PACKETS><VFB_MAX_SYMBOLS_IN_PACKET>10</VFB_MAX_SYMBOLS_IN_PACKET><VFB_INTERLACED_SUPPORT>0</VFB_INTERLACED_SUPPORT><VFB_CONTROLLED_DROP_REPEAT>0</VFB_CONTROLLED_DROP_REPEAT><VFB_BURST_ALIGNMENT>0</VFB_BURST_ALIGNMENT><VFB_DROP_INVALID_FIELDS>false</VFB_DROP_INVALID_FIELDS></frameBufferParams>]]></parameter>
</module>
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<module name="altpll_0" kind="altpll" version="16.1" enabled="1">
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<parameter name="AUTO_DEVICE_FAMILY" value="MAX 10" />
<parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
<parameter name="BANDWIDTH" value="" />
<parameter name="BANDWIDTH_TYPE" value="AUTO" />
<parameter name="CLK0_DIVIDE_BY" value="1" />
<parameter name="CLK0_DUTY_CYCLE" value="50" />
<parameter name="CLK0_MULTIPLY_BY" value="2" />
<parameter name="CLK0_PHASE_SHIFT" value="0" />
<parameter name="CLK1_DIVIDE_BY" value="1" />
<parameter name="CLK1_DUTY_CYCLE" value="50" />
<parameter name="CLK1_MULTIPLY_BY" value="2" />
<parameter name="CLK1_PHASE_SHIFT" value="7500" />
<parameter name="CLK2_DIVIDE_BY" value="1" />
<parameter name="CLK2_DUTY_CYCLE" value="50" />
<parameter name="CLK2_MULTIPLY_BY" value="2" />
<parameter name="CLK2_PHASE_SHIFT" value="0" />
<parameter name="CLK3_DIVIDE_BY" value="2" />
<parameter name="CLK3_DUTY_CYCLE" value="50" />
<parameter name="CLK3_MULTIPLY_BY" value="1" />
<parameter name="CLK3_PHASE_SHIFT" value="0" />
<parameter name="CLK4_DIVIDE_BY" value="5" />
<parameter name="CLK4_DUTY_CYCLE" value="50" />
<parameter name="CLK4_MULTIPLY_BY" value="2" />
<parameter name="CLK4_PHASE_SHIFT" value="0" />
<parameter name="CLK5_DIVIDE_BY" value="" />
<parameter name="CLK5_DUTY_CYCLE" value="" />
<parameter name="CLK5_MULTIPLY_BY" value="" />
<parameter name="CLK5_PHASE_SHIFT" value="" />
<parameter name="CLK6_DIVIDE_BY" value="" />
<parameter name="CLK6_DUTY_CYCLE" value="" />
<parameter name="CLK6_MULTIPLY_BY" value="" />
<parameter name="CLK6_PHASE_SHIFT" value="" />
<parameter name="CLK7_DIVIDE_BY" value="" />
<parameter name="CLK7_DUTY_CYCLE" value="" />
<parameter name="CLK7_MULTIPLY_BY" value="" />
<parameter name="CLK7_PHASE_SHIFT" value="" />
<parameter name="CLK8_DIVIDE_BY" value="" />
<parameter name="CLK8_DUTY_CYCLE" value="" />
<parameter name="CLK8_MULTIPLY_BY" value="" />
<parameter name="CLK8_PHASE_SHIFT" value="" />
<parameter name="CLK9_DIVIDE_BY" value="" />
<parameter name="CLK9_DUTY_CYCLE" value="" />
<parameter name="CLK9_MULTIPLY_BY" value="" />
<parameter name="CLK9_PHASE_SHIFT" value="" />
<parameter name="COMPENSATE_CLOCK" value="CLK0" />
<parameter name="DOWN_SPREAD" value="" />
<parameter name="DPA_DIVIDER" value="" />
<parameter name="DPA_DIVIDE_BY" value="" />
<parameter name="DPA_MULTIPLY_BY" value="" />
<parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
<parameter name="EXTCLK0_DIVIDE_BY" value="" />
<parameter name="EXTCLK0_DUTY_CYCLE" value="" />
<parameter name="EXTCLK0_MULTIPLY_BY" value="" />
<parameter name="EXTCLK0_PHASE_SHIFT" value="" />
<parameter name="EXTCLK1_DIVIDE_BY" value="" />
<parameter name="EXTCLK1_DUTY_CYCLE" value="" />
<parameter name="EXTCLK1_MULTIPLY_BY" value="" />
<parameter name="EXTCLK1_PHASE_SHIFT" value="" />
<parameter name="EXTCLK2_DIVIDE_BY" value="" />
<parameter name="EXTCLK2_DUTY_CYCLE" value="" />
<parameter name="EXTCLK2_MULTIPLY_BY" value="" />
<parameter name="EXTCLK2_PHASE_SHIFT" value="" />
<parameter name="EXTCLK3_DIVIDE_BY" value="" />
<parameter name="EXTCLK3_DUTY_CYCLE" value="" />
<parameter name="EXTCLK3_MULTIPLY_BY" value="" />
<parameter name="EXTCLK3_PHASE_SHIFT" value="" />
<parameter name="FEEDBACK_SOURCE" value="" />
<parameter name="GATE_LOCK_COUNTER" value="" />
<parameter name="GATE_LOCK_SIGNAL" value="" />
<parameter name="HIDDEN_CONSTANTS">CT#CLK2_DIVIDE_BY 1 CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_USED CT#PORT_clk3 PORT_USED CT#PORT_clk2 PORT_USED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#CLK3_DUTY_CYCLE 50 CT#CLK3_DIVIDE_BY 2 CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#CLK3_PHASE_SHIFT 0 CT#PORT_SCANCLKENA PORT_UNUSED CT#CLK4_DIVIDE_BY 5 CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#CLK4_MULTIPLY_BY 2 CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#CLK4_PHASE_SHIFT 0 CT#INCLK0_INPUT_FREQUENCY 20000 CT#CLK4_DUTY_CYCLE 50 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 7500 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#CLK2_MULTIPLY_BY 2 CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#CLK2_DUTY_CYCLE 50 CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK2_PHASE_SHIFT 0 CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#CLK3_MULTIPLY_BY 1 CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
<parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
<parameter name="HIDDEN_IF_PORTS">IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0}</parameter>
<parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
<parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#CLK2_DIVIDE_BY 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK3_DIVIDE_BY 1 IN#CLK4_MULTIPLY_BY 1 IN#CLK1_MULTIPLY_BY 1 IN#CLK3_DUTY_CYCLE 1 IN#CLK4_DIVIDE_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#CLK2_MULTIPLY_BY 1 IN#DIV_FACTOR4 1 IN#DIV_FACTOR3 1 IN#DIV_FACTOR2 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#CLK4_DUTY_CYCLE 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK2_DUTY_CYCLE 1 IN#CLK0_DIVIDE_BY 1 IN#CLK3_MULTIPLY_BY 1 IN#MULT_FACTOR4 1 IN#MULT_FACTOR3 1 IN#MULT_FACTOR2 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
<parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#OUTPUT_FREQ_UNIT4 MHz PT#OUTPUT_FREQ_UNIT3 MHz PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT2 MHz PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#USE_CLK4 1 PT#USE_CLK3 1 PT#USE_CLK2 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#LVDS_PHASE_SHIFT_UNIT4 deg PT#LVDS_PHASE_SHIFT_UNIT3 deg PT#PLL_AUTOPLL_CHECK 1 PT#OUTPUT_FREQ_MODE4 1 PT#LVDS_PHASE_SHIFT_UNIT2 deg PT#OUTPUT_FREQ_MODE3 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#OUTPUT_FREQ_MODE2 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ4 20.00000000 PT#OUTPUT_FREQ3 25.00000000 PT#OUTPUT_FREQ2 100.00000000 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 6 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#PHASE_SHIFT4 0.00000000 PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT3 0.00000000 PT#DIV_FACTOR4 1 PT#PHASE_SHIFT2 0.00000000 PT#DIV_FACTOR3 1 PT#PHASE_SHIFT1 270.00000000 PT#DIV_FACTOR2 1 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA4 0 PT#USE_CLKENA3 0 PT#USE_CLKENA2 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE4 20.000000 PT#EFF_OUTPUT_FREQ_VALUE3 25.000000 PT#EFF_OUTPUT_FREQ_VALUE2 100.000000 PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK4 1 PT#STICKY_CLK3 1 PT#STICKY_CLK2 1 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#MIRROR_CLK4 0 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK3 0 PT#MIRROR_CLK2 0 PT#MIRROR_CLK1 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#MIRROR_CLK0 0 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#CLKLOSS_CHECK 0 PT#PHASE_SHIFT_UNIT4 deg PT#PHASE_SHIFT_UNIT3 deg PT#PHASE_SHIFT_UNIT2 deg PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR4 1 PT#MULT_FACTOR3 1 PT#MULT_FACTOR2 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#DUTY_CYCLE4 50.00000000 PT#DUTY_CYCLE3 50.00000000 PT#DUTY_CYCLE2 50.00000000 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1472001986172141.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c4 used UP#c3 used UP#c2 used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
<parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
<parameter name="INCLK1_INPUT_FREQUENCY" value="" />
<parameter name="INTENDED_DEVICE_FAMILY" value="MAX 10" />
<parameter name="INVALID_LOCK_MULTIPLIER" value="" />
<parameter name="LOCK_HIGH" value="" />
<parameter name="LOCK_LOW" value="" />
<parameter name="OPERATION_MODE" value="NORMAL" />
<parameter name="PLL_TYPE" value="AUTO" />
<parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
<parameter name="PORT_ARESET" value="PORT_USED" />
<parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
<parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
<parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
<parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
<parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
<parameter name="PORT_ENABLE0" value="" />
<parameter name="PORT_ENABLE1" value="" />
<parameter name="PORT_FBIN" value="PORT_UNUSED" />
<parameter name="PORT_FBOUT" value="" />
<parameter name="PORT_INCLK0" value="PORT_USED" />
<parameter name="PORT_INCLK1" value="PORT_UNUSED" />
<parameter name="PORT_LOCKED" value="PORT_USED" />
<parameter name="PORT_PFDENA" value="PORT_UNUSED" />
<parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
<parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
<parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
<parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
<parameter name="PORT_PLLENA" value="PORT_UNUSED" />
<parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
<parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
<parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
<parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
<parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
<parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
<parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
<parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
<parameter name="PORT_SCLKOUT0" value="" />
<parameter name="PORT_SCLKOUT1" value="" />
<parameter name="PORT_VCOOVERRANGE" value="" />
<parameter name="PORT_VCOUNDERRANGE" value="" />
<parameter name="PORT_clk0" value="PORT_USED" />
<parameter name="PORT_clk1" value="PORT_USED" />
<parameter name="PORT_clk2" value="PORT_USED" />
<parameter name="PORT_clk3" value="PORT_USED" />
<parameter name="PORT_clk4" value="PORT_USED" />
<parameter name="PORT_clk5" value="PORT_UNUSED" />
<parameter name="PORT_clk6" value="" />
<parameter name="PORT_clk7" value="" />
<parameter name="PORT_clk8" value="" />
<parameter name="PORT_clk9" value="" />
<parameter name="PORT_clkena0" value="PORT_UNUSED" />
<parameter name="PORT_clkena1" value="PORT_UNUSED" />
<parameter name="PORT_clkena2" value="PORT_UNUSED" />
<parameter name="PORT_clkena3" value="PORT_UNUSED" />
<parameter name="PORT_clkena4" value="PORT_UNUSED" />
<parameter name="PORT_clkena5" value="PORT_UNUSED" />
<parameter name="PORT_extclk0" value="PORT_UNUSED" />
<parameter name="PORT_extclk1" value="PORT_UNUSED" />
<parameter name="PORT_extclk2" value="PORT_UNUSED" />
<parameter name="PORT_extclk3" value="PORT_UNUSED" />
<parameter name="PORT_extclkena0" value="" />
<parameter name="PORT_extclkena1" value="" />
<parameter name="PORT_extclkena2" value="" />
<parameter name="PORT_extclkena3" value="" />
<parameter name="PRIMARY_CLOCK" value="" />
<parameter name="QUALIFY_CONF_DONE" value="" />
<parameter name="SCAN_CHAIN" value="" />
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
<parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
<parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
<parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
<parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
<parameter name="SKIP_VCO" value="" />
<parameter name="SPREAD_FREQUENCY" value="" />
<parameter name="SWITCH_OVER_COUNTER" value="" />
<parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
<parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
<parameter name="SWITCH_OVER_TYPE" value="" />
<parameter name="USING_FBMIMICBIDIR_PORT" value="" />
<parameter name="VALID_LOCK_MULTIPLIER" value="" />
<parameter name="VCO_DIVIDE_BY" value="" />
<parameter name="VCO_FREQUENCY_CONTROL" value="" />
<parameter name="VCO_MULTIPLY_BY" value="" />
<parameter name="VCO_PHASE_SHIFT_STEP" value="" />
<parameter name="WIDTH_CLOCK" value="5" />
<parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
</module>
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<module name="clk_50" kind="clock_source" version="16.1" enabled="1">
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<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
name="i2c_opencores_camera"
kind="i2c_opencores"
version="12.0"
enabled="1" />
<module
name="i2c_opencores_mipi"
kind="i2c_opencores"
version="12.0"
enabled="1" />
<module
name="jtag_uart"
kind="altera_avalon_jtag_uart"
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version="16.1"
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enabled="1">
<parameter name="allowMultipleConnections" value="false" />
<parameter name="avalonSpec" value="2.0" />
<parameter name="clkFreq" value="50000000" />
<parameter name="hubInstanceID" value="0" />
<parameter name="readBufferDepth" value="64" />
<parameter name="readIRQThreshold" value="8" />
<parameter name="simInputCharacterStream" value="" />
<parameter name="simInteractiveOptions">NO_INTERACTIVE_WINDOWS</parameter>
<parameter name="useRegistersForReadBuffer" value="false" />
<parameter name="useRegistersForWriteBuffer" value="false" />
<parameter name="useRelativePathForSimFile" value="false" />
<parameter name="writeBufferDepth" value="64" />
<parameter name="writeIRQThreshold" value="8" />
</module>
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<module name="key" kind="altera_avalon_pio" version="16.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Input" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="2" />
</module>
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<module name="led" kind="altera_avalon_pio" version="16.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="10" />
</module>
<module
name="mipi_pwdn_n"
kind="altera_avalon_pio"
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version="16.1"
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enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="1" />
</module>
<module
name="mipi_reset_n"
kind="altera_avalon_pio"
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version="16.1"
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enabled="1">
<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Output" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="1" />
</module>
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<module name="nios2_gen2" kind="altera_nios2_gen2" version="16.1" enabled="1">
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<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="10M50DAF484C7G" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave" value="None" />
<parameter name="cdx_enabled" value="false" />
<parameter name="clockFrequency" value="50000000" />
<parameter name="cpuArchRev" value="1" />
<parameter name="cpuID" value="0" />
<parameter name="cpuReset" value="false" />
<parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
<parameter name="dataAddrWidth" value="19" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
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<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='timer.s1' start='0x41000' end='0x41020' type='altera_avalon_timer.s1' /><slave name='TERASIC_AUTO_FOCUS_0.mm_ctrl' start='0x41020' end='0x41040' type='TERASIC_AUTO_FOCUS.mm_ctrl' /><slave name='i2c_opencores_camera.avalon_slave_0' start='0x41040' end='0x41060' type='i2c_opencores.avalon_slave_0' /><slave name='i2c_opencores_mipi.avalon_slave_0' start='0x41060' end='0x41080' type='i2c_opencores.avalon_slave_0' /><slave name='mipi_pwdn_n.s1' start='0x41080' end='0x41090' type='altera_avalon_pio.s1' /><slave name='mipi_reset_n.s1' start='0x41090' end='0x410A0' type='altera_avalon_pio.s1' /><slave name='key.s1' start='0x410A0' end='0x410B0' type='altera_avalon_pio.s1' /><slave name='sw.s1' start='0x410B0' end='0x410C0' type='altera_avalon_pio.s1' /><slave name='led.s1' start='0x410C0' end='0x410D0' type='altera_avalon_pio.s1' /><slave name='altpll_0.pll_slave' start='0x410D0' end='0x410E0' type='altpll.pll_slave' /><slave name='sysid_qsys.control_slave' start='0x410E0' end='0x410E8' type='altera_avalon_sysid_qsys.control_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x410E8' end='0x410F0' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='EEE_IMGPROC_0.s1' start='0x42000' end='0x42020' type='EEE_IMGPROC.s1' /><slave name='uart_0.s1' start='0x42020' end='0x42040' type='altera_avalon_uart.s1' /></address-map>]]></parameter>
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<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
<parameter name="data_master_paddr_size" value="0" />
<parameter name="dcache_bursts" value="false" />
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_ramBlockType" value="Automatic" />
<parameter name="dcache_size" value="2048" />
<parameter name="dcache_tagramBlockType" value="Automatic" />
<parameter name="dcache_victim_buf_impl" value="ram" />
<parameter name="debug_OCIOnchipTrace" value="_128" />
<parameter name="debug_assignJtagInstanceID" value="false" />
<parameter name="debug_datatrigger" value="0" />
<parameter name="debug_debugReqSignals" value="false" />
<parameter name="debug_enabled" value="true" />
<parameter name="debug_hwbreakpoint" value="0" />
<parameter name="debug_jtagInstanceID" value="0" />
<parameter name="debug_traceStorage" value="onchip_trace" />
<parameter name="debug_traceType" value="none" />
<parameter name="debug_triggerArming" value="true" />
<parameter name="deviceFamilyName" value="MAX 10" />
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<parameter name="deviceFeaturesSystemInfo">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_
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<parameter name="dividerType" value="no_div" />
<parameter name="exceptionOffset" value="32" />
<parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
<parameter name="faAddrWidth" value="1" />
<parameter name="faSlaveMapParam" value="" />
<parameter name="fa_cache_line" value="2" />
<parameter name="fa_cache_linesize" value="0" />
<parameter name="flash_instruction_master_paddr_base" value="0" />
<parameter name="flash_instruction_master_paddr_size" value="0" />
<parameter name="icache_burstType" value="None" />
<parameter name="icache_numTCIM" value="0" />
<parameter name="icache_ramBlockType" value="Automatic" />
<parameter name="icache_size" value="4096" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Fast" />
<parameter name="instAddrWidth" value="19" />
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<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='altera_avalon_onchip_memory2.s1' /><slave name='nios2_gen2.debug_mem_slave' start='0x40800' end='0x41000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
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<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
<parameter name="instruction_master_high_performance_paddr_size" value="0" />
<parameter name="instruction_master_paddr_base" value="0" />
<parameter name="instruction_master_paddr_size" value="0" />
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<parameter name="internalIrqMaskSystemInfo" value="31" />
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<parameter name="io_regionbase" value="0" />
<parameter name="io_regionsize" value="0" />
<parameter name="master_addr_map" value="false" />
<parameter name="mmu_TLBMissExcOffset" value="0" />
<parameter name="mmu_TLBMissExcSlave" value="None" />
<parameter name="mmu_autoAssignTlbPtrSz" value="true" />
<parameter name="mmu_enabled" value="false" />
<parameter name="mmu_processIDNumBits" value="8" />
<parameter name="mmu_ramBlockType" value="Automatic" />
<parameter name="mmu_tlbNumWays" value="16" />
<parameter name="mmu_tlbPtrSz" value="7" />
<parameter name="mmu_udtlbNumEntries" value="6" />
<parameter name="mmu_uitlbNumEntries" value="4" />
<parameter name="mpu_enabled" value="false" />
<parameter name="mpu_minDataRegionSize" value="12" />
<parameter name="mpu_minInstRegionSize" value="12" />
<parameter name="mpu_numOfDataRegion" value="8" />
<parameter name="mpu_numOfInstRegion" value="8" />
<parameter name="mpu_useLimit" value="false" />
<parameter name="mpx_enabled" value="false" />
<parameter name="mul_32_impl" value="2" />
<parameter name="mul_64_impl" value="0" />
<parameter name="mul_shift_choice" value="0" />
<parameter name="ocimem_ramBlockType" value="Automatic" />
<parameter name="ocimem_ramInit" value="false" />
<parameter name="regfile_ramBlockType" value="Automatic" />
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<parameter name="register_file_por" value="false" />
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<parameter name="resetOffset" value="0" />
<parameter name="resetSlave" value="onchip_memory2_0.s1" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="setting_HBreakTest" value="false" />
<parameter name="setting_HDLSimCachesCleared" value="true" />
<parameter name="setting_activateMonitors" value="true" />
<parameter name="setting_activateTestEndChecker" value="false" />
<parameter name="setting_activateTrace" value="false" />
<parameter name="setting_allow_break_inst" value="false" />
<parameter name="setting_alwaysEncrypt" value="true" />
<parameter name="setting_asic_add_scan_mode_input" value="false" />
<parameter name="setting_asic_enabled" value="false" />
<parameter name="setting_asic_synopsys_translate_on_off" value="false" />
<parameter name="setting_asic_third_party_synthesis" value="false" />
<parameter name="setting_avalonDebugPortPresent" value="false" />
<parameter name="setting_bhtPtrSz" value="8" />
<parameter name="setting_bigEndian" value="false" />
<parameter name="setting_branchpredictiontype" value="Dynamic" />
<parameter name="setting_breakslaveoveride" value="false" />
<parameter name="setting_clearXBitsLDNonBypass" value="true" />
<parameter name="setting_dc_ecc_present" value="true" />
<parameter name="setting_disable_tmr_inj" value="false" />
<parameter name="setting_disableocitrace" value="false" />
<parameter name="setting_dtcm_ecc_present" value="true" />
<parameter name="setting_ecc_present" value="false" />
<parameter name="setting_ecc_sim_test_ports" value="false" />
<parameter name="setting_exportHostDebugPort" value="false" />
<parameter name="setting_exportPCB" value="false" />
<parameter name="setting_export_large_RAMs" value="false" />
<parameter name="setting_exportdebuginfo" value="false" />
<parameter name="setting_exportvectors" value="false" />
<parameter name="setting_fast_register_read" value="false" />
<parameter name="setting_ic_ecc_present" value="true" />
<parameter name="setting_interruptControllerType" value="Internal" />
<parameter name="setting_itcm_ecc_present" value="true" />
<parameter name="setting_mmu_ecc_present" value="true" />
<parameter name="setting_oci_export_jtag_signals" value="false" />
<parameter name="setting_oci_version" value="1" />
<parameter name="setting_preciseIllegalMemAccessException" value="false" />
<parameter name="setting_removeRAMinit" value="false" />
<parameter name="setting_rf_ecc_present" value="true" />
<parameter name="setting_shadowRegisterSets" value="0" />
<parameter name="setting_showInternalSettings" value="false" />
<parameter name="setting_showUnpublishedSettings" value="false" />
<parameter name="setting_support31bitdcachebypass" value="true" />
<parameter name="setting_tmr_output_disable" value="false" />
<parameter name="setting_usedesignware" value="false" />
<parameter name="shift_rot_impl" value="1" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster0MapParam" value="" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1MapParam" value="" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2MapParam" value="" />
<parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster3MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
<parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
<parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
<parameter name="tmr_enabled" value="false" />
<parameter name="tracefilename" value="" />
<parameter name="userDefinedSettings" value="" />
</module>
<module
name="onchip_memory2_0"
kind="altera_avalon_onchip_memory2"
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version="16.1"
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enabled="1">
<parameter name="allowInSystemMemoryContentEditor" value="false" />
<parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_0</parameter>
<parameter name="blockType" value="AUTO" />
<parameter name="copyInitFile" value="false" />
<parameter name="dataWidth" value="32" />
<parameter name="dataWidth2" value="32" />
<parameter name="deviceFamily" value="MAX 10" />
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<parameter name="deviceFeatures">ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPOR
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<parameter name="dualPort" value="false" />
<parameter name="ecc_enabled" value="false" />
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<parameter name="enPRInitMode" value="false" />
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<parameter name="enableDiffWidth" value="false" />
<parameter name="initMemContent" value="false" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
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<parameter name="memorySize" value="131072" />
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<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
<parameter name="simMemInitOnlyFilename" value="0" />
<parameter name="singleClockOperation" value="false" />
<parameter name="slave1Latency" value="1" />
<parameter name="slave2Latency" value="1" />
<parameter name="useNonDefaultInitFile" value="false" />
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module
name="sdram"
kind="altera_avalon_new_sdram_controller"
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version="16.1"
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enabled="1">
<parameter name="TAC" value="5.5" />
<parameter name="TMRD" value="3" />
<parameter name="TRCD" value="20.0" />
<parameter name="TRFC" value="70.0" />
<parameter name="TRP" value="20.0" />
<parameter name="TWR" value="14.0" />
<parameter name="casLatency" value="3" />
<parameter name="clockRate" value="100000000" />
<parameter name="columnWidth" value="10" />
<parameter name="componentName" value="$${FILENAME}_sdram" />
<parameter name="dataWidth" value="16" />
<parameter name="generateSimulationModel" value="true" />
<parameter name="initNOPDelay" value="0.0" />
<parameter name="initRefreshCommands" value="2" />
<parameter name="masteredTristateBridgeSlave" value="0" />
<parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
<parameter name="numberOfBanks" value="4" />
<parameter name="numberOfChipSelects" value="1" />
<parameter name="pinsSharedViaTriState" value="false" />
<parameter name="powerUpDelay" value="100.0" />
<parameter name="refreshPeriod" value="15.625" />
<parameter name="registerDataIn" value="true" />
<parameter name="rowWidth" value="13" />
</module>
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<module name="sw" kind="altera_avalon_pio" version="16.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
<parameter name="bitModifyingOutReg" value="false" />
<parameter name="captureEdge" value="false" />
<parameter name="clockRate" value="50000000" />
<parameter name="direction" value="Input" />
<parameter name="edgeType" value="RISING" />
<parameter name="generateIRQ" value="false" />
<parameter name="irqType" value="LEVEL" />
<parameter name="resetValue" value="0" />
<parameter name="simDoTestBenchWiring" value="false" />
<parameter name="simDrivenValue" value="0" />
<parameter name="width" value="10" />
</module>
<module
name="sysid_qsys"
kind="altera_avalon_sysid_qsys"
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version="16.1"
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enabled="1">
<parameter name="id" value="0" />
</module>
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<module name="timer" kind="altera_avalon_timer" version="16.1" enabled="1">
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<parameter name="alwaysRun" value="false" />
<parameter name="counterSize" value="32" />
<parameter name="fixedPeriod" value="false" />
<parameter name="period" value="1" />
<parameter name="periodUnits" value="MSEC" />
<parameter name="resetOutput" value="false" />
<parameter name="snapshot" value="true" />
<parameter name="systemFrequency" value="50000000" />
<parameter name="timeoutPulseOutput" value="false" />
<parameter name="watchdogPulse" value="2" />
</module>
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<module name="uart_0" kind="altera_avalon_uart" version="16.1" enabled="1">
<parameter name="baud" value="115200" />
<parameter name="clockRate" value="50000000" />
<parameter name="dataBits" value="8" />
<parameter name="fixedBaud" value="true" />
<parameter name="parity" value="NONE" />
<parameter name="simCharStream" value="" />
<parameter name="simInteractiveInputEnable" value="false" />
<parameter name="simInteractiveOutputEnable" value="false" />
<parameter name="simTrueBaud" value="false" />
<parameter name="stopBits" value="1" />
<parameter name="syncRegDepth" value="2" />
<parameter name="useCtsRts" value="false" />
<parameter name="useEopRegister" value="false" />
<parameter name="useRelativePathForSimFile" value="false" />
</module>
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="avalon"
Changed Colour recognition code
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version="16.1"
Add Vision initial files from vision resource repo
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start="nios2_gen2.data_master"
end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000410e8" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="i2c_opencores_mipi.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00041060" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="i2c_opencores_camera.avalon_slave_0">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00041040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
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start="nios2_gen2.data_master"
end="sysid_qsys.control_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000410e0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
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start="nios2_gen2.data_master"
end="nios2_gen2.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00040800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="TERASIC_AUTO_FOCUS_0.mm_ctrl">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00041020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
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start="nios2_gen2.data_master"
end="altpll_0.pll_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000410d0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
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start="nios2_gen2.data_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="timer.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00041000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="led.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000410c0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="sw.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000410b0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="key.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x000410a0" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="mipi_reset_n.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00041090" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="mipi_pwdn_n.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00041080" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.data_master"
end="EEE_IMGPROC_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00042000" />
<parameter name="defaultConnection" value="false" />
</connection>
Vision "Fresh Start" from Updated Upstream
2021-06-08 18:07:13 +00:00
<connection
kind="avalon"
version="16.1"
start="nios2_gen2.data_master"
end="uart_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00042020" />
<parameter name="defaultConnection" value="false" />
</connection>
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="avalon"
Changed Colour recognition code
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version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.instruction_master"
end="nios2_gen2.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00040800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.instruction_master"
end="onchip_memory2_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="alt_vip_vfb_0.read_master"
end="sdram.s1">
<parameter name="arbitrationPriority" value="50" />
<parameter name="baseAddress" value="0x04000000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="alt_vip_vfb_0.write_master"
end="sdram.s1">
<parameter name="arbitrationPriority" value="30" />
<parameter name="baseAddress" value="0x04000000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon_streaming"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="TERASIC_CAMERA_0.avalon_streaming_source"
end="alt_vip_vfb_0.din" />
<connection
kind="avalon_streaming"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="EEE_IMGPROC_0.avalon_streaming_source"
end="alt_vip_itc_0.din" />
<connection
kind="avalon_streaming"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="TERASIC_AUTO_FOCUS_0.dout"
end="EEE_IMGPROC_0.avalon_streaming_sink" />
<connection
kind="avalon_streaming"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="alt_vip_vfb_0.dout"
end="TERASIC_AUTO_FOCUS_0.din" />
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
<connection kind="clock" version="16.1" start="altpll_0.c2" end="sdram.clk" />
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="altpll_0.c2"
end="TERASIC_AUTO_FOCUS_0.clock" />
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="altpll_0.c2"
end="alt_vip_vfb_0.clock" />
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="altpll_0.c2"
end="EEE_IMGPROC_0.clock" />
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="altpll_0.c2"
end="TERASIC_CAMERA_0.clock_reset" />
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="altpll_0.c2"
end="alt_vip_itc_0.is_clk_rst" />
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
<connection kind="clock" version="16.1" start="clk_50.clk" end="jtag_uart.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="sysid_qsys.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="timer.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="led.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="sw.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="key.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="mipi_reset_n.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="mipi_pwdn_n.clk" />
<connection kind="clock" version="16.1" start="clk_50.clk" end="nios2_gen2.clk" />
Vision "Fresh Start" from Updated Upstream
2021-06-08 18:07:13 +00:00
<connection kind="clock" version="16.1" start="clk_50.clk" end="uart_0.clk" />
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk"
end="onchip_memory2_0.clk1" />
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk"
end="i2c_opencores_mipi.clock" />
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk"
end="i2c_opencores_camera.clock" />
<connection
kind="clock"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk"
end="altpll_0.inclk_interface" />
<connection
kind="interrupt"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.irq"
end="i2c_opencores_mipi.interrupt_sender">
<parameter name="irqNumber" value="0" />
</connection>
<connection
kind="interrupt"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.irq"
end="i2c_opencores_camera.interrupt_sender">
<parameter name="irqNumber" value="1" />
</connection>
<connection
kind="interrupt"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.irq"
end="jtag_uart.irq">
<parameter name="irqNumber" value="2" />
</connection>
<connection
kind="interrupt"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.irq"
end="timer.irq">
<parameter name="irqNumber" value="3" />
</connection>
Vision "Fresh Start" from Updated Upstream
2021-06-08 18:07:13 +00:00
<connection
kind="interrupt"
version="16.1"
start="nios2_gen2.irq"
end="uart_0.irq">
<parameter name="irqNumber" value="4" />
</connection>
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="i2c_opencores_mipi.clock_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="i2c_opencores_camera.clock_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="TERASIC_CAMERA_0.clock_reset_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="altpll_0.inclk_interface_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="alt_vip_itc_0.is_clk_rst_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="sdram.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="nios2_gen2.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="alt_vip_vfb_0.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="jtag_uart.reset" />
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
<connection kind="reset" version="16.1" start="clk_50.clk_reset" end="key.reset" />
<connection kind="reset" version="16.1" start="clk_50.clk_reset" end="led.reset" />
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="mipi_pwdn_n.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="mipi_reset_n.reset" />
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
<connection kind="reset" version="16.1" start="clk_50.clk_reset" end="sw.reset" />
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="sysid_qsys.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="timer.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="TERASIC_AUTO_FOCUS_0.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="EEE_IMGPROC_0.reset" />
Vision "Fresh Start" from Updated Upstream
2021-06-08 18:07:13 +00:00
<connection
kind="reset"
version="16.1"
start="clk_50.clk_reset"
end="uart_0.reset" />
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="clk_50.clk_reset"
end="onchip_memory2_0.reset1" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="i2c_opencores_mipi.clock_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="i2c_opencores_camera.clock_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="TERASIC_CAMERA_0.clock_reset_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="alt_vip_itc_0.is_clk_rst_reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="jtag_uart.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="sysid_qsys.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="timer.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="led.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="sw.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="key.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="mipi_reset_n.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="mipi_pwdn_n.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="nios2_gen2.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="sdram.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="alt_vip_vfb_0.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="TERASIC_AUTO_FOCUS_0.reset" />
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="EEE_IMGPROC_0.reset" />
Vision "Fresh Start" from Updated Upstream
2021-06-08 18:07:13 +00:00
<connection
kind="reset"
version="16.1"
start="nios2_gen2.debug_reset_request"
end="uart_0.reset" />
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
<connection
kind="reset"
Changed Colour recognition code
2021-05-27 23:40:25 +00:00
version="16.1"
Add Vision initial files from vision resource repo
2021-05-18 11:20:27 +00:00
start="nios2_gen2.debug_reset_request"
end="onchip_memory2_0.reset1" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>
Reference in a new issue Copy permalink