mirror of
https://github.com/supleed2/ELEC50003-P1-CW.git
synced 2024-09-19 20:16:16 +00:00
184 lines
6.4 KiB
Tcl
184 lines
6.4 KiB
Tcl
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# TCL File Generated by Component Editor 16.0
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# Fri Apr 23 12:07:51 BST 2021
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# DO NOT MODIFY
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#
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# EEE_IMGPROC "EEE_IMGPROC" v1.0
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# 2021.04.23.12:07:51
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#
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#
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#
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# request TCL package from ACDS 16.0
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#
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package require -exact qsys 16.0
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#
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# module EEE_IMGPROC
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME EEE_IMGPROC
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME EEE_IMGPROC
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL EEE_IMGPROC
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file EEE_IMGPROC.v VERILOG PATH ip/EEE_IMGPROC/EEE_IMGPROC.v TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset_n reset_n Input 1
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#
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# connection point avalon_streaming_sink
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#
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add_interface avalon_streaming_sink avalon_streaming end
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set_interface_property avalon_streaming_sink associatedClock clock
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set_interface_property avalon_streaming_sink associatedReset reset
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set_interface_property avalon_streaming_sink dataBitsPerSymbol 8
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set_interface_property avalon_streaming_sink errorDescriptor ""
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set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true
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set_interface_property avalon_streaming_sink maxChannel 0
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set_interface_property avalon_streaming_sink readyLatency 1
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set_interface_property avalon_streaming_sink ENABLED true
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set_interface_property avalon_streaming_sink EXPORT_OF ""
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set_interface_property avalon_streaming_sink PORT_NAME_MAP ""
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set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP ""
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add_interface_port avalon_streaming_sink sink_data data Input 24
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add_interface_port avalon_streaming_sink sink_valid valid Input 1
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add_interface_port avalon_streaming_sink sink_ready ready Output 1
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add_interface_port avalon_streaming_sink sink_sop startofpacket Input 1
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add_interface_port avalon_streaming_sink sink_eop endofpacket Input 1
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#
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# connection point avalon_streaming_source
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#
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add_interface avalon_streaming_source avalon_streaming start
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set_interface_property avalon_streaming_source associatedClock clock
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set_interface_property avalon_streaming_source associatedReset reset
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set_interface_property avalon_streaming_source dataBitsPerSymbol 8
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set_interface_property avalon_streaming_source errorDescriptor ""
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set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true
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set_interface_property avalon_streaming_source maxChannel 0
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set_interface_property avalon_streaming_source readyLatency 1
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set_interface_property avalon_streaming_source ENABLED true
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set_interface_property avalon_streaming_source EXPORT_OF ""
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set_interface_property avalon_streaming_source PORT_NAME_MAP ""
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set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP ""
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add_interface_port avalon_streaming_source source_data data Output 24
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add_interface_port avalon_streaming_source source_eop endofpacket Output 1
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add_interface_port avalon_streaming_source source_ready ready Input 1
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add_interface_port avalon_streaming_source source_sop startofpacket Output 1
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add_interface_port avalon_streaming_source source_valid valid Output 1
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#
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# connection point s1
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#
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add_interface s1 avalon end
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set_interface_property s1 addressUnits WORDS
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set_interface_property s1 associatedClock clock
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set_interface_property s1 associatedReset reset
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set_interface_property s1 bitsPerSymbol 8
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set_interface_property s1 burstOnBurstBoundariesOnly false
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set_interface_property s1 burstcountUnits WORDS
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set_interface_property s1 explicitAddressSpan 0
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set_interface_property s1 holdTime 0
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set_interface_property s1 linewrapBursts false
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set_interface_property s1 maximumPendingReadTransactions 0
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set_interface_property s1 maximumPendingWriteTransactions 0
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set_interface_property s1 readLatency 0
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set_interface_property s1 readWaitTime 1
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set_interface_property s1 setupTime 0
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set_interface_property s1 timingUnits Cycles
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set_interface_property s1 writeWaitTime 0
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set_interface_property s1 ENABLED true
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set_interface_property s1 EXPORT_OF ""
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set_interface_property s1 PORT_NAME_MAP ""
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set_interface_property s1 CMSIS_SVD_VARIABLES ""
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set_interface_property s1 SVD_ADDRESS_GROUP ""
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add_interface_port s1 s_chipselect chipselect Input 1
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add_interface_port s1 s_read read Input 1
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add_interface_port s1 s_write write Input 1
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add_interface_port s1 s_readdata readdata Output 32
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add_interface_port s1 s_writedata writedata Input 32
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add_interface_port s1 s_address address Input 3
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set_interface_assignment s1 embeddedsw.configuration.isFlash 0
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set_interface_assignment s1 embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment s1 embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment s1 embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point conduit_mode
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#
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add_interface conduit_mode conduit end
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set_interface_property conduit_mode associatedClock clock
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set_interface_property conduit_mode associatedReset ""
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set_interface_property conduit_mode ENABLED true
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set_interface_property conduit_mode EXPORT_OF ""
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set_interface_property conduit_mode PORT_NAME_MAP ""
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set_interface_property conduit_mode CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_mode SVD_ADDRESS_GROUP ""
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add_interface_port conduit_mode mode new_signal Input 1
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