ELEC40006-P1-CW/ram_instr.qip
Aadi Desai d046242bc1 Final State before Pipelining
Debug Complete, data and instruction mifs + ram files. Test program checked
2020-06-09 22:45:20 +01:00

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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_instr.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_instr.bsf"]