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14 lines
169 B
Verilog
14 lines
169 B
Verilog
module ADD_1 (enable, in, out);
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input [15:0] in;
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input enable;
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output reg [15:0] out;
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always @(*) begin
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if(enable)
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out = in + 1'b1;
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else
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out = in;
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end
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endmodule |