mirror of
https://github.com/supleed2/ELEC40006-P1-CW.git
synced 2024-11-10 02:05:48 +00:00
27 lines
291 B
Coq
27 lines
291 B
Coq
module SM_piplined (CLK, RST, E2, EXEC1, EXEC2);
|
|
|
|
input CLK;
|
|
input RST;
|
|
input E2;
|
|
output EXEC1;
|
|
output EXEC2;
|
|
|
|
reg s;
|
|
|
|
always @(posedge CLK) begin
|
|
if(!RST)
|
|
if(!s)
|
|
if(E2)
|
|
s = 1'b1;
|
|
else ;
|
|
else
|
|
s = 1'b0;
|
|
else
|
|
s = 1'b0;
|
|
end
|
|
|
|
assign EXEC1 = ~s;
|
|
assign EXEC2 = s;
|
|
|
|
endmodule
|