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28 lines
300 B
Verilog
28 lines
300 B
Verilog
module SM_pipelined (CLK, RST, E2, EXEC1, EXEC2);
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input CLK;
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input RST;
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input E2;
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output EXEC1;
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output EXEC2;
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reg s = 0;
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assign EXEC1 = ~s;
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assign EXEC2 = s;
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always @(posedge CLK) begin
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if(!RST)
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if(!s)
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if(E2)
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s <= 1;
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else
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s <= 0;
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else
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s <= 0;
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else
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s <= 0;
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end
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endmodule
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