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8 lines
139 B
Verilog
8 lines
139 B
Verilog
module min(sign, a, b, num);
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input sign;
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input [7:0] a;
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input [7:0] b;
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output [7:0] num;
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assign num = sign ? a[7:0]:b[7:0];
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endmodule
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