supleed2/ELEC40006-P1-CW
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Author SHA1 Message Date
Aadi Desai 87f3d0e919 CPU set up for testing and analysis 2020-06-11 17:28:00 +01:00
Kacper 685f69a7cf Almost ready CPU 
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
 2020-06-07 15:08:34 +01:00