supleed2/ELEC40006-P1-CW
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2 commits

Author SHA1 Message Date
Kacper 685f69a7cf Almost ready CPU 
Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
 2020-06-07 15:08:34 +01:00
Aadi Desai 7997617e00 Add stack Verilog file 
Uses Last In First Out ordering
 2020-06-04 18:03:46 +01:00