supleed2/ELEC40006-P1-CW
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4 commits

Author SHA1 Message Date
Aadi Desai 08a8635959 Updated ALU to use internal carry register 
Also tidied up begin/end tags to reduce number of lines and improve readability
 2020-06-04 15:05:13 +01:00
Aadi Desai 3647e0b15c ALU now uses multiply block rather than * operator 
Updated to use custom block and decide which step of MUL, MLA and MLS depending on exec2 input
 2020-06-03 15:15:44 +01:00
Aadi Desai 2ca1e90a2c ALU enable control added, minor fix with RRC 
Multiply still to be updated
 2020-06-02 16:57:58 +01:00
Aadi Desai 3f0c91b0ff
Initial ALU Verilog 
Currently using incorrect implementation for Multiply (* operator), to be fixed once Multiply method is decided
 2020-05-29 14:16:02 +01:00