Finished decoder

This commit is contained in:
Kacper 2020-05-27 18:53:03 +01:00
parent 1747e0c0b2
commit e1acb56b66
9 changed files with 741 additions and 152 deletions

1
.gitignore vendored
View file

@ -2,3 +2,4 @@ db/*
incremental_db/* incremental_db/*
output_files/* output_files/*
simulation/* simulation/*
greybox_tmp/cbx_args.txt

View file

@ -23,7 +23,7 @@ refer to the applicable agreement for further details.
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(text "CLK" (rect 5 0 27 12)(font "Arial" )) (text "CLK" (rect 5 0 26 12)(font "Arial" ))
(pt 168 8) (pt 168 8)
(drawing (drawing
(line (pt 84 12)(pt 109 12)) (line (pt 84 12)(pt 109 12))
@ -739,7 +739,7 @@ refer to the applicable agreement for further details.
) )
) )
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(text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10))) (text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10)))
(text "RAMd" (rect 8 128 37 140)(font "Arial" )) (text "RAMd" (rect 8 128 37 140)(font "Arial" ))
(port (port
@ -920,6 +920,195 @@ refer to the applicable agreement for further details.
(line (pt 0 0)(pt 0 0)) (line (pt 0 0)(pt 0 0))
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(text "DECODE" (rect 8 288 55 300)(font "Arial" ))
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(input)
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)
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)
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(text "R6_en" (rect 161 139 187 151)(font "Arial" ))
(line (pt 208 144)(pt 192 144))
)
(port
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(output)
(text "R7_en" (rect 0 0 31 12)(font "Arial" ))
(text "R7_en" (rect 161 155 187 167)(font "Arial" ))
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(text "s1[2..0]" (rect 0 0 37 12)(font "Arial" ))
(text "s1[2..0]" (rect 156 171 187 183)(font "Arial" ))
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(line (pt 208 256)(pt 192 256))
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(text "RAMi_en" (rect 151 267 187 279)(font "Arial" ))
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(rect 1024 304 1136 352)
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(line (pt 64 32)(pt 112 32)(line_width 3))
)
(parameter
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"0"
"Unsigned value to which outputs will be set"
(type "PARAMETER_UNSIGNED_DEC") )
(parameter
"LPM_WIDTH"
"16"
"Width of output, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32"
)
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(line (pt 16 40)(pt 64 40))
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(line (pt 16 40)(pt 16 24))
)
(annotation_block (parameter)(rect 1136 304 1152 312))
)
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(rect 1008 504 1040 536)
(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
(text "inst" (rect 3 21 20 33)(font "Arial" )(invisible))
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(pt 16 0)
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(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
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(pt 632 416) (pt 632 416)
@ -1055,21 +1244,6 @@ refer to the applicable agreement for further details.
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) )
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(pt 592 176) (pt 592 176)
(pt 592 160) (pt 592 160)
@ -1132,26 +1306,6 @@ refer to the applicable agreement for further details.
(pt 448 624) (pt 448 624)
(bus) (bus)
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(pt 1152 144)
(pt 1160 144)
(bus)
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(pt 1160 304)
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(bus)
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@ -1163,28 +1317,7 @@ refer to the applicable agreement for further details.
(bus) (bus)
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(pt 856 144) (text "s4" (rect 1203 368 1220 378)(font "Intel Clear" )(vertical))
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@ -1238,45 +1371,16 @@ refer to the applicable agreement for further details.
(pt 744 -56) (pt 744 -56)
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(text "instr[15..0]" (rect 864 -88 913 -71)(font "Intel Clear" ))
(pt 856 -72)
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(text "EXEC" (rect 783 -28 800 -3)(font "Intel Clear" )(vertical)) (text "EXEC" (rect 783 -28 800 -3)(font "Intel Clear" )(vertical))
(pt 800 -32) (pt 800 -32)
(pt 800 0) (pt 800 0)
) )
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(pt 448 608) (pt 448 608)
(bus) (bus)
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@ -1287,12 +1391,6 @@ refer to the applicable agreement for further details.
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(pt 504 144) (pt 504 144)
@ -1308,26 +1406,6 @@ refer to the applicable agreement for further details.
(pt 208 -80) (pt 208 -80)
(bus) (bus)
) )
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)
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(pt 936 224)
(pt 880 224)
)
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)
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(bus)
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(pt 504 192) (pt 504 192)
(pt 504 416) (pt 504 416)
@ -1458,16 +1536,6 @@ refer to the applicable agreement for further details.
(pt 224 448) (pt 224 448)
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@ -1538,12 +1606,6 @@ refer to the applicable agreement for further details.
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@ -1609,6 +1671,262 @@ refer to the applicable agreement for further details.
(pt 256 -16) (pt 256 -16)
(pt 216 -16) (pt 216 -16)
) )
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(pt 936 224)
(pt 872 224)
(bus)
)
(connector
(text "RAMd_en" (rect 890 272 937 289)(font "Intel Clear" ))
(pt 936 288)
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)
(connector
(text "CLK" (rect 890 256 910 273)(font "Intel Clear" ))
(pt 936 272)
(pt 880 272)
)
(connector
(text "RAMd_wren" (rect 882 192 941 209)(font "Intel Clear" ))
(pt 936 208)
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(connector
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(bus)
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(pt 1160 304)
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(bus)
)
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(pt 912 -120)
(bus)
)
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(pt 968 -88)
(pt 928 -88)
)
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(pt 928 -104)
)
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)
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(pt 1176 -104)
(pt 1224 -104)
)
(connector
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(pt 1176 -88)
(pt 1224 -88)
)
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(pt 1176 -72)
(pt 1224 -72)
)
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)
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(pt 1176 -40)
(pt 1224 -40)
)
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(pt 1176 -24)
(pt 1224 -24)
)
(connector
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(pt 1176 -8)
(pt 1224 -8)
)
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(pt 1176 8)
(pt 1224 8)
)
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(pt 1176 56)
(pt 1224 56)
(bus)
)
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(pt 1224 72)
)
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)
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)
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(pt 448 104)
(pt 448 592)
(bus)
)
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(pt 632 144)
(pt 592 144)
)
(connector
(text "s1[1]" (rect 602 144 625 161)(font "Intel Clear" ))
(pt 632 160)
(pt 592 160)
)
(connector
(text "s1[2]" (rect 602 160 625 177)(font "Intel Clear" ))
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(bus)
)
(connector
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(bus)
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(pt 1024 488)
)
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)
(junction (pt 504 416)) (junction (pt 504 416))
(junction (pt 504 192)) (junction (pt 504 192))
(junction (pt 520 432)) (junction (pt 520 432))
@ -1624,7 +1942,6 @@ refer to the applicable agreement for further details.
(junction (pt 592 144)) (junction (pt 592 144))
(junction (pt 448 592)) (junction (pt 448 592))
(junction (pt 448 608)) (junction (pt 448 608))
(junction (pt 856 144))
(junction (pt 488 -72)) (junction (pt 488 -72))
(junction (pt 520 208)) (junction (pt 520 208))
(junction (pt 536 224)) (junction (pt 536 224))
@ -1640,3 +1957,5 @@ refer to the applicable agreement for further details.
(junction (pt 160 384)) (junction (pt 160 384))
(junction (pt 160 416)) (junction (pt 160 416))
(junction (pt 160 448)) (junction (pt 160 448))
(junction (pt 856 192))
(junction (pt 872 -72))

View file

@ -38,13 +38,17 @@
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE AUTO set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY test set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name BDF_FILE CPUProject.bdf set_global_assignment -name BDF_FILE CPUProject.bdf
set_global_assignment -name BDF_FILE reg_file.bdf set_global_assignment -name BDF_FILE reg_file.bdf
set_global_assignment -name BDF_FILE mux_8x16.bdf set_global_assignment -name BDF_FILE mux_8x16.bdf
@ -52,10 +56,5 @@ set_global_assignment -name QIP_FILE ram_data.qip
set_global_assignment -name QIP_FILE ram_instr.qip set_global_assignment -name QIP_FILE ram_instr.qip
set_global_assignment -name BDF_FILE SM.bdf set_global_assignment -name BDF_FILE SM.bdf
set_global_assignment -name VERILOG_FILE DECODE.v set_global_assignment -name VERILOG_FILE DECODE.v
set_global_assignment -name MIF_FILE test.mif set_global_assignment -name MIF_FILE data.mif
set_global_assignment -name BDF_FILE test.bdf set_global_assignment -name MIF_FILE instr.mif
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

162
DECODE.bsf Normal file
View file

@ -0,0 +1,162 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
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View file

@ -1,10 +1,10 @@
module DECODE module DECODE
( (
input [15:0] instr, input [15:0] instr,
input FETCH,
input EXEC, input EXEC,
input COND_result, input COND_result,
output R0_count, output R0_count,
output R0_en,
output R1_en, output R1_en,
output R2_en, output R2_en,
output R3_en, output R3_en,
@ -20,13 +20,69 @@ module DECODE
output RAMd_en, output RAMd_en,
output RAMi_en output RAMi_en
); );
wire msb, ls, [reg_ls, addr, op, Rd, Rs1, Rs2;
assign msb = instr[15]; //MSB of the instruction word
assign ls = instr[14]; //LOAD or STORE bit
assign reg_ls = instr
wire LOAD, STORE, UJMP, JMP, AND, OR, XOR, NOT, NND, NOR, XNR, MOV, ADD, ADC, ADO, SUB, SBC, SBO, MUL, MLA, MLS, MRT, LSL, LSR, ASR, ROR, RRC, NOP, STP; wire msb = instr[15]; //MSB of the instruction word
assign LOAD = wire ls = instr[14]; //LOAD or STORE bit
wire [2:0] Rls = instr[13:11]; //Register in the LOAD/STORE operation
wire [10:0] addr = instr[10:0]; //Memory address in the LOAD/STORE operation
wire [5:0] op = instr[14:9]; //Opcode in regular instructions
wire [2:0] Rd = instr[8:6]; //Destination register in command
wire [2:0] Rs1 = instr[5:3]; //Source register 1 in command
wire [2:0] Rs2 = instr[2:0]; //Source register 2 in command
//Different opcodes (refer to documentation):
wire LOAD = msb & ~ls;
wire STORE = msb & ls;
wire UJMP = ~op[5] & ~op[4] & ~op[3] & ~op[2];
wire JMP = (~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]);
wire AND = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire OR = ~op[5] & ~op[4] & op[3] & op[2] & ~op[1] & op[0];
wire XOR = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & ~op[0];
wire NOT = ~op[5] & ~op[4] & op[3] & op[2] & op[1] & op[0];
wire NND = ~op[5] & op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
wire NOR = ~op[5] & op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire XNR = ~op[5] & op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire MOV = ~op[5] & op[4] & ~op[3] & ~op[2] & op[1] & op[0];
wire ADD = ~op[5] & op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire ADC = ~op[5] & op[4] & ~op[3] & op[2] & ~op[1] & op[0];
wire ADO = ~op[5] & op[4] & ~op[3] & op[2] & op[1] & ~op[0];
wire SUB = ~op[5] & op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
wire SBC = ~op[5] & op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire SBO = ~op[5] & op[4] & op[3] & ~op[2] & op[1] & ~op[0];
wire MUL = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire MLA = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
wire MLS = ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire MRT = ~op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
wire LSL = op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
wire LSR = op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & op[0];
wire ASR = op[5] & ~op[4] & ~op[3] & ~op[2] & op[1] & ~op[0];
wire ROR = op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & ~op[0];
wire RRC = op[5] & ~op[4] & ~op[3] & op[2] & ~op[1] & op[0];
wire NOP = op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire STP = op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
assign R0_count = EXEC & (~(UJMP | JMP | STP));
assign R0_en = EXEC & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0] | UJMP | JMP & COND_result);
assign R1_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] & ~Rd[1] & Rd[0] | LOAD & ~Rls[2] & ~Rls[1] & Rls[0]);
assign R2_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] & Rd[1] & ~Rd[0] | LOAD & ~Rls[2] & Rls[1] & ~Rls[0]);
assign R3_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] & Rd[1] & Rd[0] | LOAD & ~Rls[2] & Rls[1] & Rls[0]);
assign R4_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rd[2] & ~Rd[1] & ~Rd[0] | LOAD & Rls[2] & ~Rls[1] & ~Rls[0]);
assign R5_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rd[2] & ~Rd[1] & Rd[0] | LOAD & Rls[2] & ~Rls[1] & Rls[0]);
assign R6_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rd[2] & Rd[1] & ~Rd[0] | LOAD & Rls[2] & Rls[1] & ~Rls[0]);
assign R7_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rd[2] & Rd[1] & Rd[0] | LOAD & Rls[2] & Rls[1] & Rls[0]);
assign s1[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]));
assign s1[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]));
assign s1[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]));
assign s2[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
assign s2[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
assign s2[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
assign s3[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[2]);
assign s3[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[1]);
assign s3[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[0]);
assign s4 = EXEC & ~(LOAD | STORE);
assign RAMd_wren = EXEC & STORE;
assign RAMd_en = EXEC & (STORE | LOAD);
assign RAMi_en = EXEC & ~STP;
endmodule endmodule

25
data.mif Normal file
View file

@ -0,0 +1,25 @@
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
-- Quartus Prime generated Memory Initialization File (.mif)
WIDTH=16;
DEPTH=2048;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
[000..7FF] : 0000;
END;

25
instr.mif Normal file
View file

@ -0,0 +1,25 @@
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
-- Quartus Prime generated Memory Initialization File (.mif)
WIDTH=16;
DEPTH=2048;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
[000..7FF] : 0000;
END;

View file

@ -89,7 +89,7 @@ module ram_data (
defparam defparam
altsyncram_component.clock_enable_input_a = "NORMAL", altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "test.mif", altsyncram_component.init_file = "data.mif",
altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.lpm_type = "altsyncram",
@ -128,7 +128,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test.mif" // Retrieval info: PRIVATE: MIFfilename STRING "data.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
@ -145,7 +145,7 @@ endmodule
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif" // Retrieval info: CONSTANT: INIT_FILE STRING "data.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

View file

@ -89,6 +89,7 @@ module ram_instr (
defparam defparam
altsyncram_component.clock_enable_input_a = "NORMAL", altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "instr.mif",
altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.lpm_type = "altsyncram",
@ -115,7 +116,7 @@ endmodule
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" // Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1" // Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "1" // Retrieval info: PRIVATE: Clken NUMERIC "1"
@ -127,7 +128,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: MIFfilename STRING "instr.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048" // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
@ -144,6 +145,7 @@ endmodule
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "instr.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"