diff --git a/.gitignore b/.gitignore
index a6c0c62..a7dc782 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@ db/*
 incremental_db/*
 output_files/*
 simulation/*
+greybox_tmp/cbx_args.txt
diff --git a/CPUProject.bdf b/CPUProject.bdf
index 68acf1c..84b453d 100644
--- a/CPUProject.bdf
+++ b/CPUProject.bdf
@@ -23,7 +23,7 @@ refer to the applicable agreement for further details.
 	(input)
 	(rect 192 752 360 768)
 	(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
-	(text "CLK" (rect 5 0 27 12)(font "Arial" ))
+	(text "CLK" (rect 5 0 26 12)(font "Arial" ))
 	(pt 168 8)
 	(drawing
 		(line (pt 84 12)(pt 109 12))
@@ -739,7 +739,7 @@ refer to the applicable agreement for further details.
 	)
 )
 (symbol
-	(rect 936 112 1152 256)
+	(rect 936 160 1152 304)
 	(text "ram_data" (rect 81 0 144 16)(font "Arial" (font_size 10)))
 	(text "RAMd" (rect 8 128 37 140)(font "Arial" ))
 	(port
@@ -920,6 +920,195 @@ refer to the applicable agreement for further details.
 		(line (pt 0 0)(pt 0 0))
 	)
 )
+(symbol
+	(rect 968 -152 1176 152)
+	(text "DECODE" (rect 5 0 52 12)(font "Arial" ))
+	(text "DECODE" (rect 8 288 55 300)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "instr[15..0]" (rect 0 0 53 12)(font "Arial" ))
+		(text "instr[15..0]" (rect 21 27 74 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "EXEC" (rect 0 0 28 12)(font "Arial" ))
+		(text "EXEC" (rect 21 43 49 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "COND_result" (rect 0 0 66 12)(font "Arial" ))
+		(text "COND_result" (rect 21 59 87 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "R0_count" (rect 0 0 47 12)(font "Arial" ))
+		(text "R0_count" (rect 148 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32))
+	)
+	(port
+		(pt 208 48)
+		(output)
+		(text "R0_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R0_en" (rect 161 43 187 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "R1_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R1_en" (rect 161 59 187 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "R2_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R2_en" (rect 161 75 187 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "R3_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R3_en" (rect 161 91 187 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "R4_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R4_en" (rect 161 107 187 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "R5_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R5_en" (rect 161 123 187 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "R6_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R6_en" (rect 161 139 187 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "R7_en" (rect 0 0 31 12)(font "Arial" ))
+		(text "R7_en" (rect 161 155 187 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "s1[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s1[2..0]" (rect 156 171 187 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "s2[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s2[2..0]" (rect 156 187 187 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 208)
+		(output)
+		(text "s3[2..0]" (rect 0 0 37 12)(font "Arial" ))
+		(text "s3[2..0]" (rect 156 203 187 215)(font "Arial" ))
+		(line (pt 208 208)(pt 192 208)(line_width 3))
+	)
+	(port
+		(pt 208 224)
+		(output)
+		(text "s4" (rect 0 0 11 12)(font "Arial" ))
+		(text "s4" (rect 178 219 187 231)(font "Arial" ))
+		(line (pt 208 224)(pt 192 224))
+	)
+	(port
+		(pt 208 240)
+		(output)
+		(text "RAMd_wren" (rect 0 0 57 12)(font "Arial" ))
+		(text "RAMd_wren" (rect 139 235 187 247)(font "Arial" ))
+		(line (pt 208 240)(pt 192 240))
+	)
+	(port
+		(pt 208 256)
+		(output)
+		(text "RAMd_en" (rect 0 0 47 12)(font "Arial" ))
+		(text "RAMd_en" (rect 148 251 187 263)(font "Arial" ))
+		(line (pt 208 256)(pt 192 256))
+	)
+	(port
+		(pt 208 272)
+		(output)
+		(text "RAMi_en" (rect 0 0 43 12)(font "Arial" ))
+		(text "RAMi_en" (rect 151 267 187 279)(font "Arial" ))
+		(line (pt 208 272)(pt 192 272))
+	)
+	(drawing
+		(rectangle (rect 16 16 192 288))
+	)
+)
+(symbol
+	(rect 1024 304 1136 352)
+	(text "LPM_CONSTANT" (rect 4 0 125 16)(font "Arial" (font_size 10)))
+	(text "PLACEHOLDER" (rect 3 37 90 51)(font "Arial" (font_size 8)))
+	(port
+		(pt 112 32)
+		(output)
+		(text "result[LPM_WIDTH-1..0]" (rect 75 19 208 33)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 75 19 113 33)(font "Arial" (font_size 8)))
+		(line (pt 64 32)(pt 112 32)(line_width 3))
+	)
+	(parameter
+		"LPM_CVALUE"
+		"0"
+		"Unsigned value to which outputs will be set"
+		(type "PARAMETER_UNSIGNED_DEC")	)
+	(parameter
+		"LPM_WIDTH"
+		"16"
+		"Width of output, any integer > 0"
+		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" 
+	)
+	(drawing
+		(text "(cvalue)" (rect 21 26 68 40)(font "Arial" (font_size 8)))
+		(line (pt 16 24)(pt 64 24))
+		(line (pt 16 40)(pt 64 40))
+		(line (pt 64 40)(pt 64 24))
+		(line (pt 16 40)(pt 16 24))
+	)
+	(annotation_block (parameter)(rect 1136 304 1152 312))
+)
+(symbol
+	(rect 1008 504 1040 536)
+	(text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6)))
+	(text "inst" (rect 3 21 20 33)(font "Arial" )(invisible))
+	(port
+		(pt 16 0)
+		(output)
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(text "1" (rect 18 0 23 12)(font "Courier New" (bold))(invisible))
+		(line (pt 16 8)(pt 16 0))
+	)
+	(drawing
+		(line (pt 8 8)(pt 16 16))
+		(line (pt 16 16)(pt 24 8))
+		(line (pt 8 8)(pt 24 8))
+	)
+)
 (connector
 	(pt 504 416)
 	(pt 632 416)
@@ -1055,21 +1244,6 @@ refer to the applicable agreement for further details.
 	(pt 632 400)
 	(pt 464 400)
 )
-(connector
-	(text "s1[0]" (rect 602 128 625 145)(font "Intel Clear" ))
-	(pt 632 144)
-	(pt 592 144)
-)
-(connector
-	(text "s1[2]" (rect 602 160 625 177)(font "Intel Clear" ))
-	(pt 632 176)
-	(pt 592 176)
-)
-(connector
-	(text "s1[1]" (rect 602 144 625 161)(font "Intel Clear" ))
-	(pt 632 160)
-	(pt 592 160)
-)
 (connector
 	(pt 592 176)
 	(pt 592 160)
@@ -1132,26 +1306,6 @@ refer to the applicable agreement for further details.
 	(pt 448 624)
 	(bus)
 )
-(connector
-	(pt 1152 144)
-	(pt 1160 144)
-	(bus)
-)
-(connector
-	(pt 1160 304)
-	(pt 1168 304)
-	(bus)
-)
-(connector
-	(pt 1160 144)
-	(pt 1160 304)
-	(bus)
-)
-(connector
-	(pt 1288 792)
-	(pt 1288 320)
-	(bus)
-)
 (connector
 	(pt 1280 320)
 	(pt 1288 320)
@@ -1163,28 +1317,7 @@ refer to the applicable agreement for further details.
 	(bus)
 )
 (connector
-	(pt 856 144)
-	(pt 856 344)
-	(bus)
-)
-(connector
-	(pt 896 344)
-	(pt 856 344)
-	(bus)
-)
-(connector
-	(text "Rs1[15..0]" (rect 826 128 873 145)(font "Intel Clear" ))
-	(pt 816 144)
-	(pt 856 144)
-	(bus)
-)
-(connector
-	(pt 856 144)
-	(pt 936 144)
-	(bus)
-)
-(connector
-	(text "s4" (rect 1208 373 1225 383)(font "Intel Clear" )(vertical))
+	(text "s4" (rect 1203 368 1220 378)(font "Intel Clear" )(vertical))
 	(pt 1224 360)
 	(pt 1224 392)
 )
@@ -1238,45 +1371,16 @@ refer to the applicable agreement for further details.
 	(pt 744 -56)
 	(bus)
 )
-(connector
-	(pt 472 -112)
-	(pt 488 -112)
-	(bus)
-)
-(connector
-	(text "instr[10..0]" (rect 882 160 931 177)(font "Intel Clear" ))
-	(pt 936 176)
-	(pt 872 176)
-	(bus)
-)
-(connector
-	(text "instr[15..0]" (rect 864 -88 913 -71)(font "Intel Clear" ))
-	(pt 856 -72)
-	(pt 872 -72)
-	(bus)
-)
 (connector
 	(text "EXEC" (rect 783 -28 800 -3)(font "Intel Clear" )(vertical))
 	(pt 800 -32)
 	(pt 800 0)
 )
-(connector
-	(text "s3[2..0]" (rect 432 105 449 139)(font "Intel Clear" )(vertical))
-	(pt 448 104)
-	(pt 448 592)
-	(bus)
-)
 (connector
 	(pt 448 592)
 	(pt 448 608)
 	(bus)
 )
-(connector
-	(text "s2[2..0]" (rect 448 105 465 139)(font "Intel Clear" )(vertical))
-	(pt 464 104)
-	(pt 464 368)
-	(bus)
-)
 (connector
 	(pt 464 368)
 	(pt 464 384)
@@ -1287,12 +1391,6 @@ refer to the applicable agreement for further details.
 	(pt 480 128)
 	(bus)
 )
-(connector
-	(text "s1[2..0]" (rect 464 107 481 141)(font "Intel Clear" )(vertical))
-	(pt 480 128)
-	(pt 480 104)
-	(bus)
-)
 (connector
 	(pt 208 144)
 	(pt 504 144)
@@ -1308,26 +1406,6 @@ refer to the applicable agreement for further details.
 	(pt 208 -80)
 	(bus)
 )
-(connector
-	(text "RAMd_en" (rect 890 224 937 241)(font "Intel Clear" ))
-	(pt 936 240)
-	(pt 880 240)
-)
-(connector
-	(text "CLK" (rect 890 208 910 225)(font "Intel Clear" ))
-	(pt 936 224)
-	(pt 880 224)
-)
-(connector
-	(text "RAMd_wren" (rect 882 144 941 161)(font "Intel Clear" ))
-	(pt 936 160)
-	(pt 880 160)
-)
-(connector
-	(pt 872 -72)
-	(pt 872 176)
-	(bus)
-)
 (connector
 	(pt 504 192)
 	(pt 504 416)
@@ -1458,16 +1536,6 @@ refer to the applicable agreement for further details.
 	(pt 224 448)
 	(bus)
 )
-(connector
-	(pt 504 144)
-	(pt 504 192)
-	(bus)
-)
-(connector
-	(pt 432 192)
-	(pt 504 192)
-	(bus)
-)
 (connector
 	(pt 504 192)
 	(pt 632 192)
@@ -1538,12 +1606,6 @@ refer to the applicable agreement for further details.
 	(pt 632 288)
 	(bus)
 )
-(connector
-	(text " " (rect 549 288 551 305)(font "Intel Clear" ))
-	(pt 432 304)
-	(pt 616 304)
-	(bus)
-)
 (connector
 	(pt 616 304)
 	(pt 632 304)
@@ -1609,6 +1671,262 @@ refer to the applicable agreement for further details.
 	(pt 256 -16)
 	(pt 216 -16)
 )
+(connector
+	(text "Rs1[15..0]" (rect 826 128 873 145)(font "Intel Clear" ))
+	(pt 816 144)
+	(pt 856 144)
+	(bus)
+)
+(connector
+	(pt 896 344)
+	(pt 856 344)
+	(bus)
+)
+(connector
+	(pt 1168 304)
+	(pt 1160 304)
+	(bus)
+)
+(connector
+	(pt 1152 192)
+	(pt 1160 192)
+	(bus)
+)
+(connector
+	(pt 856 192)
+	(pt 936 192)
+	(bus)
+)
+(connector
+	(text "instr[10..0]" (rect 882 208 931 225)(font "Intel Clear" ))
+	(pt 936 224)
+	(pt 872 224)
+	(bus)
+)
+(connector
+	(text "RAMd_en" (rect 890 272 937 289)(font "Intel Clear" ))
+	(pt 936 288)
+	(pt 880 288)
+)
+(connector
+	(text "CLK" (rect 890 256 910 273)(font "Intel Clear" ))
+	(pt 936 272)
+	(pt 880 272)
+)
+(connector
+	(text "RAMd_wren" (rect 882 192 941 209)(font "Intel Clear" ))
+	(pt 936 208)
+	(pt 880 208)
+)
+(connector
+	(pt 872 -72)
+	(pt 872 224)
+	(bus)
+)
+(connector
+	(pt 856 144)
+	(pt 856 192)
+	(bus)
+)
+(connector
+	(pt 856 192)
+	(pt 856 344)
+	(bus)
+)
+(connector
+	(pt 1160 192)
+	(pt 1160 304)
+	(bus)
+)
+(connector
+	(pt 856 -72)
+	(pt 872 -72)
+	(bus)
+)
+(connector
+	(text "instr[15..0]" (rect 864 -88 913 -71)(font "Intel Clear" ))
+	(pt 872 -72)
+	(pt 912 -72)
+	(bus)
+)
+(connector
+	(pt 912 -72)
+	(pt 912 -120)
+	(bus)
+)
+(connector
+	(pt 912 -120)
+	(pt 968 -120)
+	(bus)
+)
+(connector
+	(text "COND" (rect 938 -104 967 -87)(font "Intel Clear" ))
+	(pt 968 -88)
+	(pt 928 -88)
+)
+(connector
+	(text "EXEC" (rect 938 -120 963 -103)(font "Intel Clear" ))
+	(pt 968 -104)
+	(pt 928 -104)
+)
+(connector
+	(text "R0_count" (rect 1186 -136 1230 -119)(font "Intel Clear" ))
+	(pt 1176 -120)
+	(pt 1224 -120)
+)
+(connector
+	(text "R0_en" (rect 1186 -120 1216 -103)(font "Intel Clear" ))
+	(pt 1176 -104)
+	(pt 1224 -104)
+)
+(connector
+	(text "R1_en" (rect 1186 -104 1216 -87)(font "Intel Clear" ))
+	(pt 1176 -88)
+	(pt 1224 -88)
+)
+(connector
+	(text "R2_en" (rect 1186 -88 1216 -71)(font "Intel Clear" ))
+	(pt 1176 -72)
+	(pt 1224 -72)
+)
+(connector
+	(text "R3_en" (rect 1186 -72 1216 -55)(font "Intel Clear" ))
+	(pt 1176 -56)
+	(pt 1224 -56)
+)
+(connector
+	(text "R4_en" (rect 1186 -56 1216 -39)(font "Intel Clear" ))
+	(pt 1176 -40)
+	(pt 1224 -40)
+)
+(connector
+	(text "R5_en" (rect 1186 -40 1216 -23)(font "Intel Clear" ))
+	(pt 1176 -24)
+	(pt 1224 -24)
+)
+(connector
+	(text "R6_en" (rect 1186 -24 1216 -7)(font "Intel Clear" ))
+	(pt 1176 -8)
+	(pt 1224 -8)
+)
+(connector
+	(text "R7_en" (rect 1186 -8 1216 9)(font "Intel Clear" ))
+	(pt 1176 8)
+	(pt 1224 8)
+)
+(connector
+	(text "s1[2..0]" (rect 1186 8 1220 25)(font "Intel Clear" ))
+	(pt 1176 24)
+	(pt 1224 24)
+	(bus)
+)
+(connector
+	(text "s2[2..0]" (rect 1186 24 1220 41)(font "Intel Clear" ))
+	(pt 1176 40)
+	(pt 1224 40)
+	(bus)
+)
+(connector
+	(text "s3[2..0]" (rect 1186 40 1220 57)(font "Intel Clear" ))
+	(pt 1176 56)
+	(pt 1224 56)
+	(bus)
+)
+(connector
+	(text "s4" (rect 1186 56 1196 73)(font "Intel Clear" ))
+	(pt 1176 72)
+	(pt 1224 72)
+)
+(connector
+	(text "RAMd_en" (rect 1186 88 1233 105)(font "Intel Clear" ))
+	(pt 1176 104)
+	(pt 1224 104)
+)
+(connector
+	(text "RAMi_en" (rect 1186 104 1229 121)(font "Intel Clear" ))
+	(pt 1176 120)
+	(pt 1224 120)
+)
+(connector
+	(text "RAMd_wren" (rect 1186 72 1245 89)(font "Intel Clear" ))
+	(pt 1176 88)
+	(pt 1240 88)
+)
+(connector
+	(pt 472 -112)
+	(pt 488 -112)
+	(bus)
+)
+(connector
+	(pt 1288 792)
+	(pt 1288 320)
+	(bus)
+)
+(connector
+	(text "<<__$DEF_ALIAS361>>" (rect 549 288 661 305)(font "Intel Clear" )(invisible))
+	(pt 432 304)
+	(pt 616 304)
+	(bus)
+)
+(connector
+	(text "s2[2..0]" (rect 446 103 463 137)(font "Intel Clear" )(vertical))
+	(pt 464 104)
+	(pt 464 368)
+	(bus)
+)
+(connector
+	(text "s1[2..0]" (rect 462 105 479 139)(font "Intel Clear" )(vertical))
+	(pt 480 128)
+	(pt 480 104)
+	(bus)
+)
+(connector
+	(text "s3[2..0]" (rect 429 102 446 136)(font "Intel Clear" )(vertical))
+	(pt 448 104)
+	(pt 448 592)
+	(bus)
+)
+(connector
+	(text "s1[0]" (rect 602 128 625 145)(font "Intel Clear" ))
+	(pt 632 144)
+	(pt 592 144)
+)
+(connector
+	(text "s1[1]" (rect 602 144 625 161)(font "Intel Clear" ))
+	(pt 632 160)
+	(pt 592 160)
+)
+(connector
+	(text "s1[2]" (rect 602 160 625 177)(font "Intel Clear" ))
+	(pt 632 176)
+	(pt 592 176)
+)
+(connector
+	(text "PC[15..0]" (rect 442 176 485 193)(font "Intel Clear" ))
+	(pt 432 192)
+	(pt 504 192)
+	(bus)
+)
+(connector
+	(text "PC[10..0]" (rect 488 145 505 188)(font "Intel Clear" )(vertical))
+	(pt 504 144)
+	(pt 504 192)
+	(bus)
+)
+(connector
+	(pt 1168 336)
+	(pt 1136 336)
+	(bus)
+)
+(connector
+	(pt 1024 504)
+	(pt 1024 488)
+)
+(connector
+	(text "COND" (rect 1024 472 1053 489)(font "Intel Clear" ))
+	(pt 1024 488)
+	(pt 1048 488)
+)
 (junction (pt 504 416))
 (junction (pt 504 192))
 (junction (pt 520 432))
@@ -1624,7 +1942,6 @@ refer to the applicable agreement for further details.
 (junction (pt 592 144))
 (junction (pt 448 592))
 (junction (pt 448 608))
-(junction (pt 856 144))
 (junction (pt 488 -72))
 (junction (pt 520 208))
 (junction (pt 536 224))
@@ -1640,3 +1957,5 @@ refer to the applicable agreement for further details.
 (junction (pt 160 384))
 (junction (pt 160 416))
 (junction (pt 160 448))
+(junction (pt 856 192))
+(junction (pt 872 -72))
diff --git a/CPUProject.qsf b/CPUProject.qsf
index cbd2662..793861b 100644
--- a/CPUProject.qsf
+++ b/CPUProject.qsf
@@ -38,13 +38,17 @@
 
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE AUTO
-set_global_assignment -name TOP_LEVEL_ENTITY test
+set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11  MAY 20, 2020"
 set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 set_global_assignment -name BDF_FILE CPUProject.bdf
 set_global_assignment -name BDF_FILE reg_file.bdf
 set_global_assignment -name BDF_FILE mux_8x16.bdf
@@ -52,10 +56,5 @@ set_global_assignment -name QIP_FILE ram_data.qip
 set_global_assignment -name QIP_FILE ram_instr.qip
 set_global_assignment -name BDF_FILE SM.bdf
 set_global_assignment -name VERILOG_FILE DECODE.v
-set_global_assignment -name MIF_FILE test.mif
-set_global_assignment -name BDF_FILE test.bdf
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
+set_global_assignment -name MIF_FILE data.mif
+set_global_assignment -name MIF_FILE instr.mif
\ No newline at end of file
diff --git a/DECODE.bsf b/DECODE.bsf
new file mode 100644
index 0000000..86b527f
--- /dev/null
+++ b/DECODE.bsf
@@ -0,0 +1,162 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 224 320)
+	(text "DECODE" (rect 5 0 47 12)(font "Arial" ))
+	(text "inst" (rect 8 288 20 300)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "instr[15..0]" (rect 0 0 40 12)(font "Arial" ))
+		(text "instr[15..0]" (rect 21 27 61 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "EXEC" (rect 0 0 27 12)(font "Arial" ))
+		(text "EXEC" (rect 21 43 48 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "COND_result" (rect 0 0 55 12)(font "Arial" ))
+		(text "COND_result" (rect 21 59 76 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 208 32)
+		(output)
+		(text "R0_count" (rect 0 0 40 12)(font "Arial" ))
+		(text "R0_count" (rect 147 27 187 39)(font "Arial" ))
+		(line (pt 208 32)(pt 192 32)(line_width 1))
+	)
+	(port
+		(pt 208 48)
+		(output)
+		(text "R0_en" (rect 0 0 28 12)(font "Arial" ))
+		(text "R0_en" (rect 159 43 187 55)(font "Arial" ))
+		(line (pt 208 48)(pt 192 48)(line_width 1))
+	)
+	(port
+		(pt 208 64)
+		(output)
+		(text "R1_en" (rect 0 0 27 12)(font "Arial" ))
+		(text "R1_en" (rect 160 59 187 71)(font "Arial" ))
+		(line (pt 208 64)(pt 192 64)(line_width 1))
+	)
+	(port
+		(pt 208 80)
+		(output)
+		(text "R2_en" (rect 0 0 28 12)(font "Arial" ))
+		(text "R2_en" (rect 159 75 187 87)(font "Arial" ))
+		(line (pt 208 80)(pt 192 80)(line_width 1))
+	)
+	(port
+		(pt 208 96)
+		(output)
+		(text "R3_en" (rect 0 0 28 12)(font "Arial" ))
+		(text "R3_en" (rect 159 91 187 103)(font "Arial" ))
+		(line (pt 208 96)(pt 192 96)(line_width 1))
+	)
+	(port
+		(pt 208 112)
+		(output)
+		(text "R4_en" (rect 0 0 29 12)(font "Arial" ))
+		(text "R4_en" (rect 158 107 187 119)(font "Arial" ))
+		(line (pt 208 112)(pt 192 112)(line_width 1))
+	)
+	(port
+		(pt 208 128)
+		(output)
+		(text "R5_en" (rect 0 0 28 12)(font "Arial" ))
+		(text "R5_en" (rect 159 123 187 135)(font "Arial" ))
+		(line (pt 208 128)(pt 192 128)(line_width 1))
+	)
+	(port
+		(pt 208 144)
+		(output)
+		(text "R6_en" (rect 0 0 28 12)(font "Arial" ))
+		(text "R6_en" (rect 159 139 187 151)(font "Arial" ))
+		(line (pt 208 144)(pt 192 144)(line_width 1))
+	)
+	(port
+		(pt 208 160)
+		(output)
+		(text "R7_en" (rect 0 0 28 12)(font "Arial" ))
+		(text "R7_en" (rect 159 155 187 167)(font "Arial" ))
+		(line (pt 208 160)(pt 192 160)(line_width 1))
+	)
+	(port
+		(pt 208 176)
+		(output)
+		(text "s1[2..0]" (rect 0 0 28 12)(font "Arial" ))
+		(text "s1[2..0]" (rect 159 171 187 183)(font "Arial" ))
+		(line (pt 208 176)(pt 192 176)(line_width 3))
+	)
+	(port
+		(pt 208 192)
+		(output)
+		(text "s2[2..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "s2[2..0]" (rect 158 187 187 199)(font "Arial" ))
+		(line (pt 208 192)(pt 192 192)(line_width 3))
+	)
+	(port
+		(pt 208 208)
+		(output)
+		(text "s3[2..0]" (rect 0 0 29 12)(font "Arial" ))
+		(text "s3[2..0]" (rect 158 203 187 215)(font "Arial" ))
+		(line (pt 208 208)(pt 192 208)(line_width 3))
+	)
+	(port
+		(pt 208 224)
+		(output)
+		(text "s4" (rect 0 0 10 12)(font "Arial" ))
+		(text "s4" (rect 177 219 187 231)(font "Arial" ))
+		(line (pt 208 224)(pt 192 224)(line_width 1))
+	)
+	(port
+		(pt 208 240)
+		(output)
+		(text "RAMd_wren" (rect 0 0 54 12)(font "Arial" ))
+		(text "RAMd_wren" (rect 133 235 187 247)(font "Arial" ))
+		(line (pt 208 240)(pt 192 240)(line_width 1))
+	)
+	(port
+		(pt 208 256)
+		(output)
+		(text "RAMd_en" (rect 0 0 44 12)(font "Arial" ))
+		(text "RAMd_en" (rect 143 251 187 263)(font "Arial" ))
+		(line (pt 208 256)(pt 192 256)(line_width 1))
+	)
+	(port
+		(pt 208 272)
+		(output)
+		(text "RAMi_en" (rect 0 0 41 12)(font "Arial" ))
+		(text "RAMi_en" (rect 146 267 187 279)(font "Arial" ))
+		(line (pt 208 272)(pt 192 272)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 192 288)(line_width 1))
+	)
+)
diff --git a/DECODE.v b/DECODE.v
index c2e193b..343e848 100644
--- a/DECODE.v
+++ b/DECODE.v
@@ -1,10 +1,10 @@
 module DECODE
 (
 	input [15:0] instr,
-	input FETCH,
 	input EXEC,
 	input COND_result,
 	output R0_count,
+	output R0_en,
 	output R1_en,
 	output R2_en,
 	output R3_en,
@@ -20,13 +20,69 @@ module DECODE
 	output RAMd_en,
 	output RAMi_en
 );
-	wire msb, ls, [reg_ls, addr, op, Rd, Rs1, Rs2;
-	assign msb = instr[15];		//MSB of the instruction word
-	assign ls = instr[14];		//LOAD or STORE bit
-	assign reg_ls = instr
-	
-	wire LOAD, STORE, UJMP, JMP, AND, OR, XOR, NOT, NND, NOR, XNR, MOV, ADD, ADC, ADO, SUB, SBC, SBO, MUL, MLA, MLS, MRT, LSL, LSR, ASR, ROR, RRC, NOP, STP;
-	assign LOAD = 
 
+	wire msb = instr[15];					//MSB of the instruction word
+	wire ls = instr[14];						//LOAD or STORE bit
+	wire [2:0] Rls = instr[13:11];		//Register in the LOAD/STORE operation
+	wire [10:0] addr = instr[10:0];		//Memory address in the LOAD/STORE operation
+	wire [5:0] op = instr[14:9];			//Opcode in regular instructions
+	wire [2:0] Rd = instr[8:6];			//Destination register in command
+	wire [2:0] Rs1 = instr[5:3];			//Source register 1 in command
+	wire [2:0] Rs2 = instr[2:0];			//Source register 2 in command
+	
+	//Different opcodes (refer to documentation):
+	wire LOAD = msb & ~ls;
+	wire STORE = msb & ls;
+	wire UJMP = ~op[5] & ~op[4] & ~op[3] & ~op[2];
+	wire JMP = (~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]);
+	wire AND = ~op[5] & ~op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
+	wire OR =  ~op[5] & ~op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
+	wire XOR = ~op[5] & ~op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
+	wire NOT = ~op[5] & ~op[4] &  op[3] &  op[2] &  op[1] &  op[0];
+	wire NND = ~op[5] &  op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
+	wire NOR = ~op[5] &  op[4] & ~op[3] & ~op[2] & ~op[1] &  op[0];
+	wire XNR = ~op[5] &  op[4] & ~op[3] & ~op[2] &  op[1] & ~op[0];
+	wire MOV = ~op[5] &  op[4] & ~op[3] & ~op[2] &  op[1] &  op[0];
+	wire ADD = ~op[5] &  op[4] & ~op[3] &  op[2] & ~op[1] & ~op[0];
+	wire ADC = ~op[5] &  op[4] & ~op[3] &  op[2] & ~op[1] &  op[0];
+	wire ADO = ~op[5] &  op[4] & ~op[3] &  op[2] &  op[1] & ~op[0];
+	wire SUB = ~op[5] &  op[4] &  op[3] & ~op[2] & ~op[1] & ~op[0];
+	wire SBC = ~op[5] &  op[4] &  op[3] & ~op[2] & ~op[1] &  op[0];
+	wire SBO = ~op[5] &  op[4] &  op[3] & ~op[2] &  op[1] & ~op[0];
+	wire MUL = ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] & ~op[0];
+	wire MLA = ~op[5] &  op[4] &  op[3] &  op[2] & ~op[1] &  op[0];
+	wire MLS = ~op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
+	wire MRT = ~op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
+	wire LSL =  op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] & ~op[0];
+	wire LSR =  op[5] & ~op[4] & ~op[3] & ~op[2] & ~op[1] &  op[0];
+	wire ASR =  op[5] & ~op[4] & ~op[3] & ~op[2] &  op[1] & ~op[0];
+	wire ROR =  op[5] & ~op[4] & ~op[3] &  op[2] & ~op[1] & ~op[0];
+	wire RRC =  op[5] & ~op[4] & ~op[3] &  op[2] & ~op[1] &  op[0];
+	wire NOP =  op[5] &  op[4] &  op[3] &  op[2] &  op[1] & ~op[0];
+	wire STP =  op[5] &  op[4] &  op[3] &  op[2] &  op[1] &  op[0];
+
+	assign R0_count = EXEC & (~(UJMP | JMP | STP));
+	assign R0_en = EXEC & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0] | UJMP | JMP & COND_result);
+	assign R1_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] & ~Rd[1] &  Rd[0] | LOAD & ~Rls[2] & ~Rls[1] &  Rls[0]);
+	assign R2_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] &  Rd[1] & ~Rd[0] | LOAD & ~Rls[2] &  Rls[1] & ~Rls[0]);
+	assign R3_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) & ~Rd[2] &  Rd[1] &  Rd[0] | LOAD & ~Rls[2] &  Rls[1] &  Rls[0]);
+	assign R4_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] & ~Rd[1] & ~Rd[0] | LOAD &  Rls[2] & ~Rls[1] & ~Rls[0]);
+	assign R5_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] & ~Rd[1] &  Rd[0] | LOAD &  Rls[2] & ~Rls[1] &  Rls[0]);
+	assign R6_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] &  Rd[1] & ~Rd[0] | LOAD &  Rls[2] &  Rls[1] & ~Rls[0]);
+	assign R7_en = EXEC & (~(UJMP | JMP | STORE | LOAD | NOP | STP) &  Rd[2] &  Rd[1] &  Rd[0] | LOAD &  Rls[2] &  Rls[1] &  Rls[0]);
+	assign s1[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]));
+	assign s1[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]));
+	assign s1[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]));
+	assign s2[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
+	assign s2[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
+	assign s2[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
+	assign s3[2] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[2]);
+	assign s3[1] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[1]);
+	assign s3[0] = EXEC & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rd[0]);
+	assign s4 = EXEC & ~(LOAD | STORE);
+	assign RAMd_wren = EXEC & STORE;
+	assign RAMd_en = EXEC & (STORE | LOAD);
+	assign RAMi_en = EXEC & ~STP;
+	
 endmodule
 	
\ No newline at end of file
diff --git a/data.mif b/data.mif
new file mode 100644
index 0000000..9fdeed9
--- /dev/null
+++ b/data.mif
@@ -0,0 +1,25 @@
+-- Copyright (C) 2018  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=16;
+DEPTH=2048;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	[000..7FF]  :   0000;
+END;
diff --git a/instr.mif b/instr.mif
new file mode 100644
index 0000000..9fdeed9
--- /dev/null
+++ b/instr.mif
@@ -0,0 +1,25 @@
+-- Copyright (C) 2018  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- Quartus Prime generated Memory Initialization File (.mif)
+
+WIDTH=16;
+DEPTH=2048;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	[000..7FF]  :   0000;
+END;
diff --git a/ram_data.v b/ram_data.v
index 41e23a4..7896cc9 100644
--- a/ram_data.v
+++ b/ram_data.v
@@ -89,7 +89,7 @@ module ram_data (
 	defparam
 		altsyncram_component.clock_enable_input_a = "NORMAL",
 		altsyncram_component.clock_enable_output_a = "BYPASS",
-		altsyncram_component.init_file = "test.mif",
+		altsyncram_component.init_file = "data.mif",
 		altsyncram_component.intended_device_family = "Cyclone IV E",
 		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
 		altsyncram_component.lpm_type = "altsyncram",
@@ -128,7 +128,7 @@ endmodule
 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING "test.mif"
+// Retrieval info: PRIVATE: MIFfilename STRING "data.mif"
 // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
@@ -145,7 +145,7 @@ endmodule
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif"
+// Retrieval info: CONSTANT: INIT_FILE STRING "data.mif"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
diff --git a/ram_instr.v b/ram_instr.v
index a52ca4c..9ac1882 100644
--- a/ram_instr.v
+++ b/ram_instr.v
@@ -89,6 +89,7 @@ module ram_instr (
 	defparam
 		altsyncram_component.clock_enable_input_a = "NORMAL",
 		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "instr.mif",
 		altsyncram_component.intended_device_family = "Cyclone IV E",
 		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
 		altsyncram_component.lpm_type = "altsyncram",
@@ -115,7 +116,7 @@ endmodule
 // Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
 // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
 // Retrieval info: PRIVATE: Clken NUMERIC "1"
@@ -127,7 +128,7 @@ endmodule
 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-// Retrieval info: PRIVATE: MIFfilename STRING ""
+// Retrieval info: PRIVATE: MIFfilename STRING "instr.mif"
 // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
@@ -144,6 +145,7 @@ endmodule
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "instr.mif"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
 // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"