Added LDR and STR to alu and set up data paths

Decoder changes remaining
This commit is contained in:
Aadi Desai 2020-06-10 14:02:15 +01:00
parent a249245102
commit a1cf89e644
5 changed files with 532 additions and 306 deletions

View file

@ -118,7 +118,7 @@ https://fpgasoftware.intel.com/eula.
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View file

@ -21,7 +21,7 @@ https://fpgasoftware.intel.com/eula.
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@ -1862,17 +1892,59 @@ https://fpgasoftware.intel.com/eula.
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(pt 936 288) (pt 936 288)
@ -2541,22 +2613,6 @@ https://fpgasoftware.intel.com/eula.
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@ -2727,11 +2783,71 @@ https://fpgasoftware.intel.com/eula.
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(pt 856 176) (pt 856 176)
(pt 856 192) (pt 856 192)
@ -2743,74 +2859,11 @@ https://fpgasoftware.intel.com/eula.
(bus) (bus)
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(pt 1184 432) (pt 1184 432)
@ -2818,9 +2871,19 @@ https://fpgasoftware.intel.com/eula.
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@ -2830,21 +2893,89 @@ https://fpgasoftware.intel.com/eula.
(bus) (bus)
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(junction (pt 856 192)) (junction (pt 856 192))
@ -2872,5 +3003,5 @@ https://fpgasoftware.intel.com/eula.
(junction (pt 560 496)) (junction (pt 560 496))
(junction (pt 576 512)) (junction (pt 576 512))
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(junction (pt 872 24))

56
alu.bsf
View file

@ -21,9 +21,9 @@ https://fpgasoftware.intel.com/eula.
*/ */
(header "symbol" (version "1.1")) (header "symbol" (version "1.1"))
(symbol (symbol
(rect 16 16 232 192) (rect 16 16 248 224)
(text "alu" (rect 5 0 15 12)(font "Arial" )) (text "alu" (rect 5 0 15 12)(font "Arial" ))
(text "inst" (rect 8 160 20 172)(font "Arial" )) (text "inst" (rect 8 192 20 204)(font "Arial" ))
(port (port
(pt 0 32) (pt 0 32)
(input) (input)
@ -81,48 +81,62 @@ https://fpgasoftware.intel.com/eula.
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) )

19
alu.v
View file

@ -1,13 +1,14 @@
module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, mul1, mul2, Rout, jump, carry, jumpflags); module alu (enable, Rs1, Rs2, Rd, opcode, mulresult, exec2, stackout, memdatain, mul1, mul2, Rout, jump, carry, jumpflags, memaddr);
input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
input signed [15:0] Rd; // input destination register
input signed [15:0] Rs1; // input source register 1 input signed [15:0] Rs1; // input source register 1
input signed [15:0] Rs2; // input source register 2 input signed [15:0] Rs2; // input source register 2
input signed [15:0] Rd; // input destination register
input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
input signed [31:0] mulresult; // 32-bit result from multiplier input signed [31:0] mulresult; // 32-bit result from multiplier
input exec2; // Input from state machine to indicate when to take in result from multiplication input exec2; // Input from state machine to indicate when to take in result from multiplication
input [15:0] stackout; // input from stack to be fed back to registers input [15:0] stackout; // input from stack to be fed back to registers
input signed [15:0] memdatain; // input data from RAMd
output reg signed [15:0] mul1; // first number to be multiplied output reg signed [15:0] mul1; // first number to be multiplied
output reg signed [15:0] mul2; // second number to be multiplied output reg signed [15:0] mul2; // second number to be multiplied
@ -15,6 +16,7 @@ output signed [15:0] Rout; // value to be saved to destination register
output jump; // tells decoder whether Jump condition is true output jump; // tells decoder whether Jump condition is true
output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
output [7:0] jumpflags; output [7:0] jumpflags;
output reg [10:0] memaddr; // address to load data from / store data to RAMd
reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
assign Rout = alusum [15:0]; assign Rout = alusum [15:0];
@ -164,8 +166,17 @@ always @(opcode, mulresult)
6'b101000: alusum = {1'b0, Rs1}; // PSH Push value to stack (Stack = Rs1) 6'b101000: alusum = {1'b0, Rs1}; // PSH Push value to stack (Stack = Rs1)
6'b101001: alusum = {1'b0, stackout}; // POP Pop value from stack (Rd = Stack) 6'b101001: alusum = {1'b0, stackout}; // POP Pop value from stack (Rd = Stack)
6'b101010: ; 6'b101010: begin // LDR Indirect Load (Rd = Mem[Rs1])
6'b101011: ; if(!exec2) begin
memaddr = Rs1[10:0];
end
else begin
alusum = {1'b0, memdatain};
end
end
6'b101011: begin // STR Indirect Store (Mem[Rd] = Rs1)
memaddr = Rd[10:0];
end
6'b111110: ; // NOP No Operation (Do Nothing for a cycle) 6'b111110: ; // NOP No Operation (Do Nothing for a cycle)
6'b111111: alusum = {1'b0, 16'h0000}; // STP Stop (Program Ends) 6'b111111: alusum = {1'b0, 16'h0000}; // STP Stop (Program Ends)