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Almost ready CPU

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Changed the MUX blocks into Verilog just cuz they look neater and are probably more optimised in the end. Added the LIFO stack. Working on decoder logic.
This commit is contained in:
Kacper 2020-06-07 15:08:34 +01:00
parent f6b3489884
commit 685f69a7cf
13 changed files with 1461 additions and 1934 deletions
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2219
CPUProject.bdf
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12
CPUProject.qsf
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@ -38,23 +38,19 @@
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject
set_global_assignment -name TOP_LEVEL_ENTITY mux_8x16
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name MIF_FILE LUTSquares.mif
set_global_assignment -name BDF_FILE mul8.bdf
set_global_assignment -name BDF_FILE abs.bdf
set_global_assignment -name BDF_FILE CPUProject.bdf
set_global_assignment -name BDF_FILE reg_file.bdf
set_global_assignment -name BDF_FILE mux_8x16.bdf
set_global_assignment -name QIP_FILE ram_data.qip
set_global_assignment -name QIP_FILE ram_instr.qip
set_global_assignment -name VERILOG_FILE DECODE.v
@ -64,6 +60,10 @@ set_global_assignment -name BDF_FILE mul16.bdf
set_global_assignment -name QIP_FILE LUT.qip
set_global_assignment -name VERILOG_FILE min.v
set_global_assignment -name VERILOG_FILE SM.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name BDF_FILE ALU_top.bdf
set_global_assignment -name VERILOG_FILE mux_8x16.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE mux_3x16.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

34
DECODE.v
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@ -21,7 +21,10 @@ module DECODE
output RAMd_en,
output RAMi_en,
output ALU_en,
output E2
output E2,
output stack_en,
output stack_rst,
output stack_rw
);
wire msb = instr[15]; //MSB of the instruction word
@ -41,21 +44,23 @@ module DECODE
wire MUL = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire MLA = ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
wire MLS = ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire PSH = op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & ~op[0];
wire POP = op[5] & ~op[4] & op[3] & ~op[2] & ~op[1] & op[0];
wire NOP = op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire STP = op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
assign R0_count = EXEC1 & (~(UJMP | JMP | STP));
assign R0_en = EXEC1 & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result) | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & ~Rls[1] & ~Rls[0];
assign R1_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & ~Rls[1] & Rls[0];
assign R2_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & Rls[1] & ~Rls[0];
assign R3_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & ~Rd[2] & Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & ~Rls[2] & Rls[1] & Rls[0];
assign R4_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & ~Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & ~Rls[1] & ~Rls[0];
assign R5_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & ~Rls[1] & Rls[0];
assign R6_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & Rls[1] & ~Rls[0];
assign R7_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP) & Rd[2] & Rd[1] & Rd[0] | EXEC2 & (LOAD | MUL | MLA | MLS) & Rls[2] & Rls[1] & Rls[0];
assign s1[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]));
assign s1[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]));
assign s1[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]));
assign R0_en = EXEC1 & (~(STORE | NOP | STP) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result) | EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & ~Rd[0];
assign R1_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & Rd[0];
assign R2_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & LOAD & ~Rls[2] & Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & ~Rd[0];
assign R3_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & Rd[0] | EXEC2 & LOAD & ~Rls[2] & Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & Rd[0];
assign R4_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & ~Rd[0] | EXEC2 & LOAD & Rls[2] & ~Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & ~Rd[0];
assign R5_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & LOAD & Rls[2] & ~Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & Rd[0];
assign R6_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & LOAD & Rls[2] & Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & ~Rd[0];
assign R7_en = EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & Rd[0] | EXEC2 & LOAD & Rls[2] & Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & Rd[0];
assign s1[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2]));
assign s1[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1]));
assign s1[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0]));
assign s2[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[2]);
assign s2[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[1]);
assign s2[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP)) & Rs2[0]);
@ -67,7 +72,10 @@ module DECODE
assign RAMd_en = EXEC1 & (STORE | LOAD);
assign RAMi_en = EXEC1 & ~STP | EXEC2 & (LOAD | MUL | MLA | MLS);
assign ALU_en = LOAD | STORE;
assign E2 = EXEC1 & (LOAD | MUL | MLA | MLS);
assign E2 = EXEC1 & (LOAD | MUL | MLA | MLS | POP);
assign stack_en = (EXEC1 & PSH) | POP;
assign stack_rst = STP;
assign stack_rw = POP;
endmodule

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Initial MUX 8x16 design.PNG Normal file
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85
LIFOstack.bsf Normal file
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@ -0,0 +1,85 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 200 160)
(text "LIFOstack" (rect 5 0 47 12)(font "Arial" ))
(text "inst" (rect 8 128 20 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "Din[15..0]" (rect 0 0 36 12)(font "Arial" ))
(text "Din[15..0]" (rect 21 27 57 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clk" (rect 0 0 10 12)(font "Arial" ))
(text "clk" (rect 21 43 31 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "en" (rect 0 0 9 12)(font "Arial" ))
(text "en" (rect 21 59 30 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 0 80)
(input)
(text "rst" (rect 0 0 10 12)(font "Arial" ))
(text "rst" (rect 21 75 31 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "rw" (rect 0 0 9 12)(font "Arial" ))
(text "rw" (rect 21 91 30 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 184 32)
(output)
(text "Dout[15..0]" (rect 0 0 42 12)(font "Arial" ))
(text "Dout[15..0]" (rect 121 27 163 39)(font "Arial" ))
(line (pt 184 32)(pt 168 32)(line_width 3))
)
(port
(pt 184 48)
(output)
(text "empty" (rect 0 0 25 12)(font "Arial" ))
(text "empty" (rect 138 43 163 55)(font "Arial" ))
(line (pt 184 48)(pt 168 48)(line_width 1))
)
(port
(pt 184 64)
(output)
(text "full" (rect 0 0 10 12)(font "Arial" ))
(text "full" (rect 153 59 163 71)(font "Arial" ))
(line (pt 184 64)(pt 168 64)(line_width 1))
)
(drawing
(rectangle (rect 16 16 168 128)(line_width 1))
)
)

14
LIFOstack.v
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@ -3,39 +3,39 @@ module LIFOstack (Din, clk, en, rst, rw, Dout, empty, full);
input [15:0] Din; // Data being fed to stack
input clk; // clock signal input
input en; // disable stack when not in use
input rst; // reset pin to clear and reinitialise stack
input rst; // reset pin to clear and reinitialise stack (active high)
input rw; // 0: read, 1: write
output reg [15:0] Dout; // Data being pulled from stack
output reg empty; // goes high to indicate SP is at 0
output reg full; // goes high to indicate SP is at (slots)
reg [15:0] stack_mem [3:0];
reg [4:0] SP; // Points to slot to save next value to
integer i;
reg [15:0] mem [3:0];
always @ (posedge clk) begin
if (!en); // if not enabled, ignore this cycle
else begin
if (rst) begin // if rst is high, clear memory and reset pointers/outputs
Dout = 16'h0000;
SP = 4'b0000;
empty = 1'b1;
Dout = 16'h0000;
for (i = 0; i < 16; i = i + 1) begin
stack_mem[i] = 16'h0000;
mem[i] = 16'h0000;
end
end
else begin
if (!full && rw) begin // Write when NOT full & Writing
stack_mem[SP] = Din; // Store data into current slot
mem[SP] = Din; // Store data into current slot
SP = SP + 1'b1; // Increment stack pointer to next empty slot
full = (SP == 5'b10000) ? 1 : 0; // Stack is full if SP is (slots)
empty = 1'b0; // Stack is never empty after a push
end
else if (!empty && !rw) begin // Read when NOT empty & reading
SP = SP - 1'b1; // Decrement stack pointer to last filled slot
Dout = stack_mem[SP]; // Output data from last filled slot
stack_mem[SP] = 16'h0000; // Clear slot after setting output
Dout = mem[SP]; // Output data from last filled slot
mem[SP] = 16'h0000; // Clear slot after setting output
full = 1'b0; // Stack is never full after a pop
empty = (SP == 5'b00000) ? 1 : 0; // Stack is empty if SP is 0
end

46
LIFOstack.v.bak Normal file
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@ -0,0 +1,46 @@
module LIFOstack (Din, clk, en, rst, rw, Dout, empty, full);
input [15:0] Din; // Data being fed to stack
input clk; // clock signal input
input en; // disable stack when not in use
input rst; // reset pin to clear and reinitialise stack
input rw; // 0: read, 1: write
output reg [15:0] Dout; // Data being pulled from stack
output reg empty; // goes high to indicate SP is at 0
output reg full; // goes high to indicate SP is at (slots)
reg [15:0] stack_mem [3:0];
reg [4:0] SP; // Points to slot to save next value to
integer i;
always @ (posedge clk) begin
if (!en); // if not enabled, ignore this cycle
else begin
if (rst) begin // if rst is high, clear memory and reset pointers/outputs
SP = 4'b0000;
empty = 1'b1;
Dout = 16'h0000;
for (i = 0; i < 16; i = i + 1) begin
stack_mem[i] = 16'h0000;
end
end
else begin
if (!full && rw) begin // Write when NOT full & Writing
stack_mem[SP] = Din; // Store data into current slot
SP = SP + 1'b1; // Increment stack pointer to next empty slot
full = (SP == 5'b10000) ? 1 : 0; // Stack is full if SP is (slots)
empty = 1'b0; // Stack is never empty after a push
end
else if (!empty && !rw) begin // Read when NOT empty & reading
SP = SP - 1'b1; // Decrement stack pointer to last filled slot
Dout = stack_mem[SP]; // Output data from last filled slot
stack_mem[SP] = 16'h0000; // Clear slot after setting output
full = 1'b0; // Stack is never full after a pop
empty = (SP == 5'b00000) ? 1 : 0; // Stack is empty if SP is 0
end
end
end
end
endmodule

64
mux_3x16.bsf Normal file
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@ -0,0 +1,64 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 200 128)
(text "mux_3x16" (rect 5 0 46 12)(font "Arial" ))
(text "inst" (rect 8 96 20 108)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "s[1..0]" (rect 0 0 23 12)(font "Arial" ))
(text "s[1..0]" (rect 21 27 44 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "in0[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in0[15..0]" (rect 21 43 55 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "in1[15..0]" (rect 0 0 33 12)(font "Arial" ))
(text "in1[15..0]" (rect 21 59 54 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "in2[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in2[15..0]" (rect 21 75 55 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 3))
)
(port
(pt 184 32)
(output)
(text "result[15..0]" (rect 0 0 44 12)(font "Arial" ))
(text "result[15..0]" (rect 119 27 163 39)(font "Arial" ))
(line (pt 184 32)(pt 168 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 168 96)(line_width 1))
)
)

18
mux_3x16.v Normal file
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@ -0,0 +1,18 @@
module mux_3x16 (s, in0, in1, in2, result);
input [1:0]s;
input [15:0]in0;
input [15:0]in1;
input [15:0]in2;
output reg [15:0]result;
always @(*) begin
case(s)
2'b00: result = in0;
2'b01: result = in1;
2'b10: result = in2;
endcase
end
endmodule

784
mux_8x16.bdf
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@ -1,784 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "graphic" (version "1.4"))
(pin
(input)
(rect 104 64 272 80)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
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)
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)
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(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
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(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
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)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
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(rect 104 208 272 224)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in1[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
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(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 296 272 312)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in2[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 328 272 344)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in3[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 416 272 432)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in4[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 448 272 464)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in5[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 536 272 552)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in6[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(input)
(rect 104 568 272 584)
(text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6)))
(text "in7[15..0]" (rect 5 0 49 17)(font "Intel Clear" ))
(pt 168 8)
(drawing
(line (pt 84 12)(pt 109 12))
(line (pt 84 4)(pt 109 4))
(line (pt 113 8)(pt 168 8))
(line (pt 84 12)(pt 84 4))
(line (pt 109 4)(pt 113 8))
(line (pt 109 12)(pt 113 8))
)
(text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6)))
)
(pin
(output)
(rect 872 192 1048 208)
(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
(text "result[15..0]" (rect 90 0 149 12)(font "Arial" ))
(pt 0 8)
(drawing
(line (pt 0 8)(pt 52 8))
(line (pt 52 4)(pt 78 4))
(line (pt 52 12)(pt 78 12))
(line (pt 52 12)(pt 52 4))
(line (pt 78 4)(pt 82 8))
(line (pt 82 8)(pt 78 12))
(line (pt 78 12)(pt 82 8))
)
)
(symbol
(rect 312 272 424 360)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst5" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 272 448 288))
)
(symbol
(rect 312 392 424 480)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst6" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 392 448 408))
)
(symbol
(rect 312 512 424 600)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst7" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 512 448 528))
)
(symbol
(rect 528 152 640 240)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst8" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 640 152 664 168))
)
(symbol
(rect 528 272 640 360)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst9" (rect 3 77 25 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 640 272 664 288))
)
(symbol
(rect 720 152 832 240)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst10" (rect 3 77 31 94)(font "Intel Clear" ))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
)
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 832 152 856 168))
)
(symbol
(rect 312 152 424 240)
(text "BUSMUX" (rect 28 0 91 16)(font "Arial" (font_size 10)))
(text "inst" (rect 3 77 23 91)(font "Arial" (font_size 8)))
(port
(pt 0 64)
(input)
(text "datab[WIDTH-1..0]" (rect 6 51 108 65)(font "Arial" (font_size 8)))
(text "datab[]" (rect 6 51 44 65)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 44 64)(line_width 3))
)
(port
(pt 56 88)
(input)
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(text "sel" (rect 59 70 75 84)(font "Arial" (font_size 8)))
(line (pt 56 88)(pt 56 72))
)
(port
(pt 0 32)
(input)
(text "dataa[WIDTH-1..0]" (rect 6 19 108 33)(font "Arial" (font_size 8)))
(text "dataa[]" (rect 6 19 44 33)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 44 32)(line_width 3))
)
(port
(pt 112 48)
(output)
(text "result[WIDTH-1..0]" (rect 75 35 177 49)(font "Arial" (font_size 8)))
(text "result[]" (rect 75 35 113 49)(font "Arial" (font_size 8)))
(line (pt 68 48)(pt 112 48)(line_width 3))
)
(parameter
"WIDTH"
"16"
"Width of I/O, any integer > 0"
" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64"
(type "PARAMETER_SIGNED_DEC") )
(drawing
(text "0" (rect 52 31 56 41)(font "Arial" (font_size 6)))
(text "1" (rect 52 55 56 65)(font "Arial" (font_size 6)))
(line (pt 68 64)(pt 68 32))
(line (pt 44 80)(pt 44 16))
(line (pt 44 16)(pt 68 32))
(line (pt 44 80)(pt 68 64))
)
(annotation_block (parameter)(rect 424 152 456 176))
)
(connector
(pt 424 200)
(pt 440 200)
(bus)
)
(connector
(pt 456 320)
(pt 424 320)
(bus)
)
(connector
(pt 424 440)
(pt 472 440)
(bus)
)
(connector
(pt 424 560)
(pt 488 560)
(bus)
)
(connector
(pt 656 184)
(pt 720 184)
(bus)
)
(connector
(pt 440 200)
(pt 440 184)
(bus)
)
(connector
(pt 456 320)
(pt 456 216)
(bus)
)
(connector
(pt 656 200)
(pt 640 200)
(bus)
)
(connector
(pt 656 184)
(pt 656 200)
(bus)
)
(connector
(pt 456 216)
(pt 528 216)
(bus)
)
(connector
(pt 440 184)
(pt 528 184)
(bus)
)
(connector
(pt 472 440)
(pt 472 304)
(bus)
)
(connector
(pt 488 560)
(pt 488 336)
(bus)
)
(connector
(pt 488 336)
(pt 528 336)
(bus)
)
(connector
(pt 472 304)
(pt 528 304)
(bus)
)
(connector
(pt 720 216)
(pt 672 216)
(bus)
)
(connector
(pt 640 320)
(pt 672 320)
(bus)
)
(connector
(pt 672 216)
(pt 672 320)
(bus)
)
(connector
(pt 368 240)
(pt 368 256)
)
(connector
(pt 368 256)
(pt 296 256)
)
(connector
(pt 368 360)
(pt 368 376)
)
(connector
(pt 368 376)
(pt 296 376)
)
(connector
(pt 296 608)
(pt 368 608)
)
(connector
(pt 368 608)
(pt 368 600)
)
(connector
(pt 368 496)
(pt 296 496)
)
(connector
(pt 296 496)
(pt 296 608)
)
(connector
(pt 368 496)
(pt 368 480)
)
(connector
(pt 296 376)
(pt 296 496)
)
(connector
(pt 584 240)
(pt 584 256)
)
(connector
(pt 512 256)
(pt 584 256)
)
(connector
(pt 512 376)
(pt 584 376)
)
(connector
(pt 584 360)
(pt 584 376)
)
(connector
(pt 272 184)
(pt 312 184)
(bus)
)
(connector
(pt 312 216)
(pt 272 216)
(bus)
)
(connector
(pt 312 304)
(pt 272 304)
(bus)
)
(connector
(pt 312 336)
(pt 272 336)
(bus)
)
(connector
(pt 312 424)
(pt 272 424)
(bus)
)
(connector
(pt 312 456)
(pt 272 456)
(bus)
)
(connector
(pt 312 544)
(pt 272 544)
(bus)
)
(connector
(pt 312 576)
(pt 272 576)
(bus)
)
(connector
(pt 272 72)
(pt 296 72)
)
(connector
(pt 296 72)
(pt 296 256)
)
(connector
(pt 296 256)
(pt 296 376)
)
(connector
(pt 272 88)
(pt 512 88)
)
(connector
(pt 512 88)
(pt 512 256)
)
(connector
(pt 512 256)
(pt 512 376)
)
(connector
(pt 776 240)
(pt 776 256)
)
(connector
(pt 272 104)
(pt 704 104)
)
(connector
(pt 776 256)
(pt 704 256)
)
(connector
(pt 704 104)
(pt 704 256)
)
(connector
(pt 832 200)
(pt 872 200)
(bus)
)
(junction (pt 296 496))
(junction (pt 296 376))
(junction (pt 296 256))
(junction (pt 512 256))

70
mux_8x16.bsf
View file

@ -18,96 +18,82 @@ the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 200 240)
(text "mux_8x16" (rect 5 0 67 19)(font "Intel Clear" (font_size 8)))
(text "inst" (rect 8 203 24 220)(font "Intel Clear" ))
(rect 16 16 200 224)
(text "mux_8x16" (rect 5 0 46 12)(font "Arial" ))
(text "inst" (rect 8 192 20 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "s0" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
(text "s0" (rect 21 27 35 46)(font "Intel Clear" (font_size 8)))
(line (pt 0 32)(pt 16 32))
(text "s[2..0]" (rect 0 0 24 12)(font "Arial" ))
(text "s[2..0]" (rect 21 27 45 39)(font "Arial" ))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "s1" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
(text "s1" (rect 21 43 35 62)(font "Intel Clear" (font_size 8)))
(line (pt 0 48)(pt 16 48))
(text "in0[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in0[15..0]" (rect 21 43 55 55)(font "Arial" ))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "s2" (rect 0 0 14 19)(font "Intel Clear" (font_size 8)))
(text "s2" (rect 21 59 35 78)(font "Intel Clear" (font_size 8)))
(line (pt 0 64)(pt 16 64))
(text "in1[15..0]" (rect 0 0 33 12)(font "Arial" ))
(text "in1[15..0]" (rect 21 59 54 71)(font "Arial" ))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "in0[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in0[15..0]" (rect 21 75 78 94)(font "Intel Clear" (font_size 8)))
(text "in2[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in2[15..0]" (rect 21 75 55 87)(font "Arial" ))
(line (pt 0 80)(pt 16 80)(line_width 3))
)
(port
(pt 0 96)
(input)
(text "in1[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in1[15..0]" (rect 21 91 78 110)(font "Intel Clear" (font_size 8)))
(text "in3[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in3[15..0]" (rect 21 91 55 103)(font "Arial" ))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "in2[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in2[15..0]" (rect 21 107 78 126)(font "Intel Clear" (font_size 8)))
(text "in4[15..0]" (rect 0 0 35 12)(font "Arial" ))
(text "in4[15..0]" (rect 21 107 56 119)(font "Arial" ))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "in3[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in3[15..0]" (rect 21 123 78 142)(font "Intel Clear" (font_size 8)))
(text "in5[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in5[15..0]" (rect 21 123 55 135)(font "Arial" ))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 144)
(input)
(text "in4[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in4[15..0]" (rect 21 139 78 158)(font "Intel Clear" (font_size 8)))
(text "in6[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in6[15..0]" (rect 21 139 55 151)(font "Arial" ))
(line (pt 0 144)(pt 16 144)(line_width 3))
)
(port
(pt 0 160)
(input)
(text "in5[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in5[15..0]" (rect 21 155 78 174)(font "Intel Clear" (font_size 8)))
(text "in7[15..0]" (rect 0 0 34 12)(font "Arial" ))
(text "in7[15..0]" (rect 21 155 55 167)(font "Arial" ))
(line (pt 0 160)(pt 16 160)(line_width 3))
)
(port
(pt 0 176)
(input)
(text "in6[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in6[15..0]" (rect 21 171 78 190)(font "Intel Clear" (font_size 8)))
(line (pt 0 176)(pt 16 176)(line_width 3))
)
(port
(pt 0 192)
(input)
(text "in7[15..0]" (rect 0 0 57 19)(font "Intel Clear" (font_size 8)))
(text "in7[15..0]" (rect 21 187 78 206)(font "Intel Clear" (font_size 8)))
(line (pt 0 192)(pt 16 192)(line_width 3))
)
(port
(pt 184 32)
(output)
(text "result[15..0]" (rect 0 0 71 19)(font "Intel Clear" (font_size 8)))
(text "result[15..0]" (rect 92 27 163 46)(font "Intel Clear" (font_size 8)))
(text "result[15..0]" (rect 0 0 44 12)(font "Arial" ))
(text "result[15..0]" (rect 119 27 163 39)(font "Arial" ))
(line (pt 184 32)(pt 168 32)(line_width 3))
)
(drawing
(rectangle (rect 16 16 168 208))
(rectangle (rect 16 16 168 192)(line_width 1))
)
)

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module mux_8x16 (s, in0, in1, in2, in3, in4, in5, in6, in7, result);
input [2:0]s;
input [15:0]in0;
input [15:0]in1;
input [15:0]in2;
input [15:0]in3;
input [15:0]in4;
input [15:0]in5;
input [15:0]in6;
input [15:0]in7;
output reg [15:0]result;
always @(*) begin
case(s)
3'b000: result = in0;
3'b001: result = in1;
3'b010: result = in2;
3'b011: result = in3;
3'b100: result = in4;
3'b101: result = in5;
3'b110: result = in6;
3'b111: result = in7;
endcase
end
endmodule

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module mux_8x16 (s, in0, in1, in2, in3, in4, in5, in6, in7, result);
input [2:0]s;
input [15:0]in0, [15:0]in1, [15:0]in2, [15:0]in3, [15:0]in4, [15:0]in5, [15:0]in6, [15:0]in7;
output [15:0]result;
always @(*) begin
case(s)
3'b000: result = in0;
3'b001: result = in1;
3'b010: result = in2;
3'b011: result = in3;
3'b100: result = in4;
3'b101: result = in5;
3'b110: result = in6;
3'b111: result = in7;
endcase
end
endmodule