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The multiplier uses a 2 port ROM. For some reason, I cannot generate one on my machine and so I cannot change the exusting LUT ROM to remove the register outputs. If someone else can do it (Ben), that would be great.
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Kacper 2020-06-07 23:23:13 +01:00
parent b527d5e77d
commit 3d9ea175cd
5 changed files with 624 additions and 225 deletions
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(line (pt 96 43)(pt 96 55))
(line (pt 96 55)(pt 88 55))
(line (pt 88 55)(pt 88 43))
(line (pt 88 50)(pt 90 52))
(line (pt 90 52)(pt 88 54))
(line (pt 80 52)(pt 88 52))
(line (pt 96 48)(pt 104 48))
(line (pt 88 59)(pt 96 59))
(line (pt 96 59)(pt 96 71))
(line (pt 96 71)(pt 88 71))
(line (pt 88 71)(pt 88 59))
(line (pt 88 66)(pt 90 68))
(line (pt 90 68)(pt 88 70))
(line (pt 80 68)(pt 88 68))
(line (pt 96 64)(pt 104 64)(line_width 3))
(line (pt 80 112)(pt 80 36))
(line (pt 0 0)(pt 217 0))
(line (pt 217 0)(pt 217 146))
(line (pt 0 146)(pt 217 146))
(line (pt 0 0)(pt 0 146))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
(line (pt 0 0)(pt 0 0))
)
)
(connector (connector
(pt 856 192) (pt 856 192)
(pt 936 192) (pt 936 192)
@ -1478,12 +1846,6 @@ refer to the applicable agreement for further details.
(pt 936 416) (pt 936 416)
(pt 880 416) (pt 880 416)
) )
(connector
(text "instr[15..10]" (rect 890 384 945 401)(font "Intel Clear" ))
(pt 936 400)
(pt 880 400)
(bus)
)
(connector (connector
(text "CARRY" (rect 1122 352 1157 369)(font "Intel Clear" )) (text "CARRY" (rect 1122 352 1157 369)(font "Intel Clear" ))
(pt 1120 368) (pt 1120 368)
@ -1865,22 +2227,12 @@ refer to the applicable agreement for further details.
(pt 592 592) (pt 592 592)
(bus) (bus)
) )
(connector
(pt 1120 336)
(pt 1216 336)
(bus)
)
(connector (connector
(text "s4[1..0]" (rect 1186 288 1220 305)(font "Intel Clear" )) (text "s4[1..0]" (rect 1186 288 1220 305)(font "Intel Clear" ))
(pt 1216 304) (pt 1216 304)
(pt 1176 304) (pt 1176 304)
(bus) (bus)
) )
(connector
(pt 1400 304)
(pt 1416 304)
(bus)
)
(connector (connector
(pt 136 792) (pt 136 792)
(pt 1416 792) (pt 1416 792)
@ -1912,11 +2264,6 @@ refer to the applicable agreement for further details.
(pt 936 576) (pt 936 576)
(pt 880 576) (pt 880 576)
) )
(connector
(pt 1120 512)
(pt 1184 512)
(bus)
)
(connector (connector
(pt 1184 352) (pt 1184 352)
(pt 1184 512) (pt 1184 512)
@ -1937,11 +2284,6 @@ refer to the applicable agreement for further details.
(pt 1160 320) (pt 1160 320)
(bus) (bus)
) )
(connector
(pt 1216 320)
(pt 1160 320)
(bus)
)
(connector (connector
(text "R0_count" (rect 1386 -120 1430 -103)(font "Intel Clear" )) (text "R0_count" (rect 1386 -120 1430 -103)(font "Intel Clear" ))
(pt 1376 -104) (pt 1376 -104)
@ -2157,16 +2499,6 @@ refer to the applicable agreement for further details.
(pt 1176 616) (pt 1176 616)
(pt 1232 616) (pt 1232 616)
) )
(connector
(pt 1416 304)
(pt 1416 496)
(bus)
)
(connector
(pt 1416 496)
(pt 1416 792)
(bus)
)
(connector (connector
(text "PC[15..0]" (rect 1186 648 1229 665)(font "Intel Clear" )) (text "PC[15..0]" (rect 1186 648 1229 665)(font "Intel Clear" ))
(pt 1232 664) (pt 1232 664)
@ -2313,10 +2645,73 @@ refer to the applicable agreement for further details.
(bus) (bus)
) )
(connector (connector
(text "instr[15..0]" (rect 882 -120 931 -103)(font "Intel Clear" ))
(pt 872 -104) (pt 872 -104)
(pt 1168 -104) (pt 1168 -104)
(bus) (bus)
) )
(connector
(text "ALU_out[15..0]" (rect 1130 320 1200 337)(font "Intel Clear" ))
(pt 1120 336)
(pt 1216 336)
(bus)
)
(connector
(pt 1400 304)
(pt 1416 304)
(bus)
)
(connector
(pt 1416 304)
(pt 1416 496)
(bus)
)
(connector
(pt 1416 496)
(pt 1416 792)
(bus)
)
(connector
(text "stack_out[15..0]" (rect 1122 496 1197 513)(font "Intel Clear" ))
(pt 1120 512)
(pt 1184 512)
(bus)
)
(connector
(text "RAMd_out[15..0]" (rect 1170 304 1250 321)(font "Intel Clear" ))
(pt 1216 320)
(pt 1160 320)
(bus)
)
(connector
(text "ALU_out[15..0]" (rect 1448 264 1518 281)(font "Intel Clear" ))
(pt 1440 280)
(pt 1512 280)
(bus)
)
(connector
(text "stack_out[15..0]" (rect 1450 296 1525 313)(font "Intel Clear" ))
(pt 1512 312)
(pt 1440 312)
(bus)
)
(connector
(text "RAMd_out[15..0]" (rect 1442 280 1522 297)(font "Intel Clear" ))
(pt 1512 296)
(pt 1432 296)
(bus)
)
(connector
(text "COND" (rect 1450 312 1479 329)(font "Intel Clear" ))
(pt 1512 328)
(pt 1440 328)
)
(connector
(text "instr[14..9]" (rect 890 384 939 401)(font "Intel Clear" ))
(pt 936 400)
(pt 880 400)
(bus)
)
(junction (pt 856 192)) (junction (pt 856 192))
(junction (pt 136 320)) (junction (pt 136 320))
(junction (pt 136 352)) (junction (pt 136 352))

14
CPUProject.qsf
View file

@ -38,16 +38,13 @@
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE AUTO set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY CPUProject set_global_assignment -name TOP_LEVEL_ENTITY test
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020" set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:38:11 MAY 20, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE LIFOstack.v set_global_assignment -name VERILOG_FILE LIFOstack.v
set_global_assignment -name VERILOG_FILE alu.v set_global_assignment -name VERILOG_FILE alu.v
set_global_assignment -name MIF_FILE LUTSquares.mif set_global_assignment -name MIF_FILE LUTSquares.mif
@ -68,4 +65,11 @@ set_global_assignment -name BDF_FILE ALU_top.bdf
set_global_assignment -name VERILOG_FILE mux_8x16.v set_global_assignment -name VERILOG_FILE mux_8x16.v
set_global_assignment -name VERILOG_FILE mux_3x16.v set_global_assignment -name VERILOG_FILE mux_3x16.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name BDF_FILE test.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name QIP_FILE LUT1.qip
set_global_assignment -name QIP_FILE LUT4.qip

BIN
CPUProject.qws
View file

Binary file not shown.

38
DECODE.v
View file

@ -41,7 +41,7 @@ module DECODE
wire LOAD = msb & ~ls; wire LOAD = msb & ~ls;
wire STORE = msb & ls; wire STORE = msb & ls;
wire UJMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2]; wire UJMP = ~msb & ~op[5] & ~op[4] & ~op[3] & ~op[2];
wire JMP = ~msb & (~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]); wire JMP = ~msb & ((~op[5] & ~op[4] & ~op[3] & op[2]) | (~op[5] & ~op[4] & op[3] & ~op[2]));
wire MUL = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0]; wire MUL = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & ~op[0];
wire MLA = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0]; wire MLA = ~msb & ~op[5] & op[4] & op[3] & op[2] & ~op[1] & op[0];
wire MLS = ~msb & ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0]; wire MLS = ~msb & ~op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
@ -50,24 +50,24 @@ module DECODE
wire NOP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0]; wire NOP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & ~op[0];
wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0]; wire STP = ~msb & op[5] & op[4] & op[3] & op[2] & op[1] & op[0];
assign R0_count = EXEC1 & (~(UJMP | JMP & ~COND_result | STP)); assign R0_count = EXEC1 & (~(UJMP | (JMP & ~COND_result) | STP));
assign R0_en = EXEC1 & (~(STORE | NOP | STP | LOAD) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result) | EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & ~Rd[0]; assign R0_en = (EXEC1 & (~(STORE | NOP | STP | LOAD) & ~Rd[2] & ~Rd[1] & ~Rd[0] | UJMP | JMP & COND_result)) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & ~Rd[0]);
assign R1_en = ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & Rd[0]; assign R1_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & ~Rd[1] & Rd[0]);
assign R2_en = ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & LOAD & ~Rls[2] & Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & ~Rd[0]; assign R2_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & ~Rd[0]);
assign R3_en = ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & Rd[0] | EXEC2 & LOAD & ~Rls[2] & Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & Rd[0]; assign R3_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & ~Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LOAD & ~Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & ~Rd[2] & Rd[1] & Rd[0]);
assign R4_en = ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & ~Rd[0] | EXEC2 & LOAD & Rls[2] & ~Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & ~Rd[0]; assign R4_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & Rls[2] & ~Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & ~Rd[0]);
assign R5_en = ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & Rd[0] | EXEC2 & LOAD & Rls[2] & ~Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & Rd[0]; assign R5_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & ~Rd[1] & Rd[0]) | (EXEC2 & LOAD & Rls[2] & ~Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & ~Rd[1] & Rd[0]);
assign R6_en = ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & ~Rd[0] | EXEC2 & LOAD & Rls[2] & Rls[1] & ~Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & ~Rd[0]; assign R6_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & ~Rd[0]) | (EXEC2 & LOAD & Rls[2] & Rls[1] & ~Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & ~Rd[0]);
assign R7_en = ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & Rd[0] | EXEC2 & LOAD & Rls[2] & Rls[1] & Rls[0] | EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & Rd[0]; assign R7_en = (EXEC1 & ~(UJMP | JMP | STORE | LOAD | MUL | MLA | MLS | NOP | STP | POP) & Rd[2] & Rd[1] & Rd[0]) | (EXEC2 & LOAD & Rls[2] & Rls[1] & Rls[0]) | (EXEC2 & (MUL | MLA | MLS | POP) & Rd[2] & Rd[1] & Rd[0]);
assign s1[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2])); assign s1[2] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[2]) | (STORE & Rls[2]) | (PSH & Rs1[2]);
assign s1[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1])); assign s1[1] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[1]) | (STORE & Rls[1]) | (PSH & Rs1[1]);
assign s1[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0])); assign s1[0] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs1[0]) | (STORE & Rls[0]) | (PSH & Rs1[0]);
assign s2[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rs2[2]); assign s2[2] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[2]);
assign s2[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rs2[1]); assign s2[1] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[1]);
assign s2[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rs2[0]); assign s2[0] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rs2[0]);
assign s3[2] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rd[2]); assign s3[2] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rd[2]);
assign s3[1] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rd[1]); assign s3[1] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rd[1]);
assign s3[0] = EXEC1 & ((~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP)) & Rd[0]); assign s3[0] = (~(UJMP | JMP | STORE | LOAD | NOP | STP | PSH | POP) & Rd[0]);
assign s4[1] = POP | PSH; assign s4[1] = POP | PSH;
assign s4[0] = ~(LOAD | POP | PSH); assign s4[0] = ~(LOAD | POP | PSH);
assign RAMd_wren = EXEC1 & STORE; assign RAMd_wren = EXEC1 & STORE;

132
instr.mif
View file

@ -17,73 +17,73 @@
WIDTH=16; WIDTH=16;
DEPTH=2048; DEPTH=2048;
ADDRESS_RADIX=HEX; ADDRESS_RADIX=UNS;
DATA_RADIX=HEX; DATA_RADIX=HEX;
CONTENT BEGIN CONTENT BEGIN
000 : 8800; 0 : 8800;
001 : 9001; 1 : 9001;
002 : 26D0; 2 : 26D0;
003 : 291A; 3 : 291A;
004 : 2D00; 4 : 2D20;
005 : 3161; 5 : 3161;
006 : 3440; 6 : 3448;
007 : 3993; 7 : 3993;
008 : 3AA5; 8 : 3AA5;
009 : D003; 9 : D003;
00A : 3CE2; 10 : 3CE2;
00B : A003; 11 : A003;
00C : 9804; 12 : 9804;
00D : 38A5; 13 : 38A5;
00E : 3FC0; 14 : 3FC0;
00F : 419F; 15 : 419F;
010 : 304F; 16 : 304F;
011 : 5008; 17 : 5008;
012 : 5028; 18 : 5028;
013 : 284F; 19 : 284F;
014 : 43F7; 20 : 43F7;
015 : 3540; 21 : 3568;
016 : 47F5; 22 : 47F5;
017 : 484D; 23 : 484D;
018 : 8806; 24 : 8806;
019 : 0040; 25 : 0040;
01A : B800; 26 : B800;
01B : 8807; 27 : 8807;
01C : 085A; 28 : 085A;
01D : B800; 29 : B800;
01E : 8808; 30 : 8808;
01F : 0A7D; 31 : 0A7D;
020 : B800; 32 : B800;
021 : 8809; 33 : 8809;
022 : 0C53; 34 : 0C53;
023 : B801; 35 : B801;
024 : 880A; 36 : 880A;
025 : B00B; 37 : B00B;
026 : 0E70; 38 : 0E70;
027 : B800; 39 : B800;
028 : 880C; 40 : 880C;
029 : 1063; 41 : 1063;
02A : B800; 42 : B800;
02B : 880D; 43 : 880D;
02C : 126D; 44 : 126D;
02D : B800; 45 : B800;
02E : 880E; 46 : 880E;
02F : 147A; 47 : 147A;
030 : B800; 48 : B800;
031 : 880F; 49 : 880F;
032 : 5340; 50 : 5340;
033 : 53C0; 51 : 53C0;
034 : 1678; 52 : 1678;
035 : B800; 53 : B800;
036 : 1863; 54 : 1863;
037 : 1A5A; 55 : 1A5A;
038 : 1FB8; 56 : 1FB8;
039 : 7C00; 57 : 7C00;
03A : 1C77; 58 : 1C77;
03B : 204C; 59 : 204C;
03C : A810; 60 : A810;
03D : 226D; 61 : 226D;
03E : 246D; 62 : 246D;
03F : 7E00; 63 : 7E00;
[040..7FF] : 0000; [64..2047] : 0000;
END; END;