Updated ALU to use internal carry register

Also tidied up begin/end tags to reduce number of lines and improve readability

alu.v

@@ -1,25 +1,21 @@
-module alu (enable, Rd, Rs1, Rs2, opcode, carryin, mulresult, exec2, carryout, mul1, mul2, Rout, jump);
+module alu (enable, Rd, Rs1, Rs2, opcode, mulresult, exec2, mul1, mul2, Rout, jump, carry);
 
 input enable; // active LOW, disables the ALU during load/store operations so that undefined behaviour does not occur
 input signed [15:0] Rd; // input destination register
 input signed [15:0] Rs1; // input source register 1
 input signed [15:0] Rs2; // input source register 2
 input [5:0] opcode; // opcode is fed in from instruction using wires outside ALU
-input carryin; // current status of carry flip-flop
 input signed [31:0] mulresult; // 32-bit result from multiplier
 input exec2; // Input from state machine to indicate when to take in result from multiplication
 
-output carryout; // resulting carry from operation, updated each cycle
 output reg signed [15:0] mul1; // first number to be multiplied
 output reg signed [15:0] mul2; // second number to be multiplied
 output signed [15:0] Rout; // value to be saved to destination register
 output jump; // tells decoder whether Jump condition is true
-
+output reg carry; // Internal carry register that is updated during appropriate opcodes, also provides output for debugging
-// load and store are handled outside the ALU so those opcodes can be ignored. All other instructions have a consistent format.
 
 reg signed [16:0] alusum; // extra bit to hold carry from operations other than Multiply
 assign Rout = alusum [15:0];
-assign carryout = alusum [16];
 assign jump = (alusum[16] && ((opcode[5:2] == 4'b0000) | (opcode[5:2] == 4'b0001) | (opcode[5:2] == 4'b0010)));
 reg [15:0] mulextra;
 
@@ -36,8 +32,7 @@ assign JC8 = (Rs1 < 0);
 
 always @(*)
 	begin
-		if(!enable)
+		if(!enable) begin
-			begin
 			case (opcode)
 				6'b000000: alusum = {1'b1, Rd}; // JMP Unconditional Jump, first bit high to indicate jump and passes through Rd
 				
@@ -61,51 +56,60 @@ always @(*)
 				6'b010010: alusum = {1'b0, Rs1 ~^ Rs2}; // XNR Bitwise XNOR
 				6'b010011: alusum = {1'b0, Rs1}; // MOV Move (Rd = Rs1)
 				
-				6'b010100: alusum = {1'b0, Rs1} + {1'b0, Rs2}; // ADD Add (Rd = Rs1 + Rs2)
+				6'b010100: begin
-				6'b010101: alusum = {1'b0, Rs1} + {1'b0, Rs2} + carryin; // ADC Add w/ Carry (Rd = Rs1 + Rs2 + C)
+						alusum = {1'b0, Rs1} + {1'b0, Rs2}; // ADD Add (Rd = Rs1 + Rs2)
-				6'b010110: alusum = {1'b0, Rs1} + {17'b00000000000000001}; // ADO Add 1 (Rd = Rd + 1)
+						carry = alusum[16];
+					end
+				6'b010101: begin
+						alusum = {1'b0, Rs1} + {1'b0, Rs2} + carry; // ADC Add w/ Carry (Rd = Rs1 + Rs2 + C)
+						carry = alusum[16];
+					end
+				6'b010110: begin
+						alusum = {1'b0, Rs1} + {17'b00000000000000001}; // ADO Add 1 (Rd = Rd + 1)
+						carry = alusum[16];
+					end
 				6'b010111: ;
 				
-				6'b011000: alusum = {1'b0, Rs1} - {1'b0, Rs2}; // SUB Subtract (Rd = Rs1 - Rs2)
+				6'b011000: begin
-				6'b011001: alusum = {1'b0, Rs1} - {1'b0, Rs2} + carryin - {17'b00000000000000001}; // SBC Subtract w/ Carry (Rd = Rs1 - Rs2 + C - 1)
+						alusum = {1'b0, Rs1} - {1'b0, Rs2}; // SUB Subtract (Rd = Rs1 - Rs2)
-				6'b011010: alusum = {1'b0, Rs1} - {17'b00000000000000001}; // SBO Subtract 1 (Rd = Rd - 1)
+						carry = alusum[16];
+					end
+				6'b011001: begin
+						alusum = {1'b0, Rs1} - {1'b0, Rs2} + carry - {17'b00000000000000001}; // SBC Subtract w/ Carry (Rd = Rs1 - Rs2 + C - 1)
+						carry = slusum[16];
+					end
+				6'b011010: begin
+						alusum = {1'b0, Rs1} - {17'b00000000000000001}; // SBO Subtract 1 (Rd = Rd - 1)
+						carry = alusum[16];
+					end
 				6'b011011: ;
 				
-				6'b011100: // MUL Multiply (Rd = Rs1 * Rs2)
+				6'b011100: begin // MUL Multiply (Rd = Rs1 * Rs2)
-					begin
+						if(!exec2) begin
-						if(!exec2)
-							begin
 								mul1 = Rs1;
 								mul2 = Rs2;
 							end
-						else
+						else begin
-							begin
 								alusum[16] = 1'b0;
 								{mulextra, alusum[15:0]} = mulresult;
 							end
 					end
-				6'b011101: // MLA Multiply and Add  (Rd = Rs2 + (Rd * Rs1))
+				6'b011101: begin // MLA Multiply and Add  (Rd = Rs2 + (Rd * Rs1))
-					begin
+						if(!exec2) begin
-						if(!exec2)
-							begin
 								mul1 = Rs1;
 								mul2 = Rs2;
 							end
-						else
+						else begin
-							begin
 								alusum[16] = 1'b0;
 								{mulextra, alusum[15:0]} = mulresult + {16'h0000, Rs2};
 							end
 					end
-				6'b011110: // MLS Multiply and Subtract (Rd = Rs2 - (Rd * Rs1)[15:0])
+				6'b011110: begin // MLS Multiply and Subtract (Rd = Rs2 - (Rd * Rs1)[15:0])
-					begin
+						if(!exec2) begin
-						if(!exec2)
-							begin
 								mul1 = Rs1;
 								mul2 = Rs2;
 							end
-						else
+						else begin
-							begin
 								alusum = {1'b0, Rs2 - mulresult[15:0]};
 							end
 					end
@@ -117,7 +121,7 @@ always @(*)
 				6'b100011: ;
 				
 				6'b100100: alusum = {1'b0, (Rs1 >> Rs2[3:0]) | (Rs1 << (16 - Rs2[3:0]))}; // ROR Shift Right Loop (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Rs1[15])
-				6'b100101: alusum = ({Rs1, carryin} >> (Rs2 % 17)) | ({Rs1, carryin} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
+				6'b100101: alusum = ({Rs1, carry} >> (Rs2 % 17)) | ({Rs1, carry} << (17 - (Rs2 % 17)));// RRC Shift Right Loop w/ Carry (Rd = Rs1 shifted right by Rs2, but Rs1[0] -> Carry & Carry -> Rs1[15])
 				6'b100110: ;
 				6'b100111: ;
 				
@@ -127,8 +131,7 @@ always @(*)
 				default: ; // During Load & Store as well as undefined opcodes
 			endcase;
 			end
-		else
+		else begin
-			begin
 				alusum = {1'b0, 16'h0000}; // Bring output low during Load/Store so it does not interfere
 			end
 	end