ELEC40006-P1-CW/ram_instr.qip

set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "19.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_instr.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_instr.bsf"]
Working on datapath 2020-05-27 10:10:13 +00:00			`set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"`
Final State before Pipelining Debug Complete, data and instruction mifs + ram files. Test program checked 2020-06-09 21:45:20 +00:00			`set_global_assignment -name IP_TOOL_VERSION "19.1"`
Working on datapath 2020-05-27 10:10:13 +00:00			`set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"`
			`set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_instr.v"]`
			`set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_instr.bsf"]`