mirror of
https://github.com/supleed2/EIE4-FYP.git
synced 2024-11-09 20:05:49 +00:00
Aadi Desai
2829a32dc6
Rename modules for clarity Move LiteX modules into `modules/` Move extras into `notes/`
36 lines
1.1 KiB
Python
36 lines
1.1 KiB
Python
from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.doc import ModuleDoc
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# Test RGB Module ----------------------------------------------------------------------------------
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class TestRgb(Module, AutoCSR, ModuleDoc):
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"""
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RGB LED Test Module
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Set an RGB value and this SystemVerilog block will handle PWM pulse generation to set the on-board LED to that colour.
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"""
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def __init__(self, platform, pads):
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self.pads = pads
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self._out = CSRStorage(size = 24, description="Led Output(s) Value (24-bit RGB)",
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fields = [
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CSRField("ledb", size = 8, description = "LED Blue Brightness"),
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CSRField("ledg", size = 8, description = "LED Green Brightness"),
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CSRField("ledr", size = 8, description = "LED Red Brightness"),
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])
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# # #
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leds = Signal(3)
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self.comb += pads.eq(~leds)
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self.specials += Instance("ledPwm",
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i_clk = ClockSignal(),
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i_rgb = self._out.storage,
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o_ledr = leds[0],
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o_ledg = leds[1],
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o_ledb = leds[2]
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)
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platform.add_source("rtl/ledPwm.sv")
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