mirror of
https://github.com/supleed2/EIE4-FYP.git
synced 2024-11-10 04:15:49 +00:00
Aadi Desai
2829a32dc6
Rename modules for clarity Move LiteX modules into `modules/` Move extras into `notes/`
39 lines
1.2 KiB
Python
39 lines
1.2 KiB
Python
from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.doc import ModuleDoc
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# Test RGB Module ----------------------------------------------------------------------------------
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class DacAttenuation(Module, AutoCSR, ModuleDoc):
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"""
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DAC Attenuation Control Module
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Set the Attenuation of the PCM1780 DAC
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"""
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def __init__(self, platform, pads):
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platform.add_source("rtl/dacAttenuation.sv")
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self.pads = pads
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self.atten = CSRStorage(size = 8, reset = 128, description = "PCM1780: Attenuation Control")
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self.m_sel_n = Signal()
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self.m_clock = Signal()
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self.m_data = Signal()
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# # #
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self.specials += Instance("dacAttenuation",
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i_i_clk48 = ClockSignal(),
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i_i_rst48_n = ~ResetSignal(),
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i_i_valid = self.atten.re,
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i_i_atten = self.atten.storage,
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o_o_sel_n = self.m_sel_n,
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o_o_clock = self.m_clock,
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o_o_data = self.m_data,
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)
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self.comb += self.pads.ms.eq(self.m_sel_n) # Mode Bus: Select (Active Low)
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self.comb += self.pads.mc.eq(self.m_clock) # Mode Bus: Clock
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self.comb += self.pads.md.eq(self.m_data) # Mode Bus: Data
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