mirror of
https://github.com/supleed2/EIE4-FYP.git
synced 2024-11-13 21:45:48 +00:00
Aadi Desai
2829a32dc6
Rename modules for clarity Move LiteX modules into `modules/` Move extras into `notes/`
35 lines
1.1 KiB
Python
35 lines
1.1 KiB
Python
from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.doc import ModuleDoc
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# Test RGB Module ----------------------------------------------------------------------------------
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class TestPropagation(Module, AutoCSR, ModuleDoc):
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"""
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Propagation Test Module
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Test propagation delay of the genSaw block
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"""
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def __init__(self, platform):
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platform.add_source("rtl/cordic.sv")
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platform.add_source("rtl/saw2sin.sv")
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self.targ0 = CSRStorage(size = 24, description = "Oscillator 0: Target Frequency of the Sawtooth Wave")
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self.wave0 = CSRStorage(size = 8, description = "Oscillator 0: Waveform to Output")
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self.delay = Signal(3) # Update i_saw after 2^3 = 8 cycles
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self.i_saw = Signal(16)
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self.o_sin = Signal(16)
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# # #
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self.sync += self.delay.eq(self.delay + 1)
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self.sync += If(self.delay == 0, self.i_saw.eq(self.i_saw + 1))
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self.specials += Instance("saw2sin",
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i_i_clk = ClockSignal(),
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i_i_saw = self.i_saw,
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o_o_sin = self.o_sin,
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)
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