Commit graph

13 commits

Author SHA1 Message Date
Aadi Desai c4469cd6f6
Flip MSB of square wave, avoid DAC automute 2023-05-18 16:19:53 +01:00
Aadi Desai 6381cb53a8
Optimise triangle wave gen and add comments 2023-05-18 12:42:09 +01:00
Aadi Desai a17429c105
Support selecting waveform in genSaw 2023-05-18 12:35:39 +01:00
Aadi Desai 81cf1ebc5c
Replace assign with always_comb in rtl/
Update to better match IEEE1800-2017
2023-05-18 12:01:56 +01:00
Aadi Desai 06fc184cc5
Working version of dac driver
Output limited to 16bit as the set bitclock rate is too low for 24bit
Main work was on timing issues and inconsistent output
2023-05-16 22:12:41 +01:00
Aadi Desai 0ce0835a45
Working version of sample generator 2023-05-16 22:11:17 +01:00
Aadi Desai 5b66d01ac6
Add comments to sawtooth generator 2023-05-12 14:00:13 +01:00
Aadi Desai 3edc1f92d7
Add DAC Driver block 2023-03-11 18:05:03 +00:00
Aadi Desai a473a6ff9c
Add Sawtooth Generator Block 2023-03-11 18:04:53 +00:00
Aadi Desai 0f61a6d19a
Add pcmfifo SystemVerilog module 2023-03-10 17:47:39 +00:00
Aadi Desai 529efcaf9f
Add pwm module to set LED colour from LiteX Console 2023-03-03 17:05:00 +00:00
Aadi Desai d960053a7e
Update flip.sv to cycle across colours using 48MHz 2023-03-03 17:04:22 +00:00
Aadi Desai e1b0d5c28c
Add testing SystemVerilog and LiteX Module 2023-02-26 19:40:56 +00:00