Commit graph

53 commits

Author SHA1 Message Date
Aadi Desai e1b0d5c28c
Add testing SystemVerilog and LiteX Module 2023-02-26 19:40:56 +00:00
Aadi Desai 9322fe0fd4
Add readme notes 2023-02-26 14:59:50 +00:00
Aadi Desai 6d8c1059fa
Initial commit to prevent data loss
such as in the case of sudden laptop death
2023-02-05 00:56:34 +00:00