Add testing SystemVerilog and LiteX Module

rtl/flip.sv

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+module flip
+( input  var       clk
+, output var       ledr
+, output var       ledg
+, output var       ledb
+);
+
+logic [31:0] counter;
+
+always_ff @(posedge clk)
+  counter <= counter + 1;
+
+assign {ledr, ledg, ledb} = ~counter[27:25];
+
+endmodule

testLED.py

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+from migen import *
+from migen.genlib.misc import WaitTimer
+
+from litex.soc.interconnect.csr import *
+
+# Test LED Module ----------------------------------------------------------------------------------
+
+class TestLed(Module, AutoCSR):
+    def __init__(self, platform, pads):
+        self.pads     = pads
+        leds   = Signal(3)
+        self.comb += pads.eq(leds)
+        self.specials += Instance("flip",
+            i_clk = ClockSignal(),
+            o_ledr = leds[0],
+            o_ledg = leds[1],
+            o_ledb = leds[2]
+        )
+        platform.add_source("rtl/flip.sv")
+