From e1b0d5c28c96450fb322550493fbaf41d197ae84 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Sun, 26 Feb 2023 19:40:56 +0000
Subject: [PATCH] Add testing SystemVerilog and LiteX Module

---
 rtl/flip.sv | 15 +++++++++++++++
 testLED.py  | 20 ++++++++++++++++++++
 2 files changed, 35 insertions(+)
 create mode 100644 rtl/flip.sv
 create mode 100644 testLED.py

diff --git a/rtl/flip.sv b/rtl/flip.sv
new file mode 100644
index 0000000..4df8f2c
--- /dev/null
+++ b/rtl/flip.sv
@@ -0,0 +1,15 @@
+module flip
+( input  var       clk
+, output var       ledr
+, output var       ledg
+, output var       ledb
+);
+
+logic [31:0] counter;
+
+always_ff @(posedge clk)
+  counter <= counter + 1;
+
+assign {ledr, ledg, ledb} = ~counter[27:25];
+
+endmodule
diff --git a/testLED.py b/testLED.py
new file mode 100644
index 0000000..6026162
--- /dev/null
+++ b/testLED.py
@@ -0,0 +1,20 @@
+from migen import *
+from migen.genlib.misc import WaitTimer
+
+from litex.soc.interconnect.csr import *
+
+# Test LED Module ----------------------------------------------------------------------------------
+
+class TestLed(Module, AutoCSR):
+    def __init__(self, platform, pads):
+        self.pads     = pads
+        leds   = Signal(3)
+        self.comb += pads.eq(leds)
+        self.specials += Instance("flip",
+            i_clk = ClockSignal(),
+            o_ledr = leds[0],
+            o_ledg = leds[1],
+            o_ledb = leds[2]
+        )
+        platform.add_source("rtl/flip.sv")
+