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Update flip.sv to cycle across colours using 48MHz

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Aadi Desai 2023-03-03 17:04:22 +00:00
parent 81b2d004a5
commit d960053a7e
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1 changed files with 21 additions and 7 deletions
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28
rtl/flip.sv
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@ -1,15 +1,29 @@
`default_nettype none
module flip
( input var clk
, output var ledr
, output var ledg
, output var ledb
( input var i_clk
, output var o_ledr
, output var o_ledg
, output var o_ledb
);
logic [31:0] counter;
logic [2:0] leds;
always_ff @(posedge clk)
counter <= counter + 1;
always_ff @(posedge i_clk)
if (counter > 32'd192_000_000) counter <= '0;
else counter <= counter + 1;
assign {ledr, ledg, ledb} = ~counter[27:25];
always_comb
if (counter < 24_000_000) {leds} = 3'b000;
else if (counter < 48_000_000) {leds} = 3'b001;
else if (counter < 72_000_000) {leds} = 3'b010;
else if (counter < 96_000_000) {leds} = 3'b011;
else if (counter < 120_000_000) {leds} = 3'b100;
else if (counter < 144_000_000) {leds} = 3'b101;
else if (counter < 168_000_000) {leds} = 3'b110;
else {leds} = 3'b111;
assign {o_ledr, o_ledg, o_ledb} = leds;
endmodule