supleed2/EIE4-FYP
1
0
Fork 0
mirror of https://github.com/supleed2/EIE4-FYP.git synced 2024-09-19 21:36:17 +00:00
Code Issues Packages Projects Releases Wiki Activity

Update flip.sv to cycle across colours using 48MHz

Browse source
This commit is contained in:
Aadi Desai 2023-03-03 17:04:22 +00:00
parent 81b2d004a5
commit d960053a7e
No known key found for this signature in database
1 changed files with 21 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

28
rtl/flip.sv
View file

@ -1,15 +1,29 @@
`default_nettype none
module flip module flip
( input var clk ( input var i_clk
, output var ledr , output var o_ledr
, output var ledg , output var o_ledg
, output var ledb , output var o_ledb
); );
logic [31:0] counter; logic [31:0] counter;
logic [2:0] leds;
always_ff @(posedge clk) always_ff @(posedge i_clk)
counter <= counter + 1; if (counter > 32'd192_000_000) counter <= '0;
else counter <= counter + 1;
assign {ledr, ledg, ledb} = ~counter[27:25]; always_comb
if (counter < 24_000_000) {leds} = 3'b000;
else if (counter < 48_000_000) {leds} = 3'b001;
else if (counter < 72_000_000) {leds} = 3'b010;
else if (counter < 96_000_000) {leds} = 3'b011;
else if (counter < 120_000_000) {leds} = 3'b100;
else if (counter < 144_000_000) {leds} = 3'b101;
else if (counter < 168_000_000) {leds} = 3'b110;
else {leds} = 3'b111;
assign {o_ledr, o_ledg, o_ledb} = leds;
endmodule endmodule