supleed2/EIE4-FYP
1
0
Fork 0
mirror of https://github.com/supleed2/EIE4-FYP.git synced 2024-11-10 04:15:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Add debug UART port extension

Browse source
This commit is contained in:
Aadi Desai 2023-05-11 01:46:26 +01:00
parent bb1e27f787
commit bda6a825de
No known key found for this signature in database
1 changed files with 5 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
make.py
View file

@ -223,6 +223,11 @@ class BaseSoC(SoCCore):
Subsignal("mc", Pins("R17")), # IO_SCK Subsignal("mc", Pins("R17")), # IO_SCK
Subsignal("md", Pins("N16")), # IO_MOSI Subsignal("md", Pins("N16")), # IO_MOSI
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
),
("debug_uart", 0,
Subsignal("tx", Pins("B8")), # IO_10
Subsignal("rx", Pins("C8")), # IO_9
IOStandard("LVCMOS33")
) )
]) ])