From bda6a825de9aa6ade2868cfaf10e9b215b6dfbb0 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Thu, 11 May 2023 01:46:26 +0100
Subject: [PATCH] Add debug UART port extension

---
 make.py | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/make.py b/make.py
index 76fc12c..b93057d 100755
--- a/make.py
+++ b/make.py
@@ -223,6 +223,11 @@ class BaseSoC(SoCCore):
                 Subsignal("mc", Pins("R17")), # IO_SCK
                 Subsignal("md", Pins("N16")), # IO_MOSI
                 IOStandard("LVCMOS33")
+            ),
+            ("debug_uart", 0,
+                Subsignal("tx", Pins("B8")), # IO_10
+                Subsignal("rx", Pins("C8")), # IO_9
+                IOStandard("LVCMOS33")
             )
         ])