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Add debug UART port extension

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Aadi Desai 2023-05-11 01:46:26 +01:00
parent bb1e27f787
commit bda6a825de
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1 changed files with 5 additions and 0 deletions
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5
make.py
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@ -223,6 +223,11 @@ class BaseSoC(SoCCore):
Subsignal("mc", Pins("R17")), # IO_SCK
Subsignal("md", Pins("N16")), # IO_MOSI
IOStandard("LVCMOS33")
),
("debug_uart", 0,
Subsignal("tx", Pins("B8")), # IO_10
Subsignal("rx", Pins("C8")), # IO_9
IOStandard("LVCMOS33")
)
])