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Add docs link for MigenAsyncFIFO to readme
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make.py
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make.py
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@ -237,7 +237,7 @@ class BaseSoC(SoCCore):
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pads = platform.request("dac_pcm")
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)
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# LiteScope Analyzer -----------------------------------------------------------------------
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# LiteScope Analyzer -----------------------------------------------------------------------
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self.add_uartbone(name="debug_uart", baudrate=921600)
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [
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@ -9,6 +9,7 @@
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### Useful links
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- [API Reference migen, AsyncFIFO](https://m-labs.hk/migen/manual/reference.html#module-migen.genlib.fifo)
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- [Guide on adding a new core (incomplete)](https://github.com/enjoy-digital/litex/wiki/Add-A-New-Core)
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- [Using LiteEth on ECP5](https://github.com/enjoy-digital/liteeth/issues/66)
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- [Adding HW modules](https://github.com/enjoy-digital/litex/issues/746), lots more info in issue
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