diff --git a/make.py b/make.py
index f812868..730129e 100755
--- a/make.py
+++ b/make.py
@@ -237,7 +237,7 @@ class BaseSoC(SoCCore):
             pads     = platform.request("dac_pcm")
         )
 
-                # LiteScope Analyzer -----------------------------------------------------------------------
+        # LiteScope Analyzer -----------------------------------------------------------------------
         self.add_uartbone(name="debug_uart", baudrate=921600)
         from litescope import LiteScopeAnalyzer
         analyzer_signals = [
diff --git a/readme.md b/readme.md
index 29907a1..106a093 100644
--- a/readme.md
+++ b/readme.md
@@ -9,6 +9,7 @@
 
 ### Useful links
 
+- [API Reference migen, AsyncFIFO](https://m-labs.hk/migen/manual/reference.html#module-migen.genlib.fifo)
 - [Guide on adding a new core (incomplete)](https://github.com/enjoy-digital/litex/wiki/Add-A-New-Core)
   - [Using LiteEth on ECP5](https://github.com/enjoy-digital/liteeth/issues/66)
   - [Adding HW modules](https://github.com/enjoy-digital/litex/issues/746), lots more info in issue