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Add always_ff in saw2sin to fix glitches

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Aadi Desai 2023-06-04 14:14:05 +01:00
parent 6d670dc903
commit aac2ad4c62
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2 changed files with 5 additions and 3 deletions
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3
rtl/genSaw.sv
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@ -46,7 +46,8 @@ always_comb triangle = saw[15] ? {~saw[14:0], 1'b1} : {saw[14:0], 1'b0}; // Tria
logic [15:0] sine; logic [15:0] sine;
saw2sin m_saw2sin // Instantiate saw2sin module saw2sin m_saw2sin // Instantiate saw2sin module
( .i_saw(saw) ( .i_clk(i_clk48)
, .i_saw(saw)
, .o_sin(sine) , .o_sin(sine)
); );

5
rtl/saw2sin.sv
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@ -1,7 +1,8 @@
`default_nettype none `default_nettype none
module saw2sin module saw2sin
( input var [15:0] i_saw ( input var i_clk
, input var [15:0] i_saw
, output var [15:0] o_sin , output var [15:0] o_sin
); );
@ -23,7 +24,7 @@ cordic cordic
); );
logic [16:0] sin; logic [16:0] sin;
always_comb sin = reverse always_ff @(posedge i_clk) sin <= reverse
? (invert ? ~{1'b1, qsin[15:0]} // Reverse, Invert ? (invert ? ~{1'b1, qsin[15:0]} // Reverse, Invert
: {1'b1, qsin[15:0]} + 17'd1) // Reverse, Normal : {1'b1, qsin[15:0]} + 17'd1) // Reverse, Normal
: (invert ? ~{1'b1, qsin[15:0]} + 17'd2 // Normal, Invert : (invert ? ~{1'b1, qsin[15:0]} + 17'd2 // Normal, Invert