diff --git a/rtl/genSaw.sv b/rtl/genSaw.sv
index ee025e5..86aa130 100644
--- a/rtl/genSaw.sv
+++ b/rtl/genSaw.sv
@@ -46,7 +46,8 @@ always_comb triangle = saw[15] ? {~saw[14:0], 1'b1} : {saw[14:0], 1'b0}; // Tria
 
 logic [15:0] sine;
 saw2sin m_saw2sin // Instantiate saw2sin module
-( .i_saw(saw)
+( .i_clk(i_clk48)
+, .i_saw(saw)
 , .o_sin(sine)
 );
 
diff --git a/rtl/saw2sin.sv b/rtl/saw2sin.sv
index c74347d..db66ee9 100644
--- a/rtl/saw2sin.sv
+++ b/rtl/saw2sin.sv
@@ -1,7 +1,8 @@
 `default_nettype none
 
 module saw2sin
-( input  var [15:0] i_saw
+( input  var        i_clk
+, input  var [15:0] i_saw
 , output var [15:0] o_sin
 );
 
@@ -23,7 +24,7 @@ cordic cordic
 );
 
 logic [16:0] sin;
-always_comb sin = reverse
+always_ff @(posedge i_clk) sin <= reverse
   ? (invert ? ~{1'b1, qsin[15:0]}          // Reverse, Invert
             : {1'b1, qsin[15:0]} + 17'd1)  // Reverse, Normal
   : (invert ? ~{1'b1, qsin[15:0]} + 17'd2  // Normal, Invert