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Replace assign with always_comb in rtl/

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Update to better match IEEE1800-2017
This commit is contained in:
Aadi Desai 2023-05-18 12:01:56 +01:00
parent afcf1093be
commit 81cf1ebc5c
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3 changed files with 7 additions and 7 deletions
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2
rtl/flip.sv
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@ -24,6 +24,6 @@ always_comb
else if (counter < 168_000_000) {leds} = 3'b110; else if (counter < 168_000_000) {leds} = 3'b110;
else {leds} = 3'b111; else {leds} = 3'b111;
assign {o_ledr, o_ledg, o_ledb} = leds; always_comb {o_ledr, o_ledg, o_ledb} = leds;
endmodule endmodule

6
rtl/flipPwm.sv
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@ -13,8 +13,8 @@ logic [7:0] counter;
always_ff @(posedge clk) always_ff @(posedge clk)
counter <= counter + 1; counter <= counter + 1;
assign ledr = (rgb[23:16] > counter); always_comb ledr = (rgb[23:16] > counter);
assign ledg = (rgb[15: 8] > counter); always_comb ledg = (rgb[15: 8] > counter);
assign ledb = (rgb[ 7: 0] > counter); always_comb ledb = (rgb[ 7: 0] > counter);
endmodule endmodule

6
rtl/genSaw.sv
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@ -24,13 +24,13 @@ logic clk_48k_past;
always_ff @(posedge i_clk48) // Track rising / falling edge of 48kHz clock always_ff @(posedge i_clk48) // Track rising / falling edge of 48kHz clock
clk_48k_past <= clk_48k; clk_48k_past <= clk_48k;
assign o_pulse = clk_48k && !clk_48k_past; // Detect rising edge of 48kHz clock always_comb o_pulse = clk_48k && !clk_48k_past; // Detect rising edge of 48kHz clock
logic [23:0] int_saw_step; logic [23:0] int_saw_step;
assign int_saw_step = (24'd699 * i_targetf); // Sawtooth step calc from input target freq always_comb int_saw_step = (24'd699 * i_targetf); // Sawtooth step calc from input target freq
logic [15:0] saw_step; logic [15:0] saw_step;
assign saw_step = {1'b0, int_saw_step[23:9]}; // Shift step right correctly (2^9) always_comb saw_step = {1'b0, int_saw_step[23:9]}; // Shift step right correctly (2^9)
always_ff @(posedge clk_48k) // Generate new sample on rising edge of 48kHz clock always_ff @(posedge clk_48k) // Generate new sample on rising edge of 48kHz clock
if (!i_rst48_n) o_sample <= '0; if (!i_rst48_n) o_sample <= '0;