From 81cf1ebc5cf6da563f3480d63dc890337fbfdcc9 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Thu, 18 May 2023 12:01:56 +0100
Subject: [PATCH] Replace `assign` with `always_comb` in rtl/

Update to better match IEEE1800-2017
---
 rtl/flip.sv    | 2 +-
 rtl/flipPwm.sv | 6 +++---
 rtl/genSaw.sv  | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/rtl/flip.sv b/rtl/flip.sv
index 34ffb66..d9a3347 100644
--- a/rtl/flip.sv
+++ b/rtl/flip.sv
@@ -24,6 +24,6 @@ always_comb
   else if (counter < 168_000_000) {leds} = 3'b110;
   else {leds} = 3'b111;
 
-assign {o_ledr, o_ledg, o_ledb} = leds;
+always_comb {o_ledr, o_ledg, o_ledb} = leds;
 
 endmodule
diff --git a/rtl/flipPwm.sv b/rtl/flipPwm.sv
index 959855a..30a7034 100644
--- a/rtl/flipPwm.sv
+++ b/rtl/flipPwm.sv
@@ -13,8 +13,8 @@ logic [7:0] counter;
 always_ff @(posedge clk)
   counter <= counter + 1;
 
-assign ledr = (rgb[23:16] > counter);
-assign ledg = (rgb[15: 8] > counter);
-assign ledb = (rgb[ 7: 0] > counter);
+always_comb ledr = (rgb[23:16] > counter);
+always_comb ledg = (rgb[15: 8] > counter);
+always_comb ledb = (rgb[ 7: 0] > counter);
 
 endmodule
diff --git a/rtl/genSaw.sv b/rtl/genSaw.sv
index 493f22b..d0dc2c0 100644
--- a/rtl/genSaw.sv
+++ b/rtl/genSaw.sv
@@ -24,13 +24,13 @@ logic clk_48k_past;
 always_ff @(posedge i_clk48) // Track rising / falling edge of 48kHz clock
   clk_48k_past <= clk_48k;
 
-assign o_pulse = clk_48k && !clk_48k_past; // Detect rising edge of 48kHz clock
+always_comb o_pulse = clk_48k && !clk_48k_past; // Detect rising edge of 48kHz clock
 
 logic [23:0] int_saw_step;
-assign int_saw_step = (24'd699 * i_targetf); // Sawtooth step calc from input target freq
+always_comb int_saw_step = (24'd699 * i_targetf); // Sawtooth step calc from input target freq
 
 logic [15:0] saw_step;
-assign saw_step = {1'b0, int_saw_step[23:9]}; // Shift step right correctly (2^9)
+always_comb saw_step = {1'b0, int_saw_step[23:9]}; // Shift step right correctly (2^9)
 
 always_ff @(posedge clk_48k) // Generate new sample on rising edge of 48kHz clock
   if (!i_rst48_n)    o_sample <= '0;