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Fix USB reset from PLL

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Aadi Desai 2023-06-25 12:57:01 +01:00
parent dd842c108e
commit 783dc57e4f
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1 changed files with 2 additions and 2 deletions
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4
make.py
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@ -106,8 +106,8 @@ class _CRGSDRAM(LiteXModule):
pll.register_clkin(clk48, 48e6) pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 24e6) pll.create_clkout(self.cd_init, 24e6)
pll.create_clkout(self.cd_usb_48, 48e6) pll.create_clkout(self.cd_usb_48, 48e6, with_reset=False)
pll.create_clkout(self.cd_usb_12, 12e6) pll.create_clkout(self.cd_usb_12, 12e6, with_reset=False)
self.specials += [ self.specials += [
Instance("ECLKBRIDGECS", Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk, i_CLK0 = self.cd_sys2x_i.clk,