From 783dc57e4ff8c6ccf70566ee4166cdb65346d096 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Sun, 25 Jun 2023 12:57:01 +0100
Subject: [PATCH] Fix USB reset from PLL

---
 make.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/make.py b/make.py
index cf98b60..7557a23 100755
--- a/make.py
+++ b/make.py
@@ -106,8 +106,8 @@ class _CRGSDRAM(LiteXModule):
         pll.register_clkin(clk48, 48e6)
         pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
         pll.create_clkout(self.cd_init, 24e6)
-        pll.create_clkout(self.cd_usb_48, 48e6)
-        pll.create_clkout(self.cd_usb_12, 12e6)
+        pll.create_clkout(self.cd_usb_48, 48e6, with_reset=False)
+        pll.create_clkout(self.cd_usb_12, 12e6, with_reset=False)
         self.specials += [
             Instance("ECLKBRIDGECS",
                 i_CLK0   = self.cd_sys2x_i.clk,