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Add LiteX Docs link to readme
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- [Migen Guide](https://m-labs.hk/migen/manual/fhdl.html)
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- [Migen Guide](https://m-labs.hk/migen/manual/fhdl.html)
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- [LiteX SPI Core](https://github.com/litex-hub/litespi)
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- [LiteX SPI Core](https://github.com/litex-hub/litespi)
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- [FoMu Example of using external Verilog](https://github.com/im-tomu/foboot/blob/c7ee25b3d10dba0c1df67e793c4e2585577e7a39/hw/foboot-bitstream.py#L507-L537)
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- [FoMu Example of using external Verilog](https://github.com/im-tomu/foboot/blob/c7ee25b3d10dba0c1df67e793c4e2585577e7a39/hw/foboot-bitstream.py#L507-L537)
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- [Automatic LiteX Documentation](https://github.com/enjoy-digital/litex/wiki/SoC-Documentation)
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- [Migen (base for litex) GitHub Repository](https://github.com/m-labs/migen)
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- [Migen (base for litex) GitHub Repository](https://github.com/m-labs/migen)
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- [Litex Wiki: reusing SV or other cores](https://github.com/enjoy-digital/litex/wiki/Reuse-a-(System)Verilog,-VHDL,-(n)Migen,-Spinal-HDL,-Chisel-core)
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- [Litex Wiki: reusing SV or other cores](https://github.com/enjoy-digital/litex/wiki/Reuse-a-(System)Verilog,-VHDL,-(n)Migen,-Spinal-HDL,-Chisel-core)
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- [Litex for Hardware Engineers](https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers)
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- [Litex for Hardware Engineers](https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers)
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