From 740316a47f95fb6f8549df3e5715661d42c0763f Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Fri, 3 Mar 2023 17:05:22 +0000
Subject: [PATCH] Add LiteX Docs link to readme

---
 readme.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/readme.md b/readme.md
index dcfbcea..f36d63b 100644
--- a/readme.md
+++ b/readme.md
@@ -12,6 +12,7 @@
   - [Migen Guide](https://m-labs.hk/migen/manual/fhdl.html)
   - [LiteX SPI Core](https://github.com/litex-hub/litespi)
   - [FoMu Example of using external Verilog](https://github.com/im-tomu/foboot/blob/c7ee25b3d10dba0c1df67e793c4e2585577e7a39/hw/foboot-bitstream.py#L507-L537)
+  - [Automatic LiteX Documentation](https://github.com/enjoy-digital/litex/wiki/SoC-Documentation)
 - [Migen (base for litex) GitHub Repository](https://github.com/m-labs/migen)
 - [Litex Wiki: reusing SV or other cores](https://github.com/enjoy-digital/litex/wiki/Reuse-a-(System)Verilog,-VHDL,-(n)Migen,-Spinal-HDL,-Chisel-core)
 - [Litex for Hardware Engineers](https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers)